KR100262434B1 - 쌍방향 전송형 기억장치 및 메모리의 입출력 제어방법 - Google Patents
쌍방향 전송형 기억장치 및 메모리의 입출력 제어방법 Download PDFInfo
- Publication number
- KR100262434B1 KR100262434B1 KR1019970043250A KR19970043250A KR100262434B1 KR 100262434 B1 KR100262434 B1 KR 100262434B1 KR 1019970043250 A KR1019970043250 A KR 1019970043250A KR 19970043250 A KR19970043250 A KR 19970043250A KR 100262434 B1 KR100262434 B1 KR 100262434B1
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- mode
- data
- address
- filo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
- G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Shift Register Type Memory (AREA)
- Memory System (AREA)
- Image Input (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP97-037683 | 1997-02-21 | ||
| JP9037683A JPH10241354A (ja) | 1997-02-21 | 1997-02-21 | 双方向転送型記憶装置及びメモリの入出力制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980069917A KR19980069917A (ko) | 1998-10-26 |
| KR100262434B1 true KR100262434B1 (ko) | 2000-08-01 |
Family
ID=12504406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970043250A Expired - Fee Related KR100262434B1 (ko) | 1997-02-21 | 1997-08-29 | 쌍방향 전송형 기억장치 및 메모리의 입출력 제어방법 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6067605A (enExample) |
| JP (1) | JPH10241354A (enExample) |
| KR (1) | KR100262434B1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4627823B2 (ja) * | 1999-06-25 | 2011-02-09 | 三洋電機株式会社 | 表示装置の制御回路 |
| CN1860520B (zh) * | 2003-05-20 | 2011-07-06 | 辛迪安特公司 | 数字底板 |
| US10690072B2 (en) | 2016-10-19 | 2020-06-23 | Ford Global Technologies, Llc | Method and system for catalytic conversion |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5958689A (ja) * | 1982-09-28 | 1984-04-04 | Fujitsu Ltd | 半導体記憶装置 |
| US4665482A (en) * | 1983-06-13 | 1987-05-12 | Honeywell Information Systems Inc. | Data multiplex control facility |
| JPH04248729A (ja) * | 1991-02-05 | 1992-09-04 | Fujitsu Ltd | Atm交換機 |
| KR0134177B1 (ko) * | 1992-03-24 | 1998-04-22 | Toshiba Kk | 가변장 부호의 기록 재생 장치 |
| US5442282A (en) * | 1992-07-02 | 1995-08-15 | Lsi Logic Corporation | Testing and exercising individual, unsingulated dies on a wafer |
| JPH06224933A (ja) * | 1993-01-22 | 1994-08-12 | Toshiba Corp | バッファメモリ装置 |
-
1997
- 1997-02-21 JP JP9037683A patent/JPH10241354A/ja active Pending
- 1997-06-13 US US08/876,048 patent/US6067605A/en not_active Expired - Lifetime
- 1997-08-29 KR KR1019970043250A patent/KR100262434B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6067605A (en) | 2000-05-23 |
| JPH10241354A (ja) | 1998-09-11 |
| KR19980069917A (ko) | 1998-10-26 |
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| JP2005057451A (ja) | プログラマブル論理回路 | |
| JP2005092412A (ja) | Fifo回路 |
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