KR0142797B1 - 실리콘-온-인슐레이터구조의 제조방법 - Google Patents

실리콘-온-인슐레이터구조의 제조방법

Info

Publication number
KR0142797B1
KR0142797B1 KR1019940013740A KR19940013740A KR0142797B1 KR 0142797 B1 KR0142797 B1 KR 0142797B1 KR 1019940013740 A KR1019940013740 A KR 1019940013740A KR 19940013740 A KR19940013740 A KR 19940013740A KR 0142797 B1 KR0142797 B1 KR 0142797B1
Authority
KR
South Korea
Prior art keywords
oxide film
high concentration
epitaxial layer
substrate
concentration impurity
Prior art date
Application number
KR1019940013740A
Other languages
English (en)
Korean (ko)
Inventor
김성수
Original Assignee
문정환
엘지반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체주식회사 filed Critical 문정환
Priority to KR1019940013740A priority Critical patent/KR0142797B1/ko
Priority to US08/482,002 priority patent/US5534459A/en
Priority to JP7173961A priority patent/JP2660682B2/ja
Application granted granted Critical
Publication of KR0142797B1 publication Critical patent/KR0142797B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
KR1019940013740A 1994-06-17 1994-06-17 실리콘-온-인슐레이터구조의 제조방법 KR0142797B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940013740A KR0142797B1 (ko) 1994-06-17 1994-06-17 실리콘-온-인슐레이터구조의 제조방법
US08/482,002 US5534459A (en) 1994-06-17 1995-06-07 Method for forming silicon on insulator structured
JP7173961A JP2660682B2 (ja) 1994-06-17 1995-06-19 シリコン・オン・インシュレータ(soi)の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940013740A KR0142797B1 (ko) 1994-06-17 1994-06-17 실리콘-온-인슐레이터구조의 제조방법

Publications (1)

Publication Number Publication Date
KR0142797B1 true KR0142797B1 (ko) 1998-08-17

Family

ID=19385509

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940013740A KR0142797B1 (ko) 1994-06-17 1994-06-17 실리콘-온-인슐레이터구조의 제조방법

Country Status (3)

Country Link
US (1) US5534459A (ja)
JP (1) JP2660682B2 (ja)
KR (1) KR0142797B1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
US6617226B1 (en) * 1999-06-30 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6265250B1 (en) * 1999-09-23 2001-07-24 Advanced Micro Devices, Inc. Method for forming SOI film by laser annealing
EP1495492B1 (de) * 2002-04-16 2010-06-02 Infineon Technologies AG Substrat und verfahren zum herstellen eines substrats
US7611928B2 (en) * 2002-04-16 2009-11-03 Infineon Technologies Ag Method for producing a substrate
KR100498446B1 (ko) * 2002-07-05 2005-07-01 삼성전자주식회사 Soi웨이퍼 및 그의 제조방법
FR2860919B1 (fr) * 2003-10-09 2009-09-11 St Microelectronics Sa Structures et procedes de fabrication de regions semiconductrices sur isolant

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141881A (en) * 1989-04-20 1992-08-25 Sanyo Electric Co., Ltd. Method for manufacturing a semiconductor integrated circuit
JPH04137723A (ja) * 1990-09-28 1992-05-12 Nippon Steel Corp 半導体積層基板の製造方法
KR950000660B1 (ko) * 1992-02-29 1995-01-27 현대전자산업 주식회사 고집적 소자용 미세콘택 형성방법
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
US5358881A (en) * 1993-05-19 1994-10-25 Hewlett-Packard Company Silicon topography control method
US5476800A (en) * 1994-01-31 1995-12-19 Burton; Gregory N. Method for formation of a buried layer for a semiconductor device
US5470766A (en) * 1994-06-06 1995-11-28 Integrated Devices Technology, Inc. Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors

Also Published As

Publication number Publication date
JP2660682B2 (ja) 1997-10-08
JPH08191139A (ja) 1996-07-23
US5534459A (en) 1996-07-09

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