JPWO2022038453A5 - - Google Patents

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Publication number
JPWO2022038453A5
JPWO2022038453A5 JP2022543811A JP2022543811A JPWO2022038453A5 JP WO2022038453 A5 JPWO2022038453 A5 JP WO2022038453A5 JP 2022543811 A JP2022543811 A JP 2022543811A JP 2022543811 A JP2022543811 A JP 2022543811A JP WO2022038453 A5 JPWO2022038453 A5 JP WO2022038453A5
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JP
Japan
Prior art keywords
insulating film
film
forming
oxide semiconductor
conductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2022543811A
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English (en)
Japanese (ja)
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JPWO2022038453A1 (https=
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Publication date
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Priority claimed from PCT/IB2021/057243 external-priority patent/WO2022038453A1/ja
Publication of JPWO2022038453A1 publication Critical patent/JPWO2022038453A1/ja
Publication of JPWO2022038453A5 publication Critical patent/JPWO2022038453A5/ja
Withdrawn legal-status Critical Current

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JP2022543811A 2020-08-19 2021-08-06 Withdrawn JPWO2022038453A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020138573 2020-08-19
PCT/IB2021/057243 WO2022038453A1 (ja) 2020-08-19 2021-08-06 絶縁膜の改質方法、および半導体装置の作製方法

Publications (2)

Publication Number Publication Date
JPWO2022038453A1 JPWO2022038453A1 (https=) 2022-02-24
JPWO2022038453A5 true JPWO2022038453A5 (https=) 2024-07-26

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ID=80350457

Family Applications (1)

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JP2022543811A Withdrawn JPWO2022038453A1 (https=) 2020-08-19 2021-08-06

Country Status (5)

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US (1) US20230317832A1 (https=)
JP (1) JPWO2022038453A1 (https=)
KR (1) KR20230050353A (https=)
CN (1) CN116097401A (https=)
WO (1) WO2022038453A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12295163B2 (en) 2021-12-16 2025-05-06 Asm Ip Holding B.V. Formation of gate stacks comprising a threshold voltage tuning layer
CN118156141A (zh) * 2024-03-22 2024-06-07 上海飞埃技术有限公司 薄膜晶体管的制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861334B2 (en) * 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
KR101473684B1 (ko) 2009-12-25 2014-12-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101809105B1 (ko) 2010-08-06 2017-12-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 집적 회로
US9006733B2 (en) * 2012-01-26 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing thereof
US9190525B2 (en) * 2012-07-06 2015-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including oxide semiconductor layer
JP6968567B2 (ja) * 2016-04-22 2021-11-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2019047101A (ja) * 2017-09-05 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
KR102668377B1 (ko) * 2017-12-08 2024-05-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US11031506B2 (en) * 2018-08-31 2021-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including transistor using oxide semiconductor
US11508850B2 (en) * 2018-09-05 2022-11-22 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US11929426B2 (en) * 2018-09-05 2024-03-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device

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