CN103943556A - 一种用于半导体铜互连工艺的电镀铜膜的处理方法 - Google Patents
一种用于半导体铜互连工艺的电镀铜膜的处理方法 Download PDFInfo
- Publication number
- CN103943556A CN103943556A CN201410174828.9A CN201410174828A CN103943556A CN 103943556 A CN103943556 A CN 103943556A CN 201410174828 A CN201410174828 A CN 201410174828A CN 103943556 A CN103943556 A CN 103943556A
- Authority
- CN
- China
- Prior art keywords
- copper
- annealing
- hole
- time
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010949 copper Substances 0.000 title claims abstract description 142
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 139
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 139
- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000012545 processing Methods 0.000 title abstract description 4
- 238000000137 annealing Methods 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 238000005516 engineering process Methods 0.000 claims abstract description 18
- 238000001953 recrystallisation Methods 0.000 claims abstract description 10
- 238000009713 electroplating Methods 0.000 claims description 28
- 239000010410 layer Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 22
- 238000003672 processing method Methods 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000011982 device technology Methods 0.000 claims description 4
- 230000005518 electrochemistry Effects 0.000 claims description 4
- 238000007521 mechanical polishing technique Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 235000015847 Hesperis matronalis Nutrition 0.000 description 1
- 240000004533 Hesperis matronalis Species 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种用于半导体铜互连工艺的电镀铜膜的处理方法，通过先采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，再针对已进行180℃及以下温度第一次退火处理的电镀铜膜增加一次在特定阈值之上较高温度的整体退火工艺，使铜晶粒迅速长大且铜电阻率降低，在通孔底部界面，铜的再结晶现象将使铜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟。本发明可应用于Cu/Low-k后道互连技术，且可与标准Cu/Low-k后道工艺集成兼容。
Description
技术领域
本发明涉及半导体制造领域，更具体地，涉及一种用于半导体铜互连工艺的可改善通孔与下层金属的接触电阻、进一步降低RC延迟的电镀铜膜的处理方法。
背景技术
随着半导体集成电路制造技术进入65nm及以下技术代，由各种电路源器件的临近效应引起的串扰或电磁作用已无法被忽略，并间接影响RC延迟(RC-time delay,电阻-电容延迟)，金属互连工艺中产生的RC延迟已成为整个芯片制造中的RC延迟的主要部分之一。
一方面，为了降低铜互连层间的RC延迟，业界普遍采用更低介电常数(k)介质代替传统的SiO2(k≈4.2)介质。在90nm至65nm技术代，业界一般使用介电常数在2.6～3.0的SiOCH介质；进入45nm技术代，业界一般采用多孔型SiOCH进一步降低k值，介电常数可达2.0～2.5；也有采用含C、H的有机介质，介电常数在2.2～2.6。尽管现有技术的超低介电常数介质已经将k值降至2.0附近，仍无法满足金属线宽进一步缩小的要求，
另一方面，业界普遍采用更薄的阻挡层和籽晶层，来增加双大马士革结构内金属铜的体积，进而降低互连电阻，控制RC延迟。传统阻挡层和籽晶层沉积方法磁控溅射PVD存在台阶覆盖能力的局限性，现有研究在保证铜填充能力的前提下，采用极薄的磁控溅射钽氮复合层、磁控溅射铜锰合金籽晶层和化学气相沉积钴覆盖层来进一步减薄阻挡层和籽晶层厚度，并得到不错的结果。也有研究原子层沉积技术ALD的钌(Ru)及其合金作为阻挡层和籽晶层的实例，并得到较好的铜填充性能及电学性能。
现用的铜互连集成方案一般采用双大马士革技术。在完成前道器件工艺的集成电路芯片上，先沉积以多孔型SiOCH介质和SiCN介质为主的金属间介质，通过两步光刻工艺先后定义出通孔和沟道位置，并采用刻蚀工艺对通孔和沟道区域进行图形化，紧接着采用湿法清洗工艺将金属间介质的刻蚀残留物清除掉，然后采用物理气相沉积技术先后沉积阻挡层和籽晶层，采用电化学镀技术填充金属铜并完成金属铜退火处理，最后采用化学机械抛光技术对集成电路芯片表面进行平坦化并最终实现金属布线。
阻挡层和籽晶层的减薄是大势所趋，新材料和新沉积技术的应用也是势在必行。尽管如此，通孔电阻仍然是控制铜互连RC延迟的关键之一。铜互连技术中通孔的刻蚀工艺、清洗工艺都会对通孔下层金属铜表面造成损伤，清洗工艺后暴露在空气中会引起通孔下层铜表面氧化，阻挡层沉积工艺会在通孔下层铜表面沉积一层阻挡层，由于超低k介质的引入使电镀铜的退火温度进一步降低，这些都会导致通孔内铜与下层铜之间的接触电阻增加，进而影响通孔RC延迟。目前，已通过优化刻蚀工艺和清洗工艺、控制清洗工艺到沉积工艺之间的等候时间、在阻挡层沉积前氢气表面处理、在阻挡层沉积工艺时反刻蚀底部阻挡层、延长电镀铜膜的退火处理时间等方法，来尽可能降低接触电阻。
其中，在上述影响接触电阻的众多因素中，由于多孔型的低k介质材料的引入，使电镀铜膜的退火温度逐渐降低至180℃及以下。经此温度处理的通孔内的铜膜很难充分释放杂质，获得大的晶粒结构，即使延长退火处理时间，通孔内的铜的晶粒生长仍然受限，因而具有相对较高的电阻率。因此，现有的电镀铜膜退火工艺制约了通孔接触电阻的下降空间。为了进一步降低铜互连通孔的接触电阻，有必要提出一种新的电镀铜膜处理方法。
发明内容
本发明的目的在于克服现有技术存在的上述缺陷，提供一种可改善通孔与下层金属的接触电阻、进一步降低RC延迟的用于半导体铜互连工艺的电镀铜膜新的处理方法，通过先采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，再针对电镀铜膜增加一次较高温度的整体退火工艺，使铜晶粒迅速长大且铜电阻率降低，同时，在通孔底部界面，铜的再结晶现象将使铜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟。
为实现上述目的，本发明的技术方案如下：
一种用于半导体铜互连工艺的电镀铜膜的处理方法，包括以下步骤：
步骤一：在完成了前道器件工艺的集成电路芯片上，采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，包括先沉积以多孔型SiOCH介质和SiCN介质为主的金属间介质，通过两步光刻工艺先后定义出通孔和沟道位置，并采用刻蚀工艺对通孔和沟道区域进行图形化，接着采用湿法清洗工艺将金属间介质的刻蚀残留物清除掉，然后采用物理气相沉积技术先后沉积阻挡层和籽晶层，采用电化学镀技术填充金属铜并对得到的金属铜膜进行≤180℃的第一次退火处理，最后采用化学机械抛光技术对集成电路芯片表面进行平坦化并最终实现金属布线；
步骤二：对步骤一中得到的芯片进行针对金属铜膜的高于第一次退火温度的整体第二次退火，使铜发生再结晶现象，晶粒得以迅速长大并达到稳定的结晶状态，从而得到较低电阻率的电镀铜膜；同时利用通孔内铜和下层互连线铜的再结晶共同作用，使铜膜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟；
步骤三：最后，完成铜后道互连工艺的最终介质保护层沉积。
铜晶粒的结晶程度一般采用X射线衍射能谱XRD来表征，但随着铜晶粒长大，铜电阻率会显著下降。因此，铜的方块电阻可以间接反映铜的结晶状态是否达到稳定。本发明的电镀铜膜在180℃及以下退火温度处理下，铜膜的方块电阻基本不变，铜晶粒生长受到限制，铜膜呈现高阻态。随着退火温度升高，铜膜的方块电阻略微减小，铜膜开始缓慢结晶化。当退火温度达到特定阈值及以上时，铜膜的方块电阻迅速下降，铜晶粒快速长大并达到稳定状态，此时的铜膜呈现低阻态。这个特定阈值约在240℃。
进一步地，步骤二中，所述第二次退火在氢气与氮气的混合气体气氛中进行，以氢气与氮气的混合气体作为退火处理时的保护气氛，防止铜膜在处理过程中发生氧化。
进一步地，所述第二次退火在氢气与氮气的混合气体气氛中进行，其中，氢气的体积百分比在3.6％-4.0％。
进一步地，步骤二中，所述第二次退火的温度范围是240-300℃。当退火温度达到240℃及以上时，铜膜的方块电阻迅速下降，铜晶粒快速长大并达到稳定状态。
进一步地，步骤二中，所述第二次退火的温度范围是250-275℃。在250℃时，铜膜的方块电阻的下降趋于平缓，在此温度区间对电镀铜膜进行退火处理，可获得较好的处理效果。
进一步地，步骤二中，针对金属铜膜进行温度为250℃的整体第二次退火。由于在250℃时，铜膜的方块电阻的下降趋于平缓，所以，此温度成为最佳的退火处理温度，可同时减小退火温度的升高对芯片可能造成的不良影响。
进一步地，步骤二中，所述第二次退火的时间为5-15分钟。
从上述技术方案可以看出，本发明通过先采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，再针对电镀铜膜增加一次在特定阈值之上较高温度的整体退火工艺，使铜晶粒迅速长大且铜电阻率降低，在通孔底部界面，铜的再结晶现象将使铜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟。本发明可应用于Cu/Low-k后道互连技术，且可与标准Cu/Low-k后道工艺集成兼容。
附图说明
图1是本发明一种用于半导体铜互连工艺的电镀铜膜的处理方法的工艺流程图。
具体实施方式
下面结合附图，对本发明的具体实施方式作进一步的详细说明。
在本实施例中，请参阅图1，图1是本发明一种用于半导体铜互连工艺的电镀铜膜的处理方法的工艺流程图。如图所示，本发明电镀铜膜的处理方法，包括以下步骤：
步骤一：在完成了前道器件工艺的集成电路芯片上，采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，包括先沉积以多孔型SiOCH介质和SiCN介质为主的金属间介质，通过两步光刻工艺先后定义出通孔和沟道位置，并采用刻蚀工艺对通孔和沟道区域进行图形化，接着采用湿法清洗工艺将金属间介质的刻蚀残留物清除掉，然后采用物理气相沉积技术先后沉积阻挡层和籽晶层，采用电化学镀技术填充金属铜并对得到的金属铜膜进行≤180℃的第一次退火处理，最后采用化学机械抛光技术对集成电路芯片表面进行平坦化并最终实现金属布线；
步骤二：对步骤一中得到的芯片进行针对金属铜膜的高于第一次退火温度的整体第二次退火，在氢气体积百分比为3.6％-4.0％的氢气与氮气的混合气体保护气氛下，进行240-300℃、优选250-275℃退火处理5-15分钟，使铜发生再结晶现象，晶粒得以迅速长大并达到稳定的结晶状态，从而得到较低电阻率的电镀铜膜；同时利用通孔内铜和下层互连线铜的再结晶共同作用，使铜膜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟；
步骤三：最后，完成铜后道互连工艺的最终介质保护层沉积。
铜晶粒的结晶程度一般采用X射线衍射能谱XRD来表征，但随着铜晶粒长大，铜电阻率会显著下降。因此，铜的方块电阻可以间接反映铜的结晶状态是否达到稳定。本发明的电镀铜膜在180℃及以下退火温度处理下，铜膜的方块电阻基本不变，铜晶粒生长受到限制。随着退火温度升高，铜膜的方块电阻略微减小，铜膜开始缓慢结晶化。当退火温度达到特定阈值及以上时，铜膜的方块电阻迅速下降，铜晶粒快速长大并达到稳定状态。这个特定阈值约在240℃。
因此，在本实施例中，采用上述的工艺步骤及以下具体工艺参数，针对电镀铜膜进行处理：
在步骤一中，对得到的金属铜膜进行≤180℃的第一次退火处理；
在步骤二中，针对金属铜膜进行高于第一次退火温度的整体第二次退火，在氢气体积百分比为3.8％的氢气与氮气的混合气体保护气氛下，进行250℃退火处理10分钟，使铜晶粒迅速长大且铜电阻率降低，在通孔底部界面，铜的再结晶现象将使铜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟。最后，对芯片完成铜后道互连工艺的最终介质保护层沉积。
需要说明的是，根据本发明人的研究结果，当铜膜的退火温度达到250℃以上时，铜膜方块电阻的下降开始趋于平缓，铜晶粒的长大已达到稳定状态。因此，在退火温度达到250℃以上后，继续选用更高的退火温度工艺，例如以超过300℃以上的温度，对电镀铜膜进行退火处理，已显得不再具有实际意义。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。
Claims (7)
1.一种用于半导体铜互连工艺的电镀铜膜的处理方法，其特征在于，包括以下步骤：
步骤一：在完成了前道器件工艺的集成电路芯片上，采用标准的铜后道互连工艺集成方案，完成所有层次的铜后道互连工艺，包括先沉积以多孔型SiOCH介质和SiCN介质为主的金属间介质，通过两步光刻工艺先后定义出通孔和沟道位置，并采用刻蚀工艺对通孔和沟道区域进行图形化，接着采用湿法清洗工艺将金属间介质的刻蚀残留物清除掉，然后采用物理气相沉积技术先后沉积阻挡层和籽晶层，采用电化学镀技术填充金属铜并对得到的金属铜膜进行≤180℃的第一次退火处理，最后采用化学机械抛光技术对集成电路芯片表面进行平坦化并最终实现金属布线；
步骤二：对步骤一中得到的芯片进行针对金属铜膜的高于第一次退火温度的整体第二次退火，使铜发生再结晶现象，晶粒得以迅速长大并达到稳定的结晶状态，从而得到较低电阻率的电镀铜膜；同时利用通孔内铜和下层互连线铜的再结晶共同作用，使铜膜与通孔底部极薄的阻挡层有效扩散，形成电阻率更低的界面态，以改善通孔与下层金属的接触电阻，进一步降低通孔的RC延迟；
步骤三：最后，完成铜后道互连工艺的最终介质保护层沉积。
2.如权利要求1所述的电镀铜膜的处理方法，其特征在于，步骤二中，所述第二次退火在氢气与氮气的混合气体气氛中进行。
3.如权利要求2所述的电镀铜膜的处理方法，其特征在于，所述第二次退火在氢气与氮气的混合气体气氛中进行，其中，氢气的体积百分比在3.6％-4.0％。
4.如权利要求1所述的电镀铜膜的处理方法，其特征在于，步骤二中，所述第二次退火的温度范围是240-300℃。
5.如权利要求4所述的电镀铜膜的处理方法，其特征在于，步骤二中，所述第二次退火的温度范围是250-275℃。
6.如权利要求5所述的电镀铜膜的处理方法，其特征在于，步骤二中，所述第二次退火的温度是250℃。
7.如权利要求1所述的电镀铜膜的处理方法，其特征在于，步骤二中，所述第二次退火的时间为5-15分钟。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174828.9A CN103943556A (zh) | 2014-04-28 | 2014-04-28 | 一种用于半导体铜互连工艺的电镀铜膜的处理方法 |
| US14/759,227 US9640434B2 (en) | 2014-04-28 | 2014-08-25 | Method for processing an electroplated copper film in copper interconnect process |
| PCT/CN2014/085102 WO2015165179A1 (zh) | 2014-04-28 | 2014-08-25 | 一种用于半导体铜互连工艺的电镀铜膜的处理方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174828.9A CN103943556A (zh) | 2014-04-28 | 2014-04-28 | 一种用于半导体铜互连工艺的电镀铜膜的处理方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103943556A true CN103943556A (zh) | 2014-07-23 |
Family
ID=51191160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410174828.9A Pending CN103943556A (zh) | 2014-04-28 | 2014-04-28 | 一种用于半导体铜互连工艺的电镀铜膜的处理方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9640434B2 (zh) |
| CN (1) | CN103943556A (zh) |
| WO (1) | WO2015165179A1 (zh) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158581A (zh) * | 2015-03-26 | 2016-11-23 | 北大方正集团有限公司 | 一种对布线后晶圆进行合金化处理的方法 |
| CN106293230A (zh) * | 2016-08-10 | 2017-01-04 | 意力(广州)电子科技有限公司 | 一种触摸屏铜制程方法及触摸屏 |
| CN106558530A (zh) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制作方法 |
| CN110265406A (zh) * | 2019-06-06 | 2019-09-20 | 深圳市华星光电技术有限公司 | 阵列基板及制作方法 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102312827B1 (ko) | 2017-08-08 | 2021-10-13 | 어플라이드 머티어리얼스, 인코포레이티드 | 저-k 막들의 증착을 위한 방법들 및 장치 |
| US10361119B1 (en) | 2018-04-30 | 2019-07-23 | International Business Machines Corporation | Enlarged contact area structure using noble metal cap and noble metal liner |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030224592A1 (en) * | 2002-05-31 | 2003-12-04 | Matsushita Electric Industrial Co., Ltd. | Method for forming wiring structure |
| US20060105565A1 (en) * | 2004-11-12 | 2006-05-18 | Chi-Wen Liu | Method and apparatus for copper film quality enhancement with two-step deposition |
| CN101645412A (zh) * | 2008-08-04 | 2010-02-10 | 中芯国际集成电路制造(上海)有限公司 | 集成电路中互连结构的制作方法 |
| CN102044477A (zh) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | 金属插塞的制作方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025638A (en) * | 1998-06-01 | 2000-02-15 | International Business Machines Corporation | Structure for precision multichip assembly |
| TWI238459B (en) * | 2000-11-15 | 2005-08-21 | Intel Corp | Copper alloy interconnections for integrated circuits and methods of making same |
-
2014
- 2014-04-28 CN CN201410174828.9A patent/CN103943556A/zh active Pending
- 2014-08-25 US US14/759,227 patent/US9640434B2/en active Active
- 2014-08-25 WO PCT/CN2014/085102 patent/WO2015165179A1/zh active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030224592A1 (en) * | 2002-05-31 | 2003-12-04 | Matsushita Electric Industrial Co., Ltd. | Method for forming wiring structure |
| US20060105565A1 (en) * | 2004-11-12 | 2006-05-18 | Chi-Wen Liu | Method and apparatus for copper film quality enhancement with two-step deposition |
| CN101645412A (zh) * | 2008-08-04 | 2010-02-10 | 中芯国际集成电路制造(上海)有限公司 | 集成电路中互连结构的制作方法 |
| CN102044477A (zh) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | 金属插塞的制作方法 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158581A (zh) * | 2015-03-26 | 2016-11-23 | 北大方正集团有限公司 | 一种对布线后晶圆进行合金化处理的方法 |
| CN106558530A (zh) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制作方法 |
| CN106293230A (zh) * | 2016-08-10 | 2017-01-04 | 意力(广州)电子科技有限公司 | 一种触摸屏铜制程方法及触摸屏 |
| CN110265406A (zh) * | 2019-06-06 | 2019-09-20 | 深圳市华星光电技术有限公司 | 阵列基板及制作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160247717A1 (en) | 2016-08-25 |
| US9640434B2 (en) | 2017-05-02 |
| WO2015165179A1 (zh) | 2015-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10727119B2 (en) | Process integration approach of selective tungsten via fill | |
| CN103943556A (zh) | 一种用于半导体铜互连工艺的电镀铜膜的处理方法 | |
| US10002834B2 (en) | Method and apparatus for protecting metal interconnect from halogen based precursors | |
| CN1808717A (zh) | 具有铁电电容器的半导体器件及其制造方法 | |
| US11164780B2 (en) | Process integration approach for selective metal via fill | |
| WO2011114989A1 (ja) | 薄膜の形成方法 | |
| US11967525B2 (en) | Selective tungsten deposition at low temperatures | |
| KR102383378B1 (ko) | 실리콘 관통 비아 금속화를 위한 접착층 | |
| US20130240484A1 (en) | Electroless copper alloy capping | |
| CN105575888A (zh) | 金属互连结构的形成方法 | |
| CN102881646A (zh) | 铜金属覆盖层的制备方法 | |
| TWI564422B (zh) | 釕薄膜的化學氣相沉積及其應用 | |
| CN102938393B (zh) | 铜金属覆盖层的制备方法 | |
| CN108735797A (zh) | 半导体结构及其形成方法 | |
| CN102915962B (zh) | 铜金属覆盖层的制备方法 | |
| CN102420173A (zh) | 一种提高铜互连可靠性的表面处理方法 | |
| TWI843858B (zh) | 用於選擇性金屬通孔填充的製程整合方法 | |
| WO2022006225A1 (en) | Selective tungsten deposition at low temperatures | |
| CN106356329B (zh) | 铜互连的电介质覆盖层的形成方法 | |
| CN108695237B (zh) | 一种半导体器件及其制作方法 | |
| JP2011249584A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140723 |