TWI238459B - Copper alloy interconnections for integrated circuits and methods of making same - Google Patents

Abstract

Formation of copper alloy interconnected lines on integrated circuits includes electroplating copper onto a seed layer wherein the concentration of the doping element or elements in the copper is controlled such that the core portion of the copper interconnect line has a low concentration of the doping element or elements, while surface portions of the copper interconnect line have higher concentrations of the doping element or elements. Copper alloys are plated at different current densities to provide doping element rich interfaces. In this way, electromigration resistance can be improved by having relatively higher doping concentrations at surface portions of an interconnect line while the desired low electrical resistivity of the interconnect is maintained by keeping the interior portions of the interconnect with a substantially lower doping concentration.

Description

1238459 A7

V. Description of the invention (1 B7 The present invention generally relates to the field of integrated circuit manufacturing, and more particularly, refers to steel alloy interconnects and their formation. Advances in JLi semiconductor manufacturing technology have led to the development of integrated circuits with multiple layers Interconnection. In this integrated circuit, a patterned conductive material is made from a thin film of material such as silicon dioxide and another patterned conductive material. It is electrically insulated. These conductive materials are generally a metal or a metal alloy. The connection between conductive materials between different interconnect layers is made by forming openings in these insulating layers and providing a conductive framework to make them different. Conductive materials patterned in layers are in electrical contact with each other. These conductive structures are often referred to as contact windows or vias. Other advances in semiconductor manufacturing technology have integrated millions of transistors, each of which is capable of high speeds Switching. The consequence of merging so many fast-switching transistors into an integrated circuit is to provide power consumption during operation. It can increase speed and reduce power consumption. This technology replaces traditional aluminum or aluminum alloy interconnects on integrated circuits with metals that provide lower resistance, such as copper. People in the bank will know that electrical signals can be reduced by reducing the resistance through an integrated circuit. The interconnect path propagates faster. Furthermore, because the resistance of copper is much smaller than that of aluminum, the cross-sectional area of copper interconnects can be made smaller than aluminum interconnects without causing interconnect-based interconnections. Increased signal propagation delay due to resistance. In addition, because the capacitance between two electrical nodes is a function of the overlapping area between these nodes, the use of a smaller copper interconnect can reduce 1238459

------- V. Description of the invention (2 Parasitic capacitance. A this side ", replacing copper-based interconnects with Ming-based interconnects Depending on the size selected, resistance, capacitance, or both can be reduced. 〇As mentioned above, copper has electrical advantages, such as lower resistance in each cross-cut area, which can reduce parasitic capacitance and improve the immunity of electron migration. For these reasons, integrated circuit manufacturers expect copper to be included in their products. Although copper has better electrical advantages than aluminum in integrated circuit interconnections, pure copper interconnections still suffer from defects related to electron migration. Therefore, it is necessary to provide copper-based interconnections on integrated circuits ^ Copper-based interconnects have improved levels of electron migration resistance. The figure does not briefly describe FIG. 1 is a schematic cross-sectional view of an electroplated etched structure, which depicts a non-direct cladding structure according to the present invention, in which dopants It is concentrated on the upper surface of the metal thin film. Figure 2 is a schematic cross-sectional view of an electro-mineralized engraving structure, which depicts a non-direct coating structure according to the present invention, in which the dopants have sufficiently diffused and exist. Remaining on the upper surface of the metal thin film. R — FIG. 3 is a schematic cross-sectional view of an electroplated etched structure, which depicts a non-direct cladding structure according to the present invention, which represents the dopant concentration at the copper interface. FIG. 4 is a schematic, cross-sectional view of an electroplated engraved structure, which depicts a non-direct coating structure according to the present invention, in which the dopant system is concentrated on the lower surface, the side surface, and the upper surface of the metal thin film. Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 1238459

These proper nouns are all related to metal wiring, routing, wires, conductors, signal paths, and signal media. The related proper nouns listed above are generally interchangeable and are arranged in order from specificity to generality. In this area, metal wiring is sometimes viewed as a route, wire, wiring, interconnect, or simple metal. These proper nouns, both contact windows and vias, refer to structures that electrically connect conductors from different interaction layers. These proper terms are sometimes used in the art to describe both the openings in an insulator to which a structure is to be completed and the structure itself to be completed. For the purposes of this disclosure, contact windows and interlayer windows mean completed structures. NHE means a normalized hydrogen electrode. The abbreviation ppm stands for several parts per million. The substrate can also be considered a wafer. Wafers can be made from semiconductor, non-semiconductor, or semiconductor and non-semiconductor materials. Thin films of various materials are formed on silicon wafers. Other materials such as gallium arsenide, silicon on sapphire, or silicon on insulator (SOI) can be used to form the wafer. As used herein, the proper term means perpendicular to the surface of a substrate. In a specific embodiment of the present invention, a bath is provided for depositing a copper alloy on copper or a copper alloy seed layer. Electroplated copper alloys include, but are not limited to, copper tin, copper carbide, copper sulfide, copper indium, copper cadmium, copper chrome, zinc zinc, copper, copper, copper, zinc Copper, annealed copper, copper, copper, copper, ruthenium, copper, tungsten, platinum, palladium, copper, rhodium, and hafnium. The copper alloy seed layer includes, but is not limited to, copper tin, copper magnesium, copper aluminide, copper titanium, copper tantalum, copper tungsten, copper indium, and antimony. 8- This paper is applicable to China Standard (CNS) A4 (210 X 297 mm)

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The electrical μ is used to control the concentration of doping elements deposited with copper. In this way, a copper alloy containing many one or more doping elements can be made in a special region within the interconnect structure. In particular, copper-based interconnects with alloys on the outside or interface of the interconnect are formed. Regarding the above, it is possible to have a high current density (for example, in the range of 30 to 100 mA / cm2) in the initial deposition stage and the thermal deposition stage so that the copper deposition has a similar doping element concentration (for example, greater than 0.5 wt. %) '. Conversely, a low current density (for example, in the range from 0.5 to 30 mA / cifl2) so that the copper / child product has a lower doping element concentration (for example, less than 0.5 wt%). After deposition in the same plating tool, an annealing operation can be performed briefly, even if not immediately, to form and stabilize the copper alloy microstructure. This annealing operation also drives the dopant elements into the grain boundaries and interfaces. The annealing temperature can be changed from a low annealing temperature to a high annealing temperature, wherein a low annealing temperature lower than C is performed during the first operation period to increase the size of the copper grains and drive impurities to the interface, and during the second operation period A copper alloy is preferentially formed on the interface at a high annealing temperature greater than 25 ° C. In another specific embodiment of the present invention, the annealing is performed after the chemical mechanical polishing method (CMP) so that the doping element can diffuse to these interfaces. The cladding structure can be formed. Thereafter, the CMP annealing operation can be completed at a different temperature (low temperature and high temperature) in an integrated annealing box in a mineral bath, a separate furnace or a rapid thermal processing (RTP) device. Thereafter, the CMP annealing operation can also be performed. It is implemented during the termination of the last name / ILD deposition. The copper interface on the upper interface has the copper association. The interconnection structure according to the specific embodiment of the present invention is based on the use of high current density. National Standard (CNS) A4 specification (210X297 public director) 1238459 A7 B7 V. Description of the invention (9) During the end phase of the deposition operation, one or more tools are preferentially co-deposited. Doping elements of copper are formed, and the main system of deposition is completed at a relatively low current density so that the copper deposition has a low concentration of _ or more doping elements (&lt; 0.5%). After the deposition is completed, an annealing operation is performed to diffuse one or more doping elements toward the upper portion of the copper-filled trench while maintaining a low concentration of tin (ie, <100 ppm) inside the bulk copper located at the grain boundary. Figures 1 to 3 describe this structure and process in more detail. Figure 1 shows a section β of a partially processed wafer, and even more particularly, Figure 1 shows an interlayer dielectric (ILD) 102, which has been placed between the layers. Patterns are made in the dielectric to form trenches 101 and vias 103. Part of the processed wafer is placed in a plating bath containing copper ions and one or more doping element ions. A layer of copper 104 is then plated on the ILD The trench 102 and the interlayer window 103 are filled on 102, and the upper surface of ILD 102 is also covered with copper 104. When it is still in the electroplating bath for electric copper 104, the current density increases. Make one or more doping elements in the electroplating bath co-deposit with copper to shape Copper alloy layer 106. The current density is selected so that the number of doped atoms in the copper layer 104 is less than 0.5 wt.% And the number of doped atoms in the copper alloy layer 106 is greater than 0.5 wt.%. Figure 2 Shows the structure of Figure 1 after an annealing operation is performed. In this specific embodiment, an annealing operation is performed in an environment of nitrogen, argon, or nitrogen plus hydrogen (ie, forming a gas) at a temperature of less than 450 ° C. It is performed for 0.5 to 180 minutes. In another specific embodiment, an annealing operation is performed in two steps .... Firstly, in an environment of nitrogen, argon-gas, and atmosphere plus hydrogen (that is, forming a gas) Anneal at a temperature between 100 ° C and 250 ° C for 0.5 to 180 minutes; and nitrogen, argon, or nitrogen plus hydrogen-12-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) Staple

Line 1238459 V. Description of the invention (10) The environment of the gas (that is, the gas is formed) is between 25 cc and 45. [The degree of brewing is between 0.5 and 180 minutes for the second annealing. The annealing operation drives (these) doping elements from the copper alloy layer 106 through the upper part of the copper layer 104. Some of these two doping atoms are also driven to the interface surface of the copper layer 104 to form a copper alloy layer 108, such as Shown in Figure 2. Fig. 3 shows the structure of Fig. 2 after a chemical mechanical polishing (CMp) operation is performed. This CMP operation removes the metal covering the upper and upper surfaces of the ILD 102, thereby generating an interconnection line having a copper portion 104 and a copper alloy portion 108, as shown in FIG. The copper alloy portion present on the upper surface of the interconnect structure is generally thinner and thicker toward the middle of the interconnect structure near the vertical sidewalls of the trench. ^ ― 4 Soil-Free Coated Copper Mutual Cobalt 4 In a specific embodiment of the present invention, a copper-based interconnect structure is formed by co-depositing copper to drive one or more low-solubility doping elements. To the interface portion of the interconnect structure, wherein the co-deposited copper has one or more elements after in-situ annealing of the electroplated copper doped material. This interconnect structure can also be formed in the initial deposition step by using a higher current density (&gt; 30 mA / cm2) by a common electric tool ... with a higher concentration of doping elements, and then at a lower current density (< (30mA / cm2) copper electroplating to get a lower concentration of impurity elements in the internal part of the main body of the interconnect structure. That is, the later deposited part of the interconnected structure gets relatively complex elements. — After the plating operation is completed, an annealing operation is performed to diffuse the doping elements to the upper part of the trench that fills the copper. -13- 1238459 A7 B7 V. Description of the invention (11) Figures 4 to 6 describe this structure and process in more detail. Figure 4 shows a cross section of a partially processed wafer. More particularly, FIG. 4 shows an interlayer dielectric (ILD) 402 that has been patterned to generate trenches 401 and interlayer windows 403 inside. Part of the processed wafer is placed in a plating bath containing one or more doping element ions and copper ions. A layer of copper alloy 404 is then plated on ILD 402 so that the surface of trench 401 and interlayer 403 and the upper surface of ILD 402 are coated with copper alloy 404. In the specific embodiment described, tin is co-deposited with copper to form a copper alloy 40, and the thickness of this layer is deposited to about 100 to 500 Angstroms. Copper alloy 400 is formed by co-depositing copper from a plating bath with one or more doping elements. While still in the electroplating bath used to deposit the copper alloy 404, the current density is reduced so that the doping elements in the electroplating bath are not co-deposited with copper to form the copper layer 406. As shown in FIG. 4, the copper layer 406 fills the trenches 401 and the vias 403 which do not occupy the portion of the copper alloy layer 404. These current densities are selected such that the number of doped atoms in the copper alloy layer 404 is greater than 0.5 wt.% And the number of earning heteroatoms in the layer copper layer 406 is less than 0.5 wt.%. After the layer 406 is formed, the current density is increased to co-deposit copper from the electroplating bath and one or more atoms doped with 70 element to form a copper alloy layer 408. FIG. 5 shows the structure of FIG. 4 after the annealing operation is performed. In this embodiment, an annealing operation is performed in a nitrogen, argon, or nitrogen plus hydrogen (i.e., forming gas) environment at a temperature below 450 ° C for 0.5 to 180 minutes. In another specific embodiment, an annealing operation is performed in two steps: first in a nitrogen, argon, or nitrogen plus hydrogen (ie, forming gas) environment at a temperature of 10 (TC to 250 ° C) Implementation of 0.5 to 14

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Line 1238459 A7 ____ B7 V. Description of the invention (12) 180-minute annealing; and implemented in the environment of nitrogen, argon or nitrogen plus hydrogen (ie forming gas) at a temperature between 250 ° C and 450 ° C 0.5 to 180 minutes of second annealing. The annealing operation drives (these) doping elements from the copper alloy layers 404, 408 through a portion of the copper layer 406, as shown in FIG. 4. By driving these doped atoms toward the interface surface of the copper layer 406, an auto-coated copper region is formed. That is, the copper 406 is surrounded by the post-annealed copper alloy 41. FIG. 6 shows the structure of FIG. 5 after a chemical mechanical polishing operation is performed. This CMP operation removes the metal covering the upper surface of IL1) 402 to produce individual interconnections having a copper portion 406 and a copper alloy portion 410, as shown in FIG. The copper alloy portion present on the upper surface of the interconnect structure is generally thinner and thicker toward the middle of the interconnect structure near the vertical sidewalls of the trench. In another embodiment of the present invention, the annealing operation is performed after the excess metal is removed by CMP. The subsequent CMP annealing operation can be completed at different temperatures (low and high) in an integrated annealing box in a plating tool, a stand-alone furnace or a rapid thermal processing (RTP) equipment. In addition, according to the present invention, the annealing operation may be performed during or before the termination of an etch or the deposition of an ILD layer. Fig. 7 shows a cross-sectional view of a portion of a crystal circle surrounded by an interconnect layer and a copper window. More specifically, the core area of the copper interconnect wiring and vias surrounds an autoclave I. 2. These automatic cladding layers are formed of copper alloy. Copper alloys can be used to not only improve the electromigration characteristics as described above, but also to eliminate the copper diffusion barriers individually formed in traditional copper interconnects. -15- This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 1238459

The adhesion of the thread is improved. An advantage of certain embodiments of the present invention is that a silicon nitride etch stop layer is not required. An advantage of certain embodiments of the present invention is that the wear resistance of copper-based interconnects is improved. An advantage of certain embodiments of the present invention is that the raised structure is reduced during an annealing operation. An advantage of certain embodiments of the present invention is that compared to pure copper, the adhesion between the copper alloy and the barrier layer is improved, because the doping composition of the copper alloy can be compared with that of the barrier layer (such as those based on tantalum and copper-tin alloys). Barrier layer) to form a staggered metal compound. An advantage of certain embodiments of the present invention is that the copper interconnect wiring with a copper alloy coating provides a mechanical construction to support these copper wiring. This is particularly useful when silicon dioxide based interlayer dielectric materials are replaced with less stringent low-k and ultra-low-k dielectric materials. Other variations from the specially described devices, cleaning fluids, and processes will be apparent to the Bank and have the advantages of this disclosure. Therefore, it is intended that all such variations and modifications, as defined by the scope of the attached application patent, are deemed to be within the spirit and scope of the present invention. -18- This paper size is in accordance with Chinese National Standard (CNS) A4 (21〇 &gt; &lt; 297mm)

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Claims (1)

Wang / Correction / Supplement No. A8 B8 Patent Application No. 126739⑺ Chinese patent application scope replaces too (September 1993) Bleach application patent scope. A plating bath containing a mixture of sulfuric acid and a benzene sulfonate Acid sulfonic acid, a copper-containing compound, a chlorine-containing compound, and tin. 2. The bond bath according to item 1 of Shen Qing's patent scope, further comprising at least one organic additive. 3. The electroplating bath according to item 2 of the patent application scope, wherein the at least one organic additive is selected from the group consisting of sodium thiol alkyl sulfonate, polyethers, polyimines, and polyamidoamines. . 4. The electroplating bath according to item 3 of the patent application scope, further comprising at least one complexing agent. 5. For the electroplating bath according to item 4 of the patent application scope, at least one compound is selected from the group consisting of acetate, citrate, tartrate, and EDTA. 6. For example, the electroplating bath of the scope of patent application, wherein the concentration range of the benzenesulfonic acid is between 0.005 m0iesniter and 2.5 moles / liter. Electroplating bath, wherein the concentration range of benzenesulfonic acid is between 1 and 50 g / l; and the concentration range of chloride ions from chlorine-containing compounds is between 10 and 100nig / 1. 8. The electric mineral bath as described in item 2 of the patent, in which the benzoic acid is less than 10% by weight of the plating bath. 9. The electroplating bath according to item 5 of the patent application scope, wherein the source material of tin in the electroplating bath is selected from the group consisting of tin sulfate (H), acid donating tin (I), tin bromide (II), and vaporized tin. (II), tin fluoride (Π), tin iodide (11), and oxide 74320-930929.doc This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) 1238459 A8 B8 C8 D8 VI. Application The group of patent scope tin (II). 10. For the electroplating bath of item 5 of the patent application scope, the gas-containing compound is hydrogen chloride. 11. A method of forming a copper-based interconnect on a integrated circuit 'comprising: Length: for a substrate with a dielectric layer above, the dielectric layer having a trench' and a delta-hide trench with a crystal built in Seed layer; the substrate is placed in a plating bath mixture, the electro-mineral bath mixture is composed of sulfuric acid, a benzoic acid, a carboxylic acid, a copper-containing compound, a gas-containing compound, and tin; a self-plating bath Forming a copper layer by electrolysis to fill the trenches above the seed layer 'the copper layer has a distribution of tin, wherein forming a copper layer by electrolysis to fill the trenches comprises: applying a first voltage to a substrate to generate A first positive current density; after applying a first voltage to the substrate, applying a second voltage to the substrate to generate a second positive current density, the second positive current density being less than the first positive current density; and applying a second After the voltage is applied to the substrate, a third voltage is applied to the substrate to generate a third positive current density, and the third positive current density is greater than the second positive current density. 12. The method according to item 11 of the application, wherein the first current density and the third current density are 30 mA / cm2 to 100 mA / cm2. 13. The method according to item 11 of the application, wherein the third current density is 5 mA / cm2 to 30 mA / cm2. 74320-930929.doc _ 〇 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 public director) 1238459 The method of applying for patent scope H == scope item 11 'Procedure-further includes annealing the copper uniformly distributed to the desert The method of the boundary of the trench so as to form the non-limiting range of the tin, item 11, further includes removing the upper part of the copper layer above the trench by chemically 16-J:. An interconnect structure in a -integrated circuit, comprising: an interlayer dielectric layer having at least-a trench in the ps p wide ", the trench having a vertical side wall that is open from the grid; and one disposed in the at least one trench 5 :::: Metal conductor contains an internal part, the internal part contains copper of small elements, the metal conductor has -contains-the upper two heterogeneous male ", the upper part contains 0.5 wt% 4% copper, and the upper portion has a change in distance from the vertical sidewalls of the trenches. The thickness is according to 17. If the interconnect structure of the patent application No. 16 is used, the central part is a copper tin alloy 'and the upper part is in these at least one groove: the middle of the side wall is the thickest. / 木 之 学 于 部 Data Vertical 74320-930929.doc This paper size applies to China National Standard (CNS) A4 (210X297 mm) View;. Zheng / Correction / Supplement No. 126739 Patent Application Chinese Schematic Replacement Page (Sept. 1993) _902 From a plating bath containing sulfuric acid, sulfonic acid, copper ions and doped ions at a first current density Copper is electroplated on a substrate_904 A copper alloy is electroplated on copper at a second current density from an electroplating bath containing sulfuric acid, a sulfonic acid, copper ions and doped ions "U 虿 Caΰΐ Patent No. 26739 Chinese Schematic Replacement Page (Sept. 1993) _1002 Copper alloy is electroplated at a first current density from an electro-mineral bath containing sulfuric acid, sulfonic acid, copper ions and doped ions On a substrate_1004 Copper is electroplated on a copper alloy at a second current density from a plating bath containing sulfuric acid, a sulfonic acid, copper ions and doped ions_1006 at a third current density from a sulfuric acid, a sulfonic acid, copper Ion and ion-doped electroplating bath plating copper alloy on copper_1008 annealing substrate Figure 10