WO2002045142A3 - Copper alloy interconnections for integrated circuits and methods of making same - Google Patents

Copper alloy interconnections for integrated circuits and methods of making same Download PDF

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Publication number
WO2002045142A3
WO2002045142A3 PCT/US2001/051183 US0151183W WO0245142A3 WO 2002045142 A3 WO2002045142 A3 WO 2002045142A3 US 0151183 W US0151183 W US 0151183W WO 0245142 A3 WO0245142 A3 WO 0245142A3
Authority
WO
WIPO (PCT)
Prior art keywords
copper
doping
doping element
interconnect
elements
Prior art date
Application number
PCT/US2001/051183
Other languages
French (fr)
Other versions
WO2002045142A9 (en
WO2002045142A2 (en
Inventor
Christopher D Thomas
Valery M Dubin
Original Assignee
Intel Corp
Christopher D Thomas
Valery M Dubin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Christopher D Thomas, Valery M Dubin filed Critical Intel Corp
Priority to AU2002239767A priority Critical patent/AU2002239767A1/en
Priority to EP01987565A priority patent/EP1338031A2/en
Publication of WO2002045142A2 publication Critical patent/WO2002045142A2/en
Publication of WO2002045142A9 publication Critical patent/WO2002045142A9/en
Publication of WO2002045142A3 publication Critical patent/WO2002045142A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/58—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrochemistry (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Formation of copper alloy interconnected lines on integrated circuits includes electroplating copper onto a seed layer wherein the concentration of the doping element or elements in the copper is controlled such that the core portion (104) of the copper interconnect line has a low concentration of the doping element or elements, while surface portions (106) of the copper interconnect line have higher concentrations of the doping element or elements. Copper alloys are plated at different current densities to provide doping element rich interfaces. In this way, electromigration resistance can be improved by having relatively higher doping concentrations at surface portions of an interconnect line while the desired low electrical resistivity of the interconnect is maintained by keeping the interior portions of the interconnect with a substantially lower doping concentration.
PCT/US2001/051183 2000-11-15 2001-10-29 Copper alloy interconnections for integrated circuits and methods of making same WO2002045142A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002239767A AU2002239767A1 (en) 2000-11-15 2001-10-29 Copper alloy interconnections for integrated circuits and methods of making same
EP01987565A EP1338031A2 (en) 2000-11-15 2001-10-29 Copper alloy interconnections for integrated circuits and methods of making same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71400300A 2000-11-15 2000-11-15
US09/714,003 2000-11-15

Publications (3)

Publication Number Publication Date
WO2002045142A2 WO2002045142A2 (en) 2002-06-06
WO2002045142A9 WO2002045142A9 (en) 2003-02-06
WO2002045142A3 true WO2002045142A3 (en) 2003-06-05

Family

ID=24868422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/051183 WO2002045142A2 (en) 2000-11-15 2001-10-29 Copper alloy interconnections for integrated circuits and methods of making same

Country Status (5)

Country Link
EP (1) EP1338031A2 (en)
CN (1) CN1575508A (en)
AU (1) AU2002239767A1 (en)
TW (1) TWI238459B (en)
WO (1) WO2002045142A2 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074709B2 (en) * 2002-06-28 2006-07-11 Texas Instruments Incorporated Localized doping and/or alloying of metallization for increased interconnect performance
US6841458B2 (en) 2002-09-12 2005-01-11 Intel Corporation Dopant interface formation
AU2003272573A1 (en) * 2002-09-26 2004-04-19 Advanced Micro Devices, Inc. Method of forming a copper interconnect with concentrated alloy atoms at copper-passivation interface
US6858124B2 (en) 2002-12-16 2005-02-22 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
US7147767B2 (en) 2002-12-16 2006-12-12 3M Innovative Properties Company Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor
US6884338B2 (en) 2002-12-16 2005-04-26 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
JP4178295B2 (en) * 2004-07-14 2008-11-12 富士通マイクロエレクトロニクス株式会社 Semiconductor device having wiring made of copper and method of manufacturing the same
US7169700B2 (en) * 2004-08-06 2007-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Metal interconnect features with a doping gradient
DE102005014748B4 (en) * 2005-03-31 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Technique for electrochemical deposition of a chemical order alloy
JP4589835B2 (en) 2005-07-13 2010-12-01 富士通セミコンダクター株式会社 Semiconductor device manufacturing method and semiconductor device
CN100431106C (en) * 2005-09-26 2008-11-05 财团法人工业技术研究院 Method for forming interconnected electroplating lead wire of nano-carbon tube and metal composite material
EP1845554A3 (en) * 2006-04-10 2011-07-13 Imec A method to create super secondary grain growth in narrow trenches
US7843063B2 (en) 2008-02-14 2010-11-30 International Business Machines Corporation Microstructure modification in copper interconnect structure
DE102008033174B3 (en) * 2008-07-15 2009-09-17 Enthone Inc., West Haven Cyanide-free electrolyte composition for the electrodeposition of a copper layer and method for the deposition of a copper-containing layer
CN102116828B (en) * 2010-12-24 2015-10-28 上海集成电路研发中心有限公司 The defining method of electro-migration lifetime of interconnected lines
JP5667485B2 (en) * 2011-03-17 2015-02-12 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
CN102956541B (en) * 2011-08-19 2015-11-25 中芯国际集成电路制造(上海)有限公司 A kind of method forming copper-connection
KR20180015767A (en) * 2011-11-04 2018-02-13 인텔 코포레이션 Methods and apparatuses to form self-aligned caps
CN104934368B (en) * 2011-11-04 2019-12-17 英特尔公司 Method and apparatus for forming self-aligned caps
US8729702B1 (en) * 2012-11-20 2014-05-20 Stmicroelectronics, Inc. Copper seed layer for an interconnect structure having a doping concentration level gradient
CN103943556A (en) * 2014-04-28 2014-07-23 上海集成电路研发中心有限公司 Method for processing electrocoppering film used for semiconductor copper connection process
CN105845620A (en) * 2015-01-16 2016-08-10 中芯国际集成电路制造(上海)有限公司 Method of making copper interconnection structure, semiconductor device and electronic apparatus
CN111900175A (en) * 2020-07-29 2020-11-06 北海惠科光电技术有限公司 Display panel and manufacturing method thereof
CN118186248A (en) * 2022-12-12 2024-06-14 华为技术有限公司 Copper-based composite material, preparation method thereof, PCB, integrated circuit and electronic equipment

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US6110817A (en) * 1999-08-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improvement of electromigration of copper by carbon doping
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US6387806B1 (en) * 2000-09-06 2002-05-14 Advanced Micro Devices, Inc. Filling an interconnect opening with different types of alloys to enhance interconnect reliability

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US5385661A (en) * 1993-09-17 1995-01-31 International Business Machines Corporation Acid electrolyte solution and process for the electrodeposition of copper-rich alloys exploiting the phenomenon of underpotential deposition
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US6022808A (en) * 1998-03-16 2000-02-08 Advanced Micro Devices, Inc. Copper interconnect methodology for enhanced electromigration resistance
WO2000005747A2 (en) * 1998-06-30 2000-02-03 Semitool, Inc. Metallization structures for microelectronic applications and process for forming the structures
WO2000014306A1 (en) * 1998-09-03 2000-03-16 Ebara Corporation Method for plating substrate and apparatus
EP1118696A1 (en) * 1998-09-03 2001-07-25 Ebara Corporation Method for plating substrate and apparatus
US6123825A (en) * 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
JP2000174027A (en) * 1998-12-03 2000-06-23 Internatl Business Mach Corp <Ibm> Method of forming copper conductive body in electronic structure
US6110817A (en) * 1999-08-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improvement of electromigration of copper by carbon doping
US6387806B1 (en) * 2000-09-06 2002-05-14 Advanced Micro Devices, Inc. Filling an interconnect opening with different types of alloys to enhance interconnect reliability

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Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 09 13 October 2000 (2000-10-13) *

Also Published As

Publication number Publication date
WO2002045142A9 (en) 2003-02-06
CN1575508A (en) 2005-02-02
AU2002239767A1 (en) 2002-06-11
TWI238459B (en) 2005-08-21
WO2002045142A2 (en) 2002-06-06
EP1338031A2 (en) 2003-08-27

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