JPWO2021099885A1 - - Google Patents

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Publication number
JPWO2021099885A1
JPWO2021099885A1 JP2021558030A JP2021558030A JPWO2021099885A1 JP WO2021099885 A1 JPWO2021099885 A1 JP WO2021099885A1 JP 2021558030 A JP2021558030 A JP 2021558030A JP 2021558030 A JP2021558030 A JP 2021558030A JP WO2021099885 A1 JPWO2021099885 A1 JP WO2021099885A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2021558030A
Other languages
Japanese (ja)
Other versions
JPWO2021099885A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021099885A1 publication Critical patent/JPWO2021099885A1/ja
Publication of JPWO2021099885A5 publication Critical patent/JPWO2021099885A5/ja
Priority to JP2025166553A priority Critical patent/JP2025185071A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/037Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6728Vertical TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
JP2021558030A 2019-11-21 2020-11-10 Withdrawn JPWO2021099885A1 (https=)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025166553A JP2025185071A (ja) 2019-11-21 2025-10-02 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019210330 2019-11-21
JP2019237925 2019-12-27
PCT/IB2020/060547 WO2021099885A1 (ja) 2019-11-21 2020-11-10 半導体装置および電子機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025166553A Division JP2025185071A (ja) 2019-11-21 2025-10-02 半導体装置

Publications (2)

Publication Number Publication Date
JPWO2021099885A1 true JPWO2021099885A1 (https=) 2021-05-27
JPWO2021099885A5 JPWO2021099885A5 (https=) 2023-11-14

Family

ID=75980563

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021558030A Withdrawn JPWO2021099885A1 (https=) 2019-11-21 2020-11-10
JP2025166553A Pending JP2025185071A (ja) 2019-11-21 2025-10-02 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025166553A Pending JP2025185071A (ja) 2019-11-21 2025-10-02 半導体装置

Country Status (5)

Country Link
US (1) US12550325B2 (https=)
JP (2) JPWO2021099885A1 (https=)
KR (1) KR20220103108A (https=)
CN (1) CN114787986A (https=)
WO (1) WO2021099885A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116368602A (zh) 2020-10-02 2023-06-30 株式会社半导体能源研究所 半导体装置
WO2025219846A1 (ja) * 2024-04-19 2025-10-23 株式会社半導体エネルギー研究所 半導体装置
WO2025233772A1 (ja) * 2024-05-10 2025-11-13 株式会社半導体エネルギー研究所 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010106922A1 (ja) * 2009-03-19 2010-09-23 株式会社 東芝 半導体装置及びその製造方法
JP2011023688A (ja) * 2009-07-21 2011-02-03 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US20140264525A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Vertical nand and method of making thereof using sequential stack etching and landing pad
JP2016225614A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP2018157205A (ja) * 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体メモリ
JP2019012822A (ja) * 2017-06-16 2019-01-24 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (25)

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Publication number Priority date Publication date Assignee Title
JP5016832B2 (ja) 2006-03-27 2012-09-05 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2011023687A (ja) * 2009-07-21 2011-02-03 Toshiba Corp 不揮発性半導体記憶装置
US9166055B2 (en) 2011-06-17 2015-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8952377B2 (en) 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR20140009023A (ko) 2012-07-13 2014-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US20140027762A1 (en) 2012-07-27 2014-01-30 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device
US9698153B2 (en) * 2013-03-12 2017-07-04 Sandisk Technologies Llc Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad
JP2015056443A (ja) 2013-09-10 2015-03-23 株式会社東芝 不揮発性記憶装置の製造方法
TWI666770B (zh) 2013-12-19 2019-07-21 日商半導體能源研究所股份有限公司 半導體裝置
JP6607681B2 (ja) 2014-03-07 2019-11-20 株式会社半導体エネルギー研究所 半導体装置
US9634097B2 (en) * 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel
US9761732B2 (en) 2015-02-25 2017-09-12 Snaptrack Inc. Tunnel thin film transistor with hetero-junction structure
KR102788207B1 (ko) 2015-04-13 2025-03-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6400536B2 (ja) 2015-08-04 2018-10-03 東芝メモリ株式会社 半導体記憶装置
US20180033794A1 (en) 2016-07-27 2018-02-01 Sandisk Technologies Llc Non-Volatile Memory With Reduced Program Speed Variation
US9972641B1 (en) * 2016-11-17 2018-05-15 Sandisk Technologies Llc Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof
US10553601B2 (en) 2017-03-16 2020-02-04 Toshiba Memory Corporation Semiconductor memory including semiconductor oxide
JPWO2018224904A1 (ja) 2017-06-05 2020-05-21 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP7195068B2 (ja) 2017-06-26 2022-12-23 株式会社半導体エネルギー研究所 半導体装置、電子機器
JP7234110B2 (ja) 2017-07-06 2023-03-07 株式会社半導体エネルギー研究所 メモリセル及び半導体装置
US10665604B2 (en) 2017-07-21 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor wafer, memory device, and electronic device
US10355014B1 (en) * 2017-12-22 2019-07-16 Micron Technology, Inc. Assemblies having vertically-extending structures
JP7194813B2 (ja) * 2018-09-13 2022-12-22 長江存儲科技有限責任公司 三次元メモリデバイス、三次元メモリデバイスを作製するための方法及びメモリセルストリング
WO2020095148A1 (ja) 2018-11-08 2020-05-14 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
US11985827B2 (en) 2020-01-17 2024-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, driving method of semiconductor device, and electronic device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010106922A1 (ja) * 2009-03-19 2010-09-23 株式会社 東芝 半導体装置及びその製造方法
JP2011023688A (ja) * 2009-07-21 2011-02-03 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US20140264525A1 (en) * 2013-03-12 2014-09-18 SanDisk Technologies, Inc. Vertical nand and method of making thereof using sequential stack etching and landing pad
JP2016225614A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP2018157205A (ja) * 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体メモリ
JP2019012822A (ja) * 2017-06-16 2019-01-24 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Also Published As

Publication number Publication date
US20230065351A1 (en) 2023-03-02
KR20220103108A (ko) 2022-07-21
CN114787986A (zh) 2022-07-22
US12550325B2 (en) 2026-02-10
WO2021099885A1 (ja) 2021-05-27
JP2025185071A (ja) 2025-12-18

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