JPWO2017073350A1 - 薄膜素子およびその製造方法 - Google Patents

薄膜素子およびその製造方法 Download PDF

Info

Publication number
JPWO2017073350A1
JPWO2017073350A1 JP2017547728A JP2017547728A JPWO2017073350A1 JP WO2017073350 A1 JPWO2017073350 A1 JP WO2017073350A1 JP 2017547728 A JP2017547728 A JP 2017547728A JP 2017547728 A JP2017547728 A JP 2017547728A JP WO2017073350 A1 JPWO2017073350 A1 JP WO2017073350A1
Authority
JP
Japan
Prior art keywords
film
external electrode
resist film
wiring conductor
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017547728A
Other languages
English (en)
Other versions
JP6341336B2 (ja
Inventor
俊幸 中磯
俊幸 中磯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of JPWO2017073350A1 publication Critical patent/JPWO2017073350A1/ja
Application granted granted Critical
Publication of JP6341336B2 publication Critical patent/JP6341336B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/03849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565—Only outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/1369—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

薄膜素子（１０１）は、基材（１）、基材（１）の表面に形成される配線導体膜（２）、少なくとも配線導体膜（２）の表面に被覆される保護膜（３）、外部電極（４）、保護膜（３）の表面に被覆される第１レジスト膜（１１）および第２レジスト膜（１２）を備える。保護膜（３）は（Ｚ）方向から視て配線導体膜（２）と重なる位置にコンタクトホール（ＣＨ１）を有し、外部電極（４）はコンタクトホール（ＣＨ１）内、且つ、配線導体膜（２）の表面に形成される。外部電極（４）は保護膜（３）より厚く、側面（Ｓ１）を有する。第１レジスト膜（１１）は、外部電極（４）の側面（Ｓ１）の全周に沿って接し、第２レジスト膜（１２）は、外部電極（４）の側面（Ｓ１）および第１レジスト膜（１１）から離間して配置される。

Description

本発明は、薄膜素子に関し、特に例えば、基材と基材上に形成される配線導体膜と、配線導体膜上に形成される外部電極とを有する薄膜素子に関する。また、その薄膜素子の製造方法に関する。
従来、基材と、基材上に形成される配線導体膜と、配線導体膜の表面に形成される外部電極と、基材の表面および配線導体膜の表面に被覆されるレジスト膜と、外部電極の表面に形成されるはんだバンプと、を備える端子構造が知られている（特許文献１）。
また、特許文献１に開示されているように、はんだ等の導電性接合材を外部電極に接合する際に、基材上に形成された配線導体膜や外部電極が、基材から剥離することを防止するため、配線導体膜や外部電極の外縁にレジスト膜を被せる方法（オーバーレジスト処理）が一般的である。
しかし、外部電極を構成するＡｕははんだに濡れやすく、はんだを外部電極に接合する際に、外部電極の表面とレジスト層との界面にはんだが浸入し、外部電極の表面がオーバーレジスト処理したレジスト層の剥離の起点となる虞がある。
一方、このようなレジスト層の剥離を抑制するため、レジスト層と外部電極との間に所定間隔（クリアランス）が設けられたクリアランスレジスト型の端子構造もある（特許文献２）。
特開２０１２−７４４８７号公報 特開２０１３−９８５０７号公報
しかし、レジスト層と外部電極との間に所定クリアランスを設けた場合、上記クリアランスからはんだが浸入し、上記クリアランス内で露出する配線導体膜とはんだとが反応すること（はんだ食われ等）によって、抵抗値の増大や、配線導体膜が断線する虞がある。また、上記クリアランスから水分やフラックス等が浸入し、上記クリアランス内に露出する配線導体膜が腐食する虞もある。
本発明の目的は、レジスト層を外部電極から離間して配置する構造において、配線導体膜のはんだ食われや腐食等を抑制した、信頼性の高い外部電極を有する薄膜素子を提供することにある。また、その薄膜素子の製造方法を提供することにある。
（１）本発明の薄膜素子は、
基材と、
前記基材の表面に形成される配線導体膜と、
少なくとも前記配線導体膜の表面に被覆され、平面視で前記配線導体膜と重なる位置にコンタクトホールを有する保護膜と、
前記コンタクトホール内、且つ、前記配線導体膜の表面に形成され、前記保護膜より厚く、側面を有する外部電極と、
前記保護膜の表面に被覆される第１レジスト膜および第２レジスト膜と、
を備え、
前記第１レジスト膜は、前記外部電極の前記側面の全周に沿って接し、
前記第２レジスト膜は、前記外部電極の前記側面および前記第１レジスト膜から離間して配置されることを特徴とする。
この構成では、外部電極の側面および第１レジスト膜と第２レジスト膜との間に形成された離間部内に配線導体膜が露出しないため、この離間部から導電性接合材や水分、フラックス等が浸入したとしても、配線導体膜と導電性接合材５の反応等は抑制される。
また、この構成では、外部電極の側面の全周に沿って接する第１レジスト膜を備えるため、外部電極の側面と保護膜との界面からの導電性接合材や水分、フラックス等の浸入が抑制される。
（２）上記（１）において、前記第１レジスト膜は熱硬化性樹脂であることが好ましい。この構成により、第１レジスト膜はキュアした際に収縮するため、硬化したループ状の第１レジスト膜には内側に向かって締まるような応力が発生する。したがって、保護膜の表面に被覆される第１レジスト膜が、外部電極の側面を締め付けるため、外部電極の側面と保護膜との界面からの導電性接合材や水分、フラックス等の浸入が抑制される。
また、この構成により、硬化した第２レジスト膜には外部電極から外側に向かう応力が発生するが、第２レジスト膜は第１レジスト膜と離間して配置されているため、外部電極と第１レジスト膜との間の隙間の発生がさらに抑制される。
（３）上記（１）または（２）において、前記外部電極は、前記側面の全周に沿って形成される庇部を有し、前記第１レジスト膜は、平面視で前記庇部に重なることが好ましい。この構成により、硬化したループ状の第１レジスト膜が、外部電極の底面から表面に向かって脱落することを抑制できる。
（４）上記（３）において、前記外部電極は、底面から表面に向かって前記側面が逆テーパー状に形成されていてもよい。
（５）上記（１）から（４）のいずれかにおいて、前記配線導体膜は銅を主成分とする金属膜であり、前記保護膜はチタンを主成分とする金属膜であり、前記外部電極はニッケルを主成分とする金属であってもよい。
（６）本発明の薄膜素子の製造方法は、
基材の表面に配線導体膜を形成する第１工程と、
少なくとも前記配線導体膜の表面に、前記配線導体膜と重なる位置にコンタクトホールを有する保護膜を被覆する第２工程と、
前記コンタクトホール内、且つ、前記配線導体膜の表面に、側面の全周に沿って庇部を有する外部電極を形成する第３工程と、
前記保護膜の表面にレジスト膜を被覆する第４工程と、
前記レジスト膜のうち、平面視で前記庇部に重なる第１レジスト膜と、前記第１レジスト膜以外である第２レジスト膜とを離間する離間部を除去する第５工程と、
を備えることを特徴とする。
この製造方法により、配線導体膜のはんだ食われや腐食等を抑制した、信頼性の高い外部電極を有する薄膜素子を容易に製造できる。
（７）上記（６）において、前記第５工程は、前記レジスト膜はポジ型感光性レジスト膜であり、前記離間部をフォトリソグラフィにより除去し、前記外部電極の前記庇部をフォトマスクにして露光する工程を含むことが好ましい。この製造方法により、外部電極の側面の全周に沿って接する第１レジスト膜を容易に形成できる。
（８）上記（６）または（７）において、前記第５工程の後に、前記外部電極の表面にはんだをプリコートする工程をさらに有していてもよい。
本発明によれば、レジスト層と外部電極との間に所定のクリアランスを設ける構造において、配線導体膜のはんだ食われや腐食等を抑制した、信頼性の高い外部電極を有する薄膜素子を実現できる。
図１は第１の実施形態に係る薄膜素子１０１の外部電極４の構成を示す平面詳細図である。 図２は、図１におけるＡ−Ａ断面図である。 図３は薄膜素子１０１の外部電極４の実際の様子を示す断面図である。 図４（Ａ）は、比較例として、保護膜および第１レジスト膜を備えていない薄膜素子１００Ａの外部電極４の構成を示す断面詳細図であり、図４（Ｂ）は、第１レジスト膜を備えていない薄膜素子１００Ｂの外部電極４の構成を示す断面詳細図である。 図５は、薄膜素子１０１の製造工程を順に示す断面図である。 図６は、第２の実施形態に係る薄膜素子１０２の外部電極４の構成を示す断面詳細図である。
以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明または理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換または組み合わせが可能である。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。
《第１の実施形態》
図１は第１の実施形態に係る薄膜素子１０１の外部電極４の構成を示す平面詳細図である。図２は、図１におけるＡ−Ａ断面図である。図３は薄膜素子１０１の外部電極４の実際の様子を示す断面図である。図２において、各部の厚みは誇張して図示している。以降の各実施形態における断面図についても同様である。薄膜素子１０１は、例えばキャパシタ等の受動素子やＬＣ複合電子部品、半導体集積回路素子、ＥＳＤ保護素子等の薄膜デバイス（Ｔｈｉｎ−Ｆｉｌｍ Ｄｅｖｉｃｅ）である。
薄膜素子１０１は、基材１、配線導体膜２、保護膜３、外部電極４、導電性接合材５、第１レジスト膜１１、第２レジスト膜１２を備える。
基材１は表面が平面状の絶縁性平板である。基材１の表面には配線導体膜２が形成されている。基材１は例えば受動素子やＬＣ複合電子部品、集積回路素子、ＥＳＤ保護素子等を構成するためのベース材であり、例えばＳｉ基板やガラス基板である。なお、基材１と配線導体膜２との間には、他の絶縁層や配線導体層が設けられていてもよい。
配線導体膜２の表面には保護膜３が被覆されている。保護膜３は、図２に示すように、Ｚ方向から視て（平面視で）配線導体膜２と重なる位置にコンタクトホールＣＨ１を有する。すなわち、保護膜３には、Ｚ方向から視て、配線導体膜２が形成されている位置にコンタクトホールＣＨ１が形成されている。コンタクトホールＣＨ１は保護膜３に形成される開口であり、配線導体膜２の表面に保護膜３が被覆されることにより、コンタクトホールＣＨ１から配線導体膜２が露出する。配線導体膜２は例えばＣｕ膜である。保護膜３は例えばＴｉを主成分とする金属膜である。
外部電極４は平面形状が円形の金属めっき膜であり、第１電極層４１および第２電極層４２を有する。第１電極層４１は配線導体膜２の表面に形成され、第２電極層４２は第１電極層４１の表面に形成されている。外部電極４は例えばＮｉを主成分とする金属めっき膜である。第１電極層４１は例えばＮｉめっき膜であり、第２電極層４２は例えばＡｕめっき膜である。
外部電極４は、コンタクトホールＣＨ１から露出する配線導体膜２の表面に形成される。すなわち、外部電極４はコンタクトホールＣＨ１内、且つ、配線導体膜２の表面に形成される。図１に示すように、外部電極４は保護膜３より厚く、側面Ｓ１を有する。図１に示すように、外部電極４は底面から表面に向かって側面Ｓ１が逆テーパー状に形成される。そのため、外部電極４は側面Ｓ１に庇部６を有する。庇部６は外部電極４の側面Ｓ１の全周に沿って形成される。なお、本発明における「庇部」とは、Ｚ方向から視て（平面視で）、外部電極４の底面（基部）よりもはみ出した部分全体をいう。
外部電極４の表面には導電性接合材５が形成されている。導電性接合材５は、例えば外部電極４の表面にプリコートされたはんだである。なお、導電性接合材５は、フラックス等で外部電極４の表面に仮固定されたはんだボールであってもよい。
第１レジスト膜１１は保護膜３の表面に被覆される熱硬化性樹脂であり、外部電極４の側面Ｓ１の全周に沿って接している。そのため、本実施形態に係る第１レジスト膜１１は、外部電極４と保護膜３との界面を覆うようなループ状（環状、リング状。但し、部分的に切れた形状であってもよい。）である。第１レジスト膜１１は、Ｚ方向から視て、全体が外部電極４の庇部６内に収まる。したがって、第１レジスト膜１１は、Ｚ方向から視て、外部電極４で覆われている（外部電極４に重なっている）。第１レジスト膜１１は例えばポジ型感光性のソルダーレジスト膜である。
第２レジスト膜１２は保護膜３の表面に被覆される熱硬化性樹脂であり、第１レジスト膜１１と同じ樹脂で構成され、外部電極４の側面Ｓ１および第１レジスト膜１１から離間して配置される。したがって、外部電極４の側面Ｓ１および第１レジスト膜１１と第２レジスト膜１２との間には、図２等に示すように、離間部３１（クリアランス）が形成されている。第２レジスト膜１２は例えばポジ型感光性のソルダーレジスト膜である。第１レジスト膜１１および第２レジスト膜は同一のレジスト膜をパターニングしたものであるが、第１レジスト膜１１の高さ寸法は第２レジスト膜の高さ寸法よりも小さい。
次に、保護膜３および第１レジスト膜１１を備えることの利点について、図を参照して説明する。図４（Ａ）は、比較例として、保護膜および第１レジスト膜を備えていない薄膜素子１００Ａの外部電極４の構成を示す断面詳細図であり、図４（Ｂ）は、第１レジスト膜を備えていない薄膜素子１００Ｂの外部電極４の構成を示す断面詳細図である。
図４（Ａ）に示すように、外部電極４と第２レジスト層との間には離間部３１が形成されている。そのため、この離間部３１から外部電極４に沿って導電性接合材５が浸入することがあり、離間部３１内に露出する配線導体膜２と導電性接合材５とが接触して反応（はんだ食われ等）し、抵抗値の増大や、配線導体膜２が断線する虞がある。また、上記離間部３１から水分やフラックス等が浸入し、上記離間部３１内に露出する配線導体膜２が腐食する虞もある。
また、図４（Ｂ）に示すように、配線導体膜２の表面に保護膜３が被覆されている場合には、この離間部３１から導電性接合材５が浸入しても、離間部３１内に配線導体膜２が露出していないため、配線導体膜２と導電性接合材５との反応は抑制される。しかし、外部電極４の側面と保護膜３との界面５０は物理的に隣接・接触しているだけであり、化学的に結合してはいない。そのため、導電性接合材５や水分、フラックス等がこの界面５０から浸入し、配線導体膜２と導電性接合材５とが反応したり、配線導体膜２が腐食する虞がある。
一方、本実施形態では、保護膜３が配線導体膜２の表面に被覆される。また、本実施形態では、第１レジスト膜１１が、保護膜３の表面に被覆されるループ状の熱硬化性樹脂であり、外部電極４の側面Ｓ１の全周に沿って接している。この構成では、離間部３１内で配線導体膜２が露出しないため、この離間部３１から導電性接合材５や水分、フラックス等が浸入したとしても、配線導体膜２と導電性接合材５との反応等は抑制される。また、薄膜素子１０１は、外部電極４の側面Ｓ１の全周に沿って接する第１レジスト膜１１を備えるため、外部電極４の側面と保護膜３との界面５０からの導電性接合材や水分、フラックス等の浸入が抑制される。
さらに、第１レジスト膜１１はキュアした際に収縮するため、硬化したループ状の第１レジスト膜１１には内側に向かって締まるような応力が発生する（図１中の中抜き矢印を参照）。したがって、保護膜３の表面に被覆される第１レジスト膜１１が、外部電極４の側面Ｓ１を締め付けるため、外部電極４の側面と保護膜３との界面５０からの導電性接合材や水分、フラックス等の浸入がさらに抑制される。
また、本実施形態では、第２レジスト膜１２が第１レジスト膜１１と離間して配置され、第１レジスト膜１１と第２レジスト層との間に離間部３１が形成されている。もし離間部３１が設けられていない場合、レジスト膜には外部電極４との界面から外側に向かう応力が発生するため、外部電極４の側面とレジスト膜との間に隙間が生じ、この隙間から導電性接合材や水分、フラックス等が浸入する虞がある。一方、本実施形態では、硬化した第２レジスト膜１２には外部電極４から外側に向かう応力が発生するが（図１中の矢印を参照）、第２レジスト膜１２は第１レジスト膜１１と離間して配置されているため、外部電極４とレジスト膜との間の隙間の発生がさらに抑制される。
また、本実施形態の外部電極４は、側面Ｓ１の全周に沿って形成される庇部６を有し、第１レジスト膜１１が、Ｚ方向から視て庇部６に重なっている。この構成により、硬化したループ状の第１レジスト膜１１が、外部電極４の底面から表面に向かって脱落することを抑制できる。
上記薄膜素子１０１は例えば次の工程で製造される。図５は、薄膜素子１０１の製造工程を順に示す断面図である。
まず、図５中の（１）に示すように、集合基板状態の基材１を用意し、基材１の表面に、イオンスパッタリング等によって約１μｍの配線導体膜２を形成する。基材１は例えば受動素子やＬＣ複合電子部品、集積回路素子、ＥＳＤ保護素子等のＳｉ基板等であり、配線導体膜２は例えばＣｕ等の金属膜である。基材１の表面に配線導体膜２を形成するこの工程が、本発明における「第１工程」に相当する。
次に、配線導体膜２の表面に、イオンスパッタリング等によって約０．１μｍの保護膜３を連続形成する。保護膜３は例えばＴｉ等を主成分とする金属膜である。その後、スピンコートによって保護膜３の全面に約５μｍのポジ型感光性のレジスト膜を形成し、露光してパターニングする。この工程により、底面から表面に向かってテーパー状のレジスト膜５１が形成される。さらに、レジスト膜５１をマスクとしてエッチングを行い、保護膜３の配線導体膜２と重なる位置にコンタクトホールＣＨ１を形成する。この工程により、コンタクトホールＣＨ１から配線導体膜２が露出する。配線導体膜２の表面に保護膜３を形成し、保護膜３の配線導体膜２と重なる位置にコンタクトホールＣＨ１を形成するこの工程が、本発明における「第２工程」に相当する。
次に図５中の（２）に示すように、コンタクトホールＣＨ１に露出する配線導体膜２の表面に、外部電極４を形成する。具体的には、コンタクトホールＣＨ１内、且つ、配線導体膜２の表面に、電解めっき法によって、約３μｍの第１電極層４１および約０．１μｍの第２電極層４２を連続形成する。第１電極層４１は例えばＮｉを主成分とする金属めっき膜であり、第２電極層４２はＡｕを主成分とする金属めっき膜である。
外部電極４の金属めっき膜は、底面から表面に向かってテーパー状のレジスト膜５１に沿って成長する。そのため、外部電極４は、底面から表面に向かって側面が逆テーパー状に形成され、その側面の全周に沿って庇部６が形成される。コンタクトホールＣＨ１内、且つ、配線導体膜２の表面に、側面の全周に沿って庇部６を有する外部電極４を形成するこの工程が、本発明における「第３工程」に相当する。
次に図５中の（４）に示すように、レジスト膜５１をアッシングにより取り除いた後、スピンコートによって保護膜３および外部電極４の表面に約５μｍのレジスト膜１０を形成する。レジスト膜１０は例えばポジ型感光性のソルダーレジスト膜である。なお、レジスト膜５１はウェット処理で剥離装置にかけて取り除いてもよい。保護膜３の表面にレジスト膜１０を形成するこの工程が、本発明における「第４工程」に相当する。
次に図５中の（５）（６）に示すように、レジスト膜１０のうち、平面視で庇部６に重なる部分（第１レジスト膜１１）と、それ以外の部分（第２レジスト膜１２）とを離間する離間部３１をフォトリソグラフィにより除去する。具体的には、レジスト膜１０のうち、除去したくない部分にフォトマスク６１を被せて、光線Ｌ１で露光する。このとき、外部電極４の庇部６がフォトマスクとなり、平面視で庇部６に重なる部分は露光されないため、現像して洗浄（リンス）した後、第１レジスト膜１１と第２レジスト膜１２とを離間する離間部３１が除去される。光線Ｌ１は例えば紫外線（ＵＶ光）である。
レジスト膜１０のうち、平面視で庇部６に重なる第１レジスト膜１１と、第２レジスト膜１２とを離間する離間部３１を除去するこの工程が、本発明における「第５工程」に相当する。そして、この第５工程は外部電極４の庇部６をフォトマスクにして露光する工程を含む。
上記第５工程の後に、外部電極４の表面に導電性接合材５をプリコートする。導電性接合材５は例えばはんだである。なお、導電性接合材５ははんだペーストをスクリーン印刷した後、リフロープロセスによって形成してもよい。また、外部電極４の表面にフラックス等を塗付して、はんだボールをマウントして仮固定した後、リフロープロセスによって形成してもよい。さらに、導電性接合材５は、外部電極４の表面にフラックス等を塗付して、はんだボールを仮固定した状態であってもよい。
上記製造方法により、配線導体膜２のはんだ食われや腐食等を抑制した、信頼性の高い外部電極４を有する薄膜素子１０１を容易に製造できる。
また、上記製造方法では、レジスト膜１０がポジ型感光性レジスト膜であり、外部電極４の庇部６がフォトマスクとなるため、外部電極４の側面の全周に沿って接する第１レジスト膜１１を容易に形成できる。
《第２の実施形態》
第２の実施形態では、外部電極４および第１レジスト膜１１の形状が第１の実施形態とは異なる例を示す。
図６は、第２の実施形態に係る薄膜素子１０２の外部電極４の構成を示す断面詳細図である。
本実施形態に係る外部電極４は、図６に示すように、ネジ頭のように側面上部が突出した形状である。このような構造であっても、外部電極４は側面の全周に沿って形成される庇部６を有する。また、第１レジスト膜１１は外部電極４の側面の全周に沿って接しており、Ｚ方向から視て、全体が外部電極４の庇部６内に収まる。
《その他の実施形態》
なお、上述の実施形態では、外部電極４の平面形状が円形である例を示したが、これ限定されるものではない。外部電極４の平面形状は、正方形、矩形、多角形、楕円形等、適宜変更可能である。
また、庇部６は、外部電極４の側面上部に形成されるものに限定されるものではない。庇部６は、Ｚ方向から視て、外部電極４の底面（基部）からはみ出した部分であればよく、外部電極４の底面以外に形成されていればよい。すなわち、庇部６は、外部電極４の側面中央部等に形成されていてもよい。
また、配線導体膜２は基材１の表面全体に形成されるものに限定されるものではなく、基材１の表面の一部にのみ形成されていてもよい。また、保護膜３は少なくとも配線導体膜２の表面に形成されていればよく、基材１の表面に形成されていてもよい。
なお、上述の実施形態では、基材１の表面が平面状である例を示したが、これに限定されるものではない。基材１の表面は、曲面であってもよく、基材１の表面に段差があってもよい。
ＣＨ１…コンタクトホール
Ｌ１…光線
Ｓ１…外部電極の側面
１…基材
２…配線導体膜
３…保護膜
４…外部電極
５…導電性接合材
６…庇部
１０…レジスト膜
１１…第１レジスト膜
１２…第２レジスト膜
３１…離間部
４１…第１電極層
４２…第２電極層
５０…界面
５１…レジスト膜
６１…フォトマスク
１００Ａ，１００Ｂ，１０１，１０２…薄膜素子

Claims (8)

  1. 基材と、
    前記基材の表面に形成される配線導体膜と、
    少なくとも前記配線導体膜の表面に被覆され、平面視で前記配線導体膜と重なる位置にコンタクトホールを有する保護膜と、
    前記コンタクトホール内、且つ、前記配線導体膜の表面に形成され、前記保護膜より厚く、側面を有する外部電極と、
    前記保護膜の表面に被覆される第１レジスト膜および第２レジスト膜と、
    を備え、
    前記第１レジスト膜は、前記外部電極の前記側面の全周に沿って接し、
    前記第２レジスト膜は、前記外部電極の前記側面および前記第１レジスト膜から離間して配置される、薄膜素子。
  2. 前記第１レジスト膜は熱硬化性樹脂である、請求項１に記載の薄膜素子。
  3. 前記外部電極は、前記側面の全周に沿って形成される庇部を有し、
    前記第１レジスト膜は、平面視で前記庇部に重なる、請求項１または２に記載の薄膜素子。
  4. 前記外部電極は、底面から表面に向かって前記側面が逆テーパー状に形成される、請求項３に記載の薄膜素子。
  5. 前記配線導体膜は銅を主成分とする金属膜であり、
    前記保護膜はチタンを主成分とする金属膜であり、
    前記外部電極はニッケルを主成分とする金属である、請求項１から４のいずれかに記載の薄膜素子。
  6. 基材の表面に配線導体膜を形成する第１工程と、
    少なくとも前記配線導体膜の表面に、前記配線導体膜と重なる位置にコンタクトホールを有する保護膜を被覆する第２工程と、
    前記コンタクトホール内、且つ、前記配線導体膜の表面に、側面の全周に沿って庇部を有する外部電極を形成する第３工程と、
    前記保護膜の表面にレジスト膜を被覆する第４工程と、
    前記レジスト膜のうち、平面視で前記庇部に重なる第１レジスト膜と、前記第１レジスト膜以外である第２レジスト膜とを離間する離間部を除去する第５工程と、
    を備える、薄膜素子の製造方法。
  7. 前記第５工程は、
    前記レジスト膜はポジ型感光性レジスト膜であり、前記離間部をフォトリソグラフィにより除去し、
    前記外部電極の前記庇部をフォトマスクにして露光する工程を含む、請求項６に記載の薄膜素子の製造方法。
  8. 前記第５工程の後に、前記外部電極の表面にはんだをプリコートする工程をさらに有する、請求項６または７に記載の薄膜素子の製造方法。
JP2017547728A 2015-10-30 2016-10-14 薄膜素子およびその製造方法 Active JP6341336B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2015214182 2015-10-30
JP2015214182 2015-10-30
PCT/JP2016/080467 WO2017073350A1 (ja) 2015-10-30 2016-10-14 薄膜素子およびその製造方法

Publications (2)

Publication Number Publication Date
JPWO2017073350A1 true JPWO2017073350A1 (ja) 2018-04-12
JP6341336B2 JP6341336B2 (ja) 2018-06-13

Family

ID=58630067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017547728A Active JP6341336B2 (ja) 2015-10-30 2016-10-14 薄膜素子およびその製造方法

Country Status (4)

Country Link
US (1) US10388603B2 (ja)
JP (1) JP6341336B2 (ja)
CN (1) CN208706584U (ja)
WO (1) WO2017073350A1 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003124389A (ja) * 2001-10-10 2003-04-25 Fujikura Ltd 半導体パッケージ
JP2010267641A (ja) * 2009-05-12 2010-11-25 Panasonic Corp 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
CN100590859C (zh) * 2007-01-16 2010-02-17 百慕达南茂科技股份有限公司 具有环状支撑物的凸块结构及其制造方法
JP2009231682A (ja) 2008-03-25 2009-10-08 Citizen Watch Co Ltd 半導体装置およびその製造方法
JP2009266803A (ja) 2008-04-03 2009-11-12 Fuji Electric Holdings Co Ltd 有機ｅｌディスプレイパネル及びその製造方法
US8598030B2 (en) * 2010-08-12 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
JP2012074487A (ja) 2010-09-28 2012-04-12 Toppan Printing Co Ltd 半導体パッケージの製造方法
JP5862210B2 (ja) 2011-11-07 2016-02-16 株式会社村田製作所 高周波電子部品
JP6238007B2 (ja) 2013-03-02 2017-11-29 荒川化学工業株式会社 クリアランスレジスト用鉛フリーはんだ向けフラックスおよびクリアランスレジスト用鉛フリーはんだペースト
US9779969B2 (en) * 2014-03-13 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003124389A (ja) * 2001-10-10 2003-04-25 Fujikura Ltd 半導体パッケージ
JP2010267641A (ja) * 2009-05-12 2010-11-25 Panasonic Corp 半導体装置

Also Published As

Publication number Publication date
CN208706584U (zh) 2019-04-05
US10388603B2 (en) 2019-08-20
US20180226346A1 (en) 2018-08-09
JP6341336B2 (ja) 2018-06-13
WO2017073350A1 (ja) 2017-05-04

Similar Documents

Publication Publication Date Title
JP4922891B2 (ja) 半導体装置およびその製造方法
TWI473552B (zh) 具有元件設置區之基板結構及其製程
US7781338B2 (en) Semiconductor device manufacturing method and semiconductor device
CN106206505B (zh) 半导体装置以及半导体装置的制造方法
JP2009043857A (ja) 半導体装置およびその製造方法
JP5249080B2 (ja) 半導体装置
TWI413210B (zh) 電子裝置封裝及製造方法
JP7134617B2 (ja) 半導体装置及び半導体装置の製造方法
JP6341336B2 (ja) 薄膜素子およびその製造方法
JP4506767B2 (ja) 半導体装置の製造方法
US9293402B2 (en) Device with pillar-shaped components
JP2006287094A (ja) 半導体装置及びその製造方法
JP6072510B2 (ja) 半導体装置の製造方法及び半導体装置
US9922923B2 (en) Method of manufacturing wiring substrate and wiring substrate
JP3972211B2 (ja) 半導体装置及びその製造方法
JP2010062170A (ja) 半導体装置およびその製造方法
JP5128712B1 (ja) 半導体装置
JP6328741B2 (ja) 半導体装置
JP2008210828A (ja) 半導体装置およびその製造方法
JP4873179B2 (ja) 半導体装置の製造方法
WO2023163223A1 (ja) 半導体装置及び半導体装置の製造方法
JP6021399B2 (ja) 半導体装置の製造方法
US7615474B2 (en) Method for manufacturing semiconductor device with reduced damage to metal wiring layer
JP7335036B2 (ja) 半導体パッケージの製造方法
JP5068830B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180122

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180122

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20180122

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20180406

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180417

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180430

R150 Certificate of patent or registration of utility model

Ref document number: 6341336

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150