JPWO2016084768A1 - 表面実装型パッケージおよびその製造方法 - Google Patents
表面実装型パッケージおよびその製造方法 Download PDFInfo
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- JPWO2016084768A1 JPWO2016084768A1 JP2016561572A JP2016561572A JPWO2016084768A1 JP WO2016084768 A1 JPWO2016084768 A1 JP WO2016084768A1 JP 2016561572 A JP2016561572 A JP 2016561572A JP 2016561572 A JP2016561572 A JP 2016561572A JP WO2016084768 A1 JPWO2016084768 A1 JP WO2016084768A1
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Abstract
Description
円形の支持基板上に半導体チップを接合する第一工程、
半導体チップを樹脂で封止する第二工程、
半導体チップのパッドを覆う樹脂を除去する第三工程、
再配線層を形成する第四工程、
バンプを形成する第五工程。
2.前記第二工程において、支持基板を樹脂で封止しないことを特徴とする1.に記載の表面実装型パッケージの製造方法。
3.前記半導体チップが矩形であることを特徴とする1.または2.に記載の表面実装型パッケージの製造方法。
4.前記半導体チップが円形であることを特徴とする1.または2.に記載の表面実装型パッケージの製造方法。
5.前記半導体チップの直径が0.5インチであることを特徴とする4.に記載の表面実装型パッケージの製造方法。
6.複数個の半導体チップを1つの表面実装型パッケージに封止することを特徴とする1.〜5.のいずれかに記載の表面実装型パッケージの製造方法。
7.CSP(チップ・サイズ・パッケージ)であることを特徴とする4.〜6.のいずれかに記載の表面実装型パッケージの製造方法。
8.前記バンプが、前記表面実装型パッケージの底面に円形を形成するように等間隔で配置されていることを特徴とする1.〜7.のいずれかに記載の表面実装型パッケージの製造方法。
9.前記パッドが、円形を形成するように等間隔で配置されていることを特徴とする1.〜8.のいずれかに記載の表面実装型パッケージの製造方法。
10.前記再配線層の配線パターンが、曲線、直線のいずれか、または両方から形成されていることを特徴とする1.〜9.のいずれかに記載の表面実装型パッケージの製造方法。
11.バンプ、再配線層、半導体チップ、支持基板がこの順に積層され、
前記半導体チップの少なくとも側面が封止樹脂部で覆われ、
半導体チップ表面に平行な面の断面が円形であることを特徴とする表面実装型パッケージ。
12.前記支持基板が表面に露出していることを特徴とする11.に記載の表面実装型パッケージ。
13.前記半導体チップが矩形であることを特徴とする11.または12.に記載の表面実装型パッケージ。
14.前記半導体チップが円形であることを特徴とする11.または12.に記載の表面実装型パッケージ。
15.前記半導体チップの直径が0.5インチであることを特徴とする14.に記載の表面実装型パッケージ。
16.複数個の半導体チップが封止されていることを特徴とする11.〜15.のいずれかに記載の表面実装型パッケージ。
17.CSP(チップ・サイズ・パッケージ)であることを特徴とする14.〜16.のいずれかに記載の表面実装型パッケージ。
18.前記バンプが、前記表面実装型パッケージの底面に円形を形成するように等間隔で配置されていることを特徴とする11.〜17.のいずれかに記載の表面実装型パッケージ。
19.前記半導体チップのパッドが、円形を形成するように等間隔で配置されていることを特徴とする11.〜18.のいずれかに記載の表面実装型パッケージ。
20.前記再配線層の配線パターンが、曲線、直線のいずれか、または両方から形成されていることを特徴とする11.〜19.のいずれかに記載の表面実装型パッケージ。
2 バンプ
3 再配線層
4 半導体チップ
5 接着剤
6 支持基板
7 封止樹脂部
8 パッド
9 導電部
10 開口部
11 銅層
12 レジスト層
13 ビアホール
14 ソルダーレジスト
15 はんだボール
図1に記載の表面実装型パッケージ1は、バンプ2、再配線層3、半導体チップ4、接着剤5、支持基板6がこの順に積層され、支持基板6は表面実装型パッケージ1の表面に露出している。半導体チップ4の再配線層3側の面および側面は封止樹脂部7で覆われている。半導体チップ4のパッド8は封止樹脂部7で覆われておらず、パッド8は再配線層3の導電部9によりバンプ2と電気的に接続されている。支持基板6と封止樹脂部7とは半導体チップ表面に平行な面の断面が円形であり、表面実装型パッケージ断面と同心円になるように配置されている。
なお、図1に記載の表面実装型パッケージは、本発明の製造方法により得られる表面実装型パッケージの一例であり、本発明の製造方法により得られる表面実装型パッケージの構成はこれに限定されない。例えば、半導体チップ4と支持基板6とは共晶接合してもよく、支持基板6は全体が封止樹脂部7で封止されてもよく、複数個の半導体チップ4を並列または積層して封止してもよい。
42アロイからなる直径13.5mmの円形の支持基板6上に、シリコンからなる直径0.5インチ(12.5mm)、厚さ0.25mmの円形の半導体チップ4を支持基板6と同心円となるように熱伝導性の接着剤5を用いて接合する(図5)。
直径12.8mm、深さ0.4mmの円柱状の凹部が設けられた金型を、支持基板6上に密着させてキャビティを形成する。熱硬化性樹脂をキャビティ内に注型、硬化させるモールド成形を行い、半導体チップ4の上面と側面とを封止する封止樹脂部7を形成する(図6)。
上記第二工程で、半導体チップ4の上面は封止樹脂部7で覆われているため、半導体チップ4の信号の入出力に用いるパッド8を覆う樹脂をレーザアブレーションにより除去し開口部10を形成する(図7)。
パッド8と外部電極であるバンプ2とを接続するための導電部9を有する再配線層3を形成する。再配線層の形成には、通常使用される公知の工程を利用することができる。一例として、以下の工程を用いることができる。
封止樹脂部7とパッド8上に電解メッキによる銅層11を形成する(図8)。封止樹脂部7は非導電性であるため、電解メッキはCuシード層をスパッタにより薄く形成した後に行う。なお、支持基板は42アロイから形成されているため、そのまま電解メッキを行うと支持基板の裏面にも銅層が形成される。パッケージの最表面となる支持基板の裏面に、錆びると緑青となる銅層が形成されるのは外観上好ましくないため、マスキングテープ等で保護して支持基板の裏面に銅層が形成されないようにすることが好ましい。
ボールマウンターを用いてビアホール13上にはんだボール15を搭載する(図13)。リフロー装置で加熱してはんだボールを熔融させてバンプ2を形成するとともに、バンプ2とパッド8とを導電部9を通じて電気的に接続する(図14)。
Claims (20)
- 少なくとも下記工程をこの順で有することを特徴とする、半導体チップ表面に平行な面の断面が円形である表面実装型パッケージの製造方法:
円形の支持基板上に半導体チップを接合する第一工程、
半導体チップを樹脂で封止する第二工程、
半導体チップのパッドを覆う樹脂を除去する第三工程、
再配線層を形成する第四工程、
バンプを形成する第五工程。 - 前記第二工程において、支持基板を樹脂で封止しないことを特徴とする請求項1に記載の表面実装型パッケージの製造方法。
- 前記半導体チップが矩形であることを特徴とする請求項1または2に記載の表面実装型パッケージの製造方法。
- 前記半導体チップが円形であることを特徴とする請求項1または2に記載の表面実装型パッケージの製造方法。
- 前記半導体チップの直径が0.5インチであることを特徴とする請求項4に記載の表面実装型パッケージの製造方法。
- 複数個の半導体チップを1つの表面実装型パッケージに封止することを特徴とする請求項1〜5のいずれかに記載の表面実装型パッケージの製造方法。
- CSP(チップ・サイズ・パッケージ)であることを特徴とする請求項4〜6のいずれかに記載の表面実装型パッケージの製造方法。
- 前記バンプが、前記表面実装型パッケージの底面に円形を形成するように等間隔で配置されていることを特徴とする請求項1〜7のいずれかに記載の表面実装型パッケージの製造方法。
- 前記パッドが、円形を形成するように等間隔で配置されていることを特徴とする請求項1〜8のいずれかに記載の表面実装型パッケージの製造方法。
- 前記再配線層の配線パターンが、曲線、直線のいずれか、または両方から形成されていることを特徴とする請求項1〜9のいずれかに記載の表面実装型パッケージの製造方法。
- バンプ、再配線層、半導体チップ、支持基板がこの順に積層され、
前記半導体チップの少なくとも側面が封止樹脂部で覆われ、
半導体チップ表面に平行な面の断面が円形であることを特徴とする表面実装型パッケージ。 - 前記支持基板が表面に露出していることを特徴とする請求項11に記載の表面実装型パッケージ。
- 前記半導体チップが矩形であることを特徴とする請求項11または12に記載の表面実装型パッケージ。
- 前記半導体チップが円形であることを特徴とする請求項11または12に記載の表面実装型パッケージ。
- 前記半導体チップの直径が0.5インチであることを特徴とする請求項14に記載の表面実装型パッケージ。
- 複数個の半導体チップが封止されていることを特徴とする請求項11〜15のいずれかに記載の表面実装型パッケージ。
- CSP(チップ・サイズ・パッケージ)であることを特徴とする請求項14〜16のいずれかに記載の表面実装型パッケージ。
- 前記バンプが、前記表面実装型パッケージの底面に円形を形成するように等間隔で配置されていることを特徴とする請求項11〜17のいずれかに記載の表面実装型パッケージ。
- 前記半導体チップのパッドが、円形を形成するように等間隔で配置されていることを特徴とする請求項11〜18のいずれかに記載の表面実装型パッケージ。
- 前記再配線層の配線パターンが、曲線、直線のいずれか、または両方から形成されていることを特徴とする請求項11〜19のいずれかに記載の表面実装型パッケージ。
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JP2012054414A (ja) * | 2010-09-01 | 2012-03-15 | National Institute Of Advanced Industrial & Technology | デバイス製造装置および方法 |
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JP2002050721A (ja) * | 2000-08-03 | 2002-02-15 | Hitachi Cable Ltd | 電子装置及びその製造方法 |
JP2005038944A (ja) * | 2003-07-16 | 2005-02-10 | Hitachi Maxell Ltd | 半導体装置 |
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JP2006196865A (ja) * | 2004-12-15 | 2006-07-27 | Shinko Electric Ind Co Ltd | 電子部品実装構造体及びその製造方法 |
JP2009194322A (ja) * | 2008-02-18 | 2009-08-27 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法、半導体装置及び配線基板 |
JP2012054414A (ja) * | 2010-09-01 | 2012-03-15 | National Institute Of Advanced Industrial & Technology | デバイス製造装置および方法 |
JP2012209317A (ja) * | 2011-03-29 | 2012-10-25 | Dainippon Printing Co Ltd | 半導体装置および半導体装置の製造方法 |
US20130075924A1 (en) * | 2011-09-23 | 2013-03-28 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP |
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