JPWO2014030254A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す回路図である。2つの半導体モジュール1a,1bが直列に接続されている。各半導体モジュール1a,1bは、並列に接続されたIGBT2(Insulated Gate Bipolar Transistor)とFWD3(Free Wheeling Diode)を有する。
図8は、本発明の実施の形態2に係る半導体装置を示す断面図である。接続電極7の両端が下方に曲がって引っ掛け部17になっている。引っ掛け部17が引っ掛かる溝18が半導体モジュール1a,1bのケース4の上面に設けられている。これにより、半導体モジュール1a,1b同士の位置決めが容易になる。
図9は、本発明の実施の形態3に係る半導体装置を示す断面図である。ケース4の上面に凹部19が設けられている。コレクタ主電極5とエミッタ主電極6は凹部19の底面に引き出されている。凹部19内においてコレクタ主電極5やエミッタ主電極6と接続電極7が接続及び固定されている。このようにコレクタ主電極5やエミッタ主電極6へのボルト8の取り付け位置を下げることで、半導体装置に隣接して接続された外部機器との絶縁距離を確保できるため、絶縁性能を向上することができる。
図10は、本発明の実施の形態4に係る半導体装置を示す断面図である。半導体モジュール1bのエミッタ主電極6は半導体モジュール1bのケース4の上面に引き出されている。半導体モジュール1aのコレクタ主電極5は、半導体モジュール1bのケース4の上方まで延びて、半導体モジュール1bのエミッタ主電極6に接続及び固定されている。
図11は、本発明の実施の形態5に係る半導体装置を示す断面図である。半導体モジュール1aのコレクタ主電極5の先端が下方に曲がって引っ掛け部17になっている。引っ掛け部17が引っ掛かる溝18が半導体モジュール1bのケース4の上面に設けられている。これにより、半導体モジュール1a,1b同士の位置決めが容易になる。
図12は、本発明の実施の形態6に係る半導体装置を示す断面図である。半導体モジュール1bのケース4の上面に凹部19が設けられている。半導体モジュール1bのエミッタ主電極6は凹部19の底面に引き出されている。凹部19内において半導体モジュール1aのコレクタ主電極5と半導体モジュール1bのエミッタ主電極6が接続及び固定されている。このようにコレクタ主電極5やエミッタ主電極6へのボルト8の取り付け位置を下げることで、半導体装置に隣接して接続された外部機器との絶縁距離を確保できるため、絶縁性能を向上することができる。
図13は、本発明の実施の形態7に係る半導体装置の主電極を示す上面図である。実施の形態4〜6では半導体モジュール1a,1bのコレクタ主電極5とエミッタ主電極6はボルト8により接続されていたが、本実施の形態では半導体モジュール1a,1bのコレクタ主電極5とエミッタ主電極6は一方が他方に差し込まれる差し込み型になっている。これにより更に接続が容易になり、作業性が向上する。
図14は、本発明の実施の形態8に係る半導体装置を示す断面図である。絶縁部材20が半導体モジュール1a,1bのコレクタ主電極5とエミッタ主電極6にボルト8で固定される。半導体モジュール1a,1bのコレクタ主電極5とエミッタ主電極6の間においてケース4の上面の最外周部に凸部21が設けられている。これにより、電気的な接続を必要としない結線において、主電極間の沿面距離を伸ばすことで主電極間の絶縁性を向上することができる。
1b 半導体モジュール(第2の半導体モジュール)
2 IGBT(半導体チップ)
3 FWD(半導体チップ)
4 ケース
5 コレクタ主電極(主電極)
6 エミッタ主電極(主電極)
7 接続電極
17 引っ掛け部
18 溝
19 凹部
20 絶縁部材
21 凸部
Claims (9)
- 半導体チップと、前記半導体チップを囲むケースと、前記半導体チップに接続され前記ケースの上面に引き出された主電極とを有する第1及び第2の半導体モジュールと、
前記第1及び第2の半導体モジュールの前記主電極に接続及び固定された接続電極とを備え、
前記接続電極は金属板のみからなることを特徴とする半導体装置。 - 前記接続電極の両端が下方に曲がって引っ掛け部になっており、
前記引っ掛け部が引っ掛かる溝が前記第1及び第2の半導体モジュールの前記ケースの前記上面に設けられていることを特徴とする請求項1に記載の半導体装置。 - 前記ケースの前記上面に凹部が設けられ、
前記主電極は前記凹部の底面に引き出され、
前記凹部内において前記主電極と前記接続電極が接続及び固定されていることを特徴とする請求項1又は2に記載の半導体装置。 - 前記主電極の上面は前記ケースの前記上面に対して段差が無いことを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 半導体チップと、前記半導体チップを囲むケースと、前記半導体チップに接続され前記ケースから引き出された主電極とを有する第1及び第2の半導体モジュールを備え、
前記第2の半導体モジュールの前記主電極は、前記第2の半導体モジュールの前記ケースの上面に引き出され、
前記第1の半導体モジュールの前記主電極は、前記第2の半導体モジュールの前記ケースの上方まで延びて、前記第2の半導体モジュールの前記主電極に接続及び固定されていることを特徴とする半導体装置。 - 前記第1の半導体モジュールの前記主電極の先端が下方に曲がって引っ掛け部になっており、
前記引っ掛け部が引っ掛かる溝が前記第2の半導体モジュールの前記ケースの前記上面に設けられていることを特徴とする請求項5に記載の半導体装置。 - 前記第2の半導体モジュールの前記ケースの前記上面に凹部が設けられ、
前記第2の半導体モジュールの前記主電極は前記凹部の底面に引き出され、
前記凹部内において前記第1の半導体モジュールの前記主電極と前記第2の半導体モジュールの前記主電極が接続及び固定されていることを特徴とする請求項5又は6に記載の半導体装置。 - 前記第1及び第2の半導体モジュールの前記主電極は一方が他方に差し込まれる差し込み型になっていることを特徴とする請求項5〜7の何れか1項に記載の半導体装置。
- 半導体チップと、前記半導体チップを囲むケースと、前記半導体チップに接続され前記ケースの上面に引き出された主電極とを有する第1及び第2の半導体モジュールと、
前記第1及び第2の半導体モジュールの前記主電極に固定される絶縁部材とを備え、
前記第1及び第2の半導体モジュールの前記主電極の間において前記ケースの前記上面に凸部が設けられていることを特徴とする半導体装置。
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