CN104584213A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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Abstract
各半导体模块(1a、1b)具有半导体芯片(2、3)、包围半导体芯片(2、3)的壳体(4)、以及与半导体芯片(2、3)连接并被引出至壳体(4)的上表面的主电极(5、6)。连接电极(7)与相邻的半导体模块(1a、1b)的主电极(5、6)连接以及固定。连接电极(7)仅由金属板构成。如果变更由该连接电极(7)实现的接线,则能够容易地变更额定电流·额定电压·电路结构等,因此,能够缩短设计时间,使制造管理变得容易。而且,只要仅替换故障的半导体模块(1a、1b)即可,无需替换装置整体。其结果,能够削减成本。另外,由于连接电极(7)由导电板构成,因此,与现有的配线母线相比能够削减部件个数,能够将装置小型化。
Description
技术领域
本发明涉及一种在电气化铁路用、工业设备、民生设备等的电动机控制中使用的电力用半导体装置。
背景技术
半导体制造商需要根据用途,对半导体装置的额定电流·额定电压·电路结构等进行设计,并与其多种多样的组合对应地进行部件的调度及制造管理。同时,用户也需要针对各设备进行半导体装置的安排和管理。另外,在半导体装置的内部安装有大量的半导体芯片,在即使其中的1个被破坏的情况下,由于难以对内部进行修理,也需要替换装置整体。特别地,使用SiC的半导体芯片与Si芯片相比单价较高,更换装置整体会造成较大的损失。如上所述,存在成本较大的问题。对此,提出了一种利用配线母线连接2个半导体模块而形成的半导体装置(例如,参照专利文献1)
专利文献1:日本特开2000-082772号公报
发明内容
但是,在现有的半导体装置中,存在下述问题,即,由于使用配线母线而使部件个数变多,半导体装置整体变大。
本发明就是为了解决上述课题而提出的,其目的在于得到一种能够削减成本及部件个数,使装置小型化的半导体装置。
本发明所涉及的半导体装置的特征在于,具有:第1及第2半导体模块,其具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并被引出至所述壳体的上表面的主电极;以及连接电极,其与所述第1及第2半导体模块连接以及固定,所述连接电极仅由金属板构成。
发明的效果
根据本发明,能够削减成本及部件个数,将装置小型化。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的电路图。
图2是表示本发明的实施方式1所涉及的半导体装置的斜视图。
图3是表示本发明的实施方式1所涉及的半导体装置的剖面图。
图4是表示本发明的实施方式1所涉及的半导体模块的内部的斜视图。
图5是表示本发明的实施方式1所涉及的半导体装置的变形例1的电路图。
图6是表示本发明的实施方式1所涉及的半导体装置的变形例2的电路图。
图7是表示本发明的实施方式1所涉及的半导体装置的变形例3的电路图。
图8是表示本发明的实施方式2所涉及的半导体装置的剖面图。
图9是表示本发明的实施方式3所涉及的半导体装置的剖面图。
图10是表示本发明的实施方式4所涉及的半导体装置的剖面图。
图11是表示本发明的实施方式5所涉及的半导体装置的剖面图。
图12是表示本发明的实施方式6所涉及的半导体装置的剖面图。
图13是表示本发明的实施方式7所涉及的半导体装置的主电极的俯视图。
图14是表示本发明的实施方式8所涉及的半导体装置的剖面图。
具体实施方式
参照附图,对本发明的实施方式所涉及的半导体装置进行说明。有时对于相同或对应的构成要素,标注相同的标号,省略重复说明。
实施方式1.
图1是表示本发明的实施方式1所涉及的半导体装置的电路图。2个半导体模块1a、1b串联连接。各半导体模块1a、1b具有并联连接的IBGT2(Insulated Gate Bipolar Transistor)和FWD 3(FreeWheeling Diode)。
图2是表示本发明的实施方式1所涉及的半导体装置的斜视图。在各半导体模块1a、1b的壳体4的上表面,引出有集电极主电极5和发射极主电极6。该集电极主电极5、发射极主电极6与外部电路或相邻的半导体模块连接。在此,仅由Al、Cu等的导电板构成的连接电极7,利用螺栓8与半导体模块1a的集电极主电极5和半导体模块1b的发射极主电极6连接以及固定。由此,将两个主电极电连接,半导体模块1a、1b彼此固定。
图3是表示本发明的实施方式1所涉及的半导体装置的剖面图。图4是表示本发明的实施方式1所涉及的半导体模块的内部的斜视图。在基座板9上,经由焊料12安装有绝缘衬底10和驱动衬底11。绝缘衬底10由作为绝缘性以及导热性优异的材料的AlN构成。在绝缘衬底10上,安装有作为半导体芯片的IGBT 2和FWD 3。
在绝缘衬底10上设置有金属镀层13、14。IGBT 2的集电极电极和FWD 3的阴极电极通过焊料12与金属镀层13接合。IGBT 2的发射极电极和FWD 3的阳极电极通过导线15与金属镀层14连接。集电极主电极5和发射极主电极6通过焊料12分别与金属镀层13、14连接。
IGBT 2的栅极电极通过导线15与驱动衬底11连接。驱动衬底11经由金属的电极或专用的衬底被引出至模块外部。驱动衬底11具有连接在IGBT 2的栅极电极和栅极驱动电路之间的电阻。通过该电阻,能够减轻在并联多个IGBT 2时产生的各芯片间的动作波动。
壳体4包围IGBT 2及FWD 3等,树脂等封装材料16对IGBT 2及FWD 3等进行封装。通过将螺栓8插入至壳体4侧的螺母并紧固,从而将连接电极7与半导体模块1a的集电极主电极5和半导体模块1b的发射极主电极6连接以及固定。
以上,如说明所述,在本实施方式中,使用连接电极7对半导体模块1a的集电极主电极5和半导体模块1b的发射极主电极6进行连接。如果变更由该连接电极7实现的接线,则能够容易地变更额定电流、额定电压、电路结构等,因此能够缩短设计时间,使制造管理变得容易。而且,仅替换发生了故障的半导体模块1a、1B即可,无需替换装置整体。其结果,能够削减成本。另外,在本实施方式中,由于连接电极7由导电板构成,因此,与现有的配线母线相比能够削减部件个数,能够使装置小型化。
图5是表示本发明的实施方式1所涉及的半导体装置的变形例1的电路图。半导体模块1a、1b并联连接。图6是表示本发明的实施方式1所涉及的半导体装置的变形例2的电路图。半导体模块1a、1b的集电极主电极5彼此绝缘。图7是表示本发明的实施方式1所涉及的半导体装置的变形例3的电路图。3个半导体模块1a、1b、1c并联连接。如上所述,能够以串联、并联组合大于或等于2个的半导体模块。
另外,优选集电极主电极5和发射极主电极6的上表面相对于第壳体4的上表面没有台阶。由此,电路路径变短,配线电感变小。
实施方式2.
图8是表示本发明的实施方式2所涉及的半导体装置的剖面图。连接电极7的两端向下方弯曲成为卡挂部17。卡挂部17所卡挂的槽18设置在半导体模块1a、1b的壳体4的上表面。由此,使半导体模块1a、1b彼此的定位变得容易。
实施方式3.
图9是表示本发明的实施方式3所涉及的半导体装置的剖面图。在壳体4的上表面设置有凹部19。集电极主电极5和发射极主电极6被引出至凹部19的底面。在凹部19内,将连接电极7和集电极主电极5、发射极主电极6连接以及固定。如上所述,通过降低螺栓8向集电极主电极5、发射极主电极6的安装位置,能够确保与相邻地连接于半导体装置上的外部设备之间的绝缘距离,因此能够提高绝缘性能。
实施方式4.
图10是表示本发明的实施方式4所涉及的半导体装置的剖面图。半导体模块1b的发射极主电极6被引出至半导体模块1b的壳体4的上表面。半导体模块1a的集电极主电极5延伸至半导体模块1b的壳体4的上方,与半导体模块1b的发射极主电极6连接以及固定。
如上所述,一个半导体模块的主电极具有连接电极的功能,从而在半导体模块彼此的连接中不需要另外的连接电极。并且,通过使连接部位仅为1处,从而使操作性提高。
实施方式5.
图11是表示本发明的实施方式5所涉及的半导体装置的剖面图。半导体模块1a的集电极主电极5的前端向下方弯曲成为卡挂部17。卡挂部17所卡挂的槽18设置在半导体模块1b的壳体4的上表面。由此,半导体模块1a、1b彼此的定位变得容易。
实施方式6.
图12是表示本发明的实施方式6所涉及的半导体装置的剖面图。在半导体模块1b的壳体4的上表面设置有凹部19。半导体模块1b的发射极主电极6被引出至凹部19的底面。在凹部19内,半导体模块1a的集电极主电极5与半导体模块1b的发射极主电极6连接以及固定。如上所述,通过降低螺栓8向集电极主电极5、发射极主电极6的安装位置,能够确保与相邻地连接于半导体装置上的外部设备之间的绝缘距离,因此能够提高绝缘性能。
实施方式7.
图13是表示本发明的实施方式7所涉及的半导体装置的主电极的俯视图。在实施方式4~6中,半导体模块1a、1b的集电极主电极5和发射极主电极6通过螺栓8连接,但在本实施方式中,半导体模块1a、1b的集电极主电极5和发射极主电极6成为将一个向另一个插入的插入型。由此,连接变得更容易,使操作性提高。
实施方式8.
图14是表示本发明的实施方式8所涉及的半导体装置的剖面图。绝缘部件20利用螺栓8固定于半导体模块1a、1b的集电极主电极5和发射极主电极6上。在半导体模块1a、1b的集电极主电极5和发射极主电极6之间,在壳体4的上表面的最外周部,设置有凸部21。由此,通过在不需要电连接的接线中,延长主电极间的沿面距离,能够提高主电极间的绝缘性。
此外,在实施方式1~8中,各半导体模块1a、1b具有Si-IGBT和Si二极管,但并不限定于此,作为半导体芯片能够使用Si-IGBT、Si二极管、SiC-IGBT、SiC-MOSFET、SiC二极管中的任何一种或它们的组合。由SiC形成的半导体芯片由于耐电压性、容许电流密度较高,因此能够小型化。通过使用该小型化后的半导体芯片,能够将组装有该半导体芯片的半导体装置也小型化。另外,由于半导体芯片的耐热性较高,因此能够将散热装置的散热片小型化,能够使用空气冷却代替水冷部,所以能够将装置进一步小型化。另外,由于半导体芯片的电力损耗低、效率高,因此能够将装置高效率化。
标号的说明
1a 半导体模块(第1半导体模块)
1b 半导体模块(第2半导体模块)
2 IGBT(半导体芯片)
3 FWD(半导体芯片)
4 壳体
5 集电极主电极(主电极)
6 发射极主电极(主电极)
7 连接电极
17 卡挂部
18 槽
19 凹部
20 绝缘部件
21 凸部
权利要求书(按照条约第19条的修改)
1.(删除)
2.(修改后)一种半导体装置,其特征在于,具有:
第1及第2半导体模块,它们具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并被引出至所述壳体的上表面的主电极;以及
连接电极,其与所述第1及第2半导体模块的所述主电极连接以及固定,
所述连接电极仅由金属板构成,
所述连接电极的两端向下方弯曲成为卡挂部,
所述卡挂部所卡挂的槽设置在所述第1及第2半导体模块的所述壳体的所述上表面。
3.(修改后)根据权利要求2所述的半导体装置,其特征在于,
在所述壳体的所述上表面设置有凹部,
所述主电极被引出至所述凹部的底面,
在所述凹部内,将所述主电极和所述连接电极连接以及固定。
4.(修改后)根据权利要求2或3中任一项所述的半导体装置,其特征在于,
所述主电极的上表面相对于所述壳体的所述上表面没有台阶。
5.(删除)
6.(修改后)一种半导体装置,其特征在于,
具有第1及第2半导体模块,该第1及第2半导体模块具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并从所述壳体引出的主电极,
所述第2半导体模块的所述主电极被引出至所述第2半导体模块的所述壳体的上表面,
所述第1半导体模块的所述主电极延伸至所述第2半导体模块的所述壳体的上方,与所述第2半导体模块的所述主电极连接以及固定,
所述第1半导体模块的所述主电极的前端向下方弯曲成为卡挂部,
所述卡挂部所卡挂的槽设置在所述第2半导体模块的所述壳体的所述上表面。
7.(修改后)根据权利要求6所述的半导体装置,其特征在于,
在所述第2半导体模块的所述壳体的所述上表面设置有凹部,
所述第2半导体模块的所述主电极被引出至所述凹部的底面,
在所述凹部内,将所述第1半导体模块的所述主电极和所述第2半导体模块的所述主电极连接以及固定。
8.(修改后)根据权利要求6或7中任一项所述的半导体装置,其特征在于,
所述第1及第2半导体模块的所述主电极成为将一个向另一个插入的插入型。
9.一种半导体装置,其特征在于,具有:
第1及第2半导体模块,它们具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并被引出至所述壳体的上表面的主电极;以及
绝缘部件,其固定于所述第1及第2半导体模块的所述主电极上,
在所述第1及第2半导体模块的所述主电极之间,在所述壳体的所述上表面设置有凸部。
说明或声明(按照条约第19条的修改)
在权利要求2中追加权利要求1的内容并改为独立权利要求。相应地,将权利要求1删除。
将权利要求3的引用关系改为引用权利要求2。
将权利要求4的引用关系改为引用权利要求2或3。
在权利要求6中追加权利要求5的内容并改为独立权利要求。相应地,将权利要求5删除。
将权利要求7的引用关系改为引用权利要求6。
将权利要求8的引用关系改为引用权利要求6或7。
Claims (9)
1.一种半导体装置,其特征在于,具有:
第1及第2半导体模块,它们具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并被引出至所述壳体的上表面的主电极;以及
连接电极,其与所述第1及第2半导体模块的所述主电极连接以及固定,
所述连接电极仅由金属板构成。
2.根据权利要求1所述的半导体装置,其特征在于,
所述连接电极的两端向下方弯曲成为卡挂部,
所述卡挂部所卡挂的槽设置在所述第1及第2半导体模块的所述壳体的所述上表面。
3.根据权利要求1或2所述的半导体装置,其特征在于,
在所述壳体的所述上表面设置有凹部,
所述主电极被引出至所述凹部的底面,
在所述凹部内,将所述主电极和所述连接电极连接以及固定。
4.根据权利要求1~3中任一项所述的半导体装置,其特征在于,
所述主电极的上表面相对于所述壳体的所述上表面没有台阶。
5.一种半导体装置,其特征在于,
具有第1及第2半导体模块,该第1及第2半导体模块具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并从所述壳体引出的主电极,
所述第2半导体模块的所述主电极被引出至所述第2半导体模块的所述壳体的上表面,
所述第1半导体模块的所述主电极延伸至所述第2半导体模块的所述壳体的上方,与所述第2半导体模块的所述主电极连接以及固定。
6.根据权利要求5所述的半导体装置,其特征在于,
所述第1半导体模块的所述主电极的前端向下方弯曲成为卡挂部,
所述卡挂部所卡挂的槽设置在所述第2半导体模块的所述壳体的所述上表面。
7.根据权利要求5或6所述的半导体装置,其特征在于,
在所述第2半导体模块的所述壳体的所述上表面设置有凹部,
所述第2半导体模块的所述主电极被引出至所述凹部的底面,
在所述凹部内,将所述第1半导体模块的所述主电极和所述第2半导体模块的所述主电极连接以及固定。
8.根据权利要求5~7中任一项所述的半导体装置,其特征在于,
所述第1及第2半导体模块的所述主电极成为将一个向另一个插入的插入型。
9.一种半导体装置,其特征在于,具有:
第1及第2半导体模块,它们具有半导体芯片、包围所述半导体芯片的壳体、以及与所述半导体芯片连接并被引出至所述壳体的上表面的主电极;以及
绝缘部件,其固定于所述第1及第2半导体模块的所述主电极上,
在所述第1及第2半导体模块的所述主电极之间,在所述壳体的所述上表面设置有凸部。
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KR101642754B1 (ko) | 2016-07-26 |
CN104584213B (zh) | 2018-02-13 |
DE112012006842B4 (de) | 2022-06-09 |
KR20150036347A (ko) | 2015-04-07 |
US9622368B2 (en) | 2017-04-11 |
US20150138733A1 (en) | 2015-05-21 |
JPWO2014030254A1 (ja) | 2016-07-28 |
JP5854147B2 (ja) | 2016-02-09 |
WO2014030254A1 (ja) | 2014-02-27 |
DE112012006842T5 (de) | 2015-05-21 |
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