JPWO2011121725A1 - 電子装置および電子システム - Google Patents
電子装置および電子システム Download PDFInfo
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H05K2201/09209—Shape and layout details of conductors
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Abstract
Description
メインボードと、
それぞれ複数のはんだ接合部を有し、前記複数のはんだ接合部を介して前記メインボードに搭載された複数の電子基板と、
すべての前記電子基板に渡って前記はんだ接合部を一続きに接続した第1チェーンと、
前記第1チェーンの電気抵抗値、および前記第1チェーンの一部であり前記電子基板毎の前記はんだ接合部を一続きに接続した複数の第2チェーンの電気抵抗値を測定する測定部と、
前記測定部を用いて前記第1チェーンの電気抵抗値を取得し、前記第1チェーンの電気抵抗値が閾値以上であるとき、前記測定部を用いて、前記電子基板にそれぞれ対応する前記第2チェーンのうち前記電気抵抗値が前記閾値以上である第2チェーンを検出する制御部と、
を備える。
前記第1の態様に記載の複数の電子装置と、
前記複数の電子装置を制御する制御装置と、を備え、
前記制御装置は、前記複数の電子装置のそれぞれに検査指示信号を送信し、
前記電子装置は、
前記検査指示信号に応じて、前記第1チェーンの電気抵抗値を測定し、
前記第1チェーンの電気抵抗値が前記閾値未満のときは、前記電子装置におけるはんだ接合部に破断はないことを示す第1の検査結果情報を前記制御装置に送信し、
前記第1チェーンの電気抵抗値が前記閾値以上のときは、前記閾値以上の電気抵抗値を有する第2チェーンを検出し、検出した第2チェーンに対応する電子基板の前記はんだ接合部の少なくとも1つに破断が発生していることを示す第2の検査結果情報を前記制御装置に送信する
ことを特徴とする。
図1は、本発明の電子装置の一実施形態としてのSSD(Solid State Disk)の機能ブロック図である。
図15は、複数のSSDを用いたRAID構成を備えた電子システムを示す。RAID(1)〜RAID(N1)は、RAID構成を示すラベルである。本図ではRAID(1)の構成のみが具体的に示されているが、RAIDコントローラ31に、他のRAID(2)〜RAID(N1)の構成が接続されてもよい。
図16は、多層構造型NANDフラッシュパッケージ41を複数、メインボード上に搭載したSSDを示す斜視図である。このSSDは、図1の各NANDフラッシュパッケージをそれぞれ多層構造型NANDフラッシュパッケージに置換したものに相当する。SSDコントローラおよび電気特性測定部等の要素の図示は、簡単のため省略している。
11・・・メインボード(実装基板)
12・・・コネクタ(通信インターフェース(IF))
13・・・ボス穴
15・・・SSDコントローラ(制御部)
16・・・コンデンサ
17・・・電気特性測定部
41:多層構造型NANDフラッシュパッケージ
Claims (7)
- メインボードと、
それぞれ複数のはんだ接合部を有し、前記複数のはんだ接合部を介して前記メインボードに搭載された複数の電子基板と、
すべての前記電子基板に渡って前記はんだ接合部を一続きに接続した第1チェーンと、
前記第1チェーンの電気抵抗値、および前記第1チェーンの一部であり前記電子基板毎の前記はんだ接合部を一続きに接続した複数の第2チェーンの電気抵抗値を測定する測定部と、
前記測定部を用いて前記第1チェーンの電気抵抗値を取得し、前記第1チェーンの電気抵抗値が閾値以上であるとき、前記測定部を用いて、前記電子基板にそれぞれ対応する前記第2チェーンのうち前記電気抵抗値が前記閾値以上である第2チェーンを検出する制御部と、
を備えた電子装置。 - 前記測定部は、前記検出された第2チェーンのうちそれぞれ異なる範囲の部分である複数の第3チェーンの電気抵抗値をそれぞれ測定し、
前記制御部は、前記測定部を用いて、前記複数の第3チェーンのうち前記電気抵抗値が閾値以上の第3チェーンを検出する
ことを特徴とする請求項1に記載の電子装置。 - 前記電子基板が前記メインボードの厚さ方向に積み重ねられ、
前記電子基板は前記はんだ接合部を介して互いに接合され、
前記第1チェーンは、積み重ねられた電子基板の前記はんだ接合部を一続きに接続した、
ことを特徴とする請求項2に記載の電子装置。 - 前記第1チェーンは、前記メインボード側の配線と、前記電子基板側の配線を交互に用いて前記はんだ接合部を接続する
ことを特徴とする請求項1に記載の電子装置。 - 前記第1チェーンにより接続される前記はんだ接合部は、前記電子基板のはんだ接合部のうち最外周に位置する接合部である
ことを特徴とする請求項1に記載の電子装置。 - 前記第1チェーンにより接続される前記はんだ接合部はダミー接合部である
ことを特徴とする請求項1に記載の電子装置。 - 請求項1に記載の複数の電子装置と、
前記複数の電子装置を制御する制御装置と、を備え、
前記制御装置は、前記複数の電子装置のそれぞれに検査指示信号を送信し、
前記電子装置は、
前記検査指示信号に応じて、前記第1チェーンの電気抵抗値を測定し、
前記第1チェーンの電気抵抗値が前記閾値未満のときは、前記電子装置におけるはんだ接合部に破断はないことを示す第1の検査結果情報を前記制御装置に送信し、
前記第1チェーンの電気抵抗値が前記閾値以上のときは、前記閾値以上の電気抵抗値を有する第2チェーンを検出し、検出した第2チェーンに対応する電子基板の前記はんだ接合部の少なくとも1つに破断が発生していることを示す第2の検査結果情報を前記制御装置に送信する
ことを特徴とする電子システム。
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JP5175911B2 (ja) * | 2010-09-16 | 2013-04-03 | 株式会社東芝 | はんだ接合部の寿命予測方法、はんだ接合部の寿命予測装置 |
JP2013083619A (ja) * | 2011-09-27 | 2013-05-09 | Elpida Memory Inc | 半導体チップ、半導体装置、及びその測定方法 |
JP6081055B2 (ja) | 2011-11-16 | 2017-02-15 | 株式会社東芝 | 電子部品および測定方法 |
JP2013247244A (ja) * | 2012-05-25 | 2013-12-09 | Toshiba Corp | 電子装置、破損推定方法、寿命推定方法 |
JP5894515B2 (ja) * | 2012-09-28 | 2016-03-30 | 株式会社東芝 | 半導体装置、寿命推定装置、寿命推定方法 |
JP6076208B2 (ja) * | 2013-06-21 | 2017-02-08 | 株式会社日本マイクロニクス | 配線基板の検査装置および配線基板の検査方法 |
US9619381B2 (en) | 2013-12-24 | 2017-04-11 | International Business Machines Corporation | Collaborative health management in a storage system |
KR102252380B1 (ko) * | 2014-04-24 | 2021-05-14 | 삼성전자주식회사 | 테이프 배선 기판, 반도체 패키지 및 상기 반도체 패키지를 포함한 디스플레이 장치 |
KR102269914B1 (ko) * | 2015-02-13 | 2021-06-29 | 삼성디스플레이 주식회사 | 구동 칩 및 구동 칩을 포함하는 표시 장치 |
JP6139619B2 (ja) * | 2015-09-09 | 2017-05-31 | 株式会社東芝 | 電子部品および測定方法 |
JP6520640B2 (ja) * | 2015-10-23 | 2019-05-29 | 富士ゼロックス株式会社 | 画像形成システム |
WO2017109974A1 (ja) * | 2015-12-25 | 2017-06-29 | 株式会社日立製作所 | 半導体装置及び半導体破断予兆システム |
KR20210072178A (ko) | 2019-12-06 | 2021-06-17 | 삼성전자주식회사 | 테스트 범프들을 포함하는 반도체 패키지 |
US11550506B2 (en) * | 2020-09-29 | 2023-01-10 | EMC IP Holding Company LLC | Systems and methods for accessing hybrid storage devices |
US11586508B2 (en) | 2020-09-29 | 2023-02-21 | EMC IP Holding Company LLC | Systems and methods for backing up volatile storage devices |
US11755223B2 (en) | 2020-09-29 | 2023-09-12 | EMC IP Holding Company LLC | Systems for modular hybrid storage devices |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0648706B2 (ja) * | 1985-02-20 | 1994-06-22 | 日立超エル・エス・アイ・エンジニアリング株式会社 | 配線パタ−ンの検査方法及びその検査装置 |
US6002177A (en) * | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
JP3265197B2 (ja) | 1996-09-12 | 2002-03-11 | 株式会社東芝 | 半導体装置 |
JP3459765B2 (ja) * | 1997-07-16 | 2003-10-27 | シャープ株式会社 | 実装検査システム |
US6452502B1 (en) * | 1998-10-15 | 2002-09-17 | Intel Corporation | Method and apparatus for early detection of reliability degradation of electronic devices |
US6564986B1 (en) * | 2001-03-08 | 2003-05-20 | Xilinx, Inc. | Method and assembly for testing solder joint fractures between integrated circuit package and printed circuit board |
US6940288B2 (en) * | 2003-06-04 | 2005-09-06 | Hewlett-Packard Development Company, L.P. | Apparatus and method for monitoring and predicting failures in system interconnect |
US6895353B2 (en) * | 2003-06-04 | 2005-05-17 | Hewlett-Packard Development Company, L.P. | Apparatus and method for monitoring high impedance failures in chip interconnects |
JP4063796B2 (ja) * | 2004-06-30 | 2008-03-19 | 日本電気株式会社 | 積層型半導体装置 |
JP2006165325A (ja) * | 2004-12-08 | 2006-06-22 | Toyota Motor Corp | Icパッケージを実装した基板の配線構造、及び電気接続不良検査方法 |
JP4577839B2 (ja) | 2005-07-26 | 2010-11-10 | レノボ・シンガポール・プライベート・リミテッド | 半田ボールを有するパッケージを用いた電子機器、および半田ボールを有するパッケージの異常状態検知方法 |
US7573282B2 (en) * | 2006-04-26 | 2009-08-11 | Hewlett-Packard Development Company, L.P. | Ball grid array connection monitoring system and method |
JP4187022B2 (ja) * | 2006-08-23 | 2008-11-26 | ソニー株式会社 | 半導体装置、半導体集積回路およびバンプ抵抗測定方法 |
JP2010093231A (ja) * | 2008-09-11 | 2010-04-22 | Yokogawa Electric Corp | 半導体装置の実装構造 |
JP4776703B2 (ja) | 2009-01-23 | 2011-09-21 | 株式会社東芝 | 半導体記憶装置を用いたraidシステム及びその制御方法 |
JP5025676B2 (ja) | 2009-03-25 | 2012-09-12 | 株式会社東芝 | 監視装置および監視方法 |
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US9383401B2 (en) | 2016-07-05 |
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