JPWO2011074589A1 - エッチング液及びこれを用いた半導体装置の製造方法 - Google Patents
エッチング液及びこれを用いた半導体装置の製造方法 Download PDFInfo
- Publication number
- JPWO2011074589A1 JPWO2011074589A1 JP2011546137A JP2011546137A JPWO2011074589A1 JP WO2011074589 A1 JPWO2011074589 A1 JP WO2011074589A1 JP 2011546137 A JP2011546137 A JP 2011546137A JP 2011546137 A JP2011546137 A JP 2011546137A JP WO2011074589 A1 JPWO2011074589 A1 JP WO2011074589A1
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- Prior art keywords
- etching
- semiconductor device
- copper
- layer
- hydrogen peroxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 238000005530 etching Methods 0.000 title claims abstract description 183
- 239000004065 semiconductor Substances 0.000 title claims abstract description 109
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 73
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 96
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 95
- 229910052802 copper Inorganic materials 0.000 claims abstract description 95
- 239000010949 copper Substances 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 74
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 30
- BJEPYKJPYRNKOW-REOHCLBHSA-N (S)-malic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O BJEPYKJPYRNKOW-REOHCLBHSA-N 0.000 claims abstract description 22
- BJEPYKJPYRNKOW-UHFFFAOYSA-N alpha-hydroxysuccinic acid Natural products OC(=O)C(O)CC(O)=O BJEPYKJPYRNKOW-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000001630 malic acid Substances 0.000 claims abstract description 22
- 235000011090 malic acid Nutrition 0.000 claims abstract description 22
- 239000007788 liquid Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 118
- 229910052759 nickel Inorganic materials 0.000 abstract description 59
- 229920002120 photoresistant polymer Polymers 0.000 description 33
- 239000010408 film Substances 0.000 description 32
- 230000000052 comparative effect Effects 0.000 description 27
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 21
- 229910052719 titanium Inorganic materials 0.000 description 21
- 239000010936 titanium Substances 0.000 description 21
- 238000011156 evaluation Methods 0.000 description 14
- 238000009713 electroplating Methods 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000354 decomposition reaction Methods 0.000 description 5
- 150000007524 organic acids Chemical class 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 150000001261 hydroxy acids Chemical class 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005502 peroxidation Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005342 ion exchange Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/18—Acidic compositions for etching copper or alloys thereof
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/44—Compositions for etching metallic material from a metallic material substrate of different composition
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- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02311—Additive methods
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- H01L2224/02331—Multilayer structure
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Abstract
Description
より具体的には、特許文献1で開示されるバンプ電極の形成方法は、導電性材料で構成される電極が設けられた基板上に、該電極部分を開口させたカバー膜を設け、さらに銅などをスパッタして形成した下地導電膜、該電極から対応するバンプ電極を形成する箇所まで延在する開口部を有するフォトレジスト膜、及び該開口部に電解めっきにより銅配線ならびにニッケル配線を順次設けた後、フォトレジスト膜を除去し、当該下地導電膜のうち配線で覆われていない部分をエッチングするという、エッチングの工程を有する。当該エッチングの工程で下地導電膜を形成する銅をエッチングする際、より高い性能を確保するためには、電解めっきにより形成したニッケル配線をエッチングしないことが望ましい。
102,202,302,402.電極
103,203,303,304.絶縁膜
104,204,304,404.開口部
105,205,305,405.チタン層
106,206,306,406.銅層
107.フォトレジスト(I)
108,208,308,408.開口部
109,209,409.銅層
110.フォトレジスト(II)
111,211.開口部
112,210,309,410.ニッケル層
113,310,411.金層
114,212.絶縁膜
116.銅層の残渣
117,311,412.凹み部
207,307,407.フォトレジスト
213.バンプ電極
214.肩削れ
[2]過酸化水素とリンゴ酸とを含み、過酸化水素の含有量が0.75〜12質量%、リンゴ酸の含有量が1.5〜25質量%、かつ過酸化水素とリンゴ酸とのモル比が0.2〜6の範囲内である、電極を有する半導体基板を用いた半導体装置の製造に用いられる、銅の選択的エッチング用エッチング液。
[3]過酸化水素の含有量が1.5〜7質量%、クエン酸の含有量が2〜15質量%、かつ過酸化水素とクエン酸とのモル比が0.3〜5の範囲内である前記1に記載の銅の選択的エッチング用エッチング液。
[4]過酸化水素の含有量が1.5〜4.5質量%、リンゴ酸の含有量が1〜15質量%、かつ過酸化水素とリンゴ酸とのモル比が0.3〜6の範囲内である前記2に記載の銅の選択的エッチング用エッチング液。
[5]前記1〜4のいずれかに記載の銅の選択的エッチング用エッチング液を用いるエッチング工程を有する半導体装置の製造方法。
[6]半導体装置が、バンプ電極を有するものである前記5に記載の半導体装置の製造方法。
[7]電極を有する半導体基板の該電極上に配線を形成する再配線形成工程を有する前記5又は6に記載の半導体装置の製造方法。
[8]半導体装置が、銅を用いて形成される配線を有するものである前記5〜7のいずれかに記載の半導体装置の製造方法
本発明のエッチング液は、電極を有する半導体基板を用いた半導体装置の製造工程における、エッチング工程で用いられ、過酸化水素と有機酸成分として特定のヒドロキシ酸であるクエン酸又はリンゴ酸とを含み、特定の組成を有する液である。
本発明の半導体装置の製造方法は、本発明のエッチング液を用いるエッチング工程を有し、該半導体装置がバンプ電極を有していることが好ましい。また、当該エッチング工程は、ニッケルをエッチングせずに銅を選択的にエッチングしうる本発明のエッチング液の特徴を有効に活用する観点から、ニッケルからなる部材と銅からなる部材とが同時にエッチング液に触れうる状態であり、該銅からなる部材をエッチングすることを特徴とするものであることが好ましい。以下に、本発明の製造方法をより具体的に説明する。
本発明の半導体装置の製造方法の第一の態様(以下、製造方法Aという。)は、シード層形成工程A1、フォトレジスト(I)形成工程A2、再配線形成工程A3、フォトレジスト(II)形成工程A4、バンプ電極形成工程A5、本発明のエッチング液を用いるエッチング工程A6を順に有するものである。本発明の製造方法Aを、図A(a)〜(p)を用いて、詳細に説明する。
工程A1は、電極が設けられた半導体基板上に、該電極が露出する開口部を有する絶縁膜を設け、さらに該開口部及び該絶縁膜上にシード層を形成する、シード層形成工程である。ここで、電極が設けられた半導体基板とは、図A(a)に示されるように、例えばシリコン基板101の表面に、周知の製造方法により製造された半導体素子を含む電子回路が形成され、該電子回路が形成された面に、パッドと呼ばれる、例えばアルミニウムなどの導電性材料からなる電極102が形成されたものである。導電性材料としては、アルミニウムのほか、チタンや銅を添加したアルミニウム合金や、銅又は銅合金、金なども好ましく挙げることができる。
この電極102が設けられた半導体基板101上(該電極が形成された面)に、酸化ケイ素などからなる絶縁膜103が形成され、該絶縁膜103には、電極102に対応する開口部104が、電極102を露出するように形成する。
工程A2は、前記シード層の電極上に設けた箇所及びバンプ電極を形成する箇所を含む領域を開口し、該シード層を露出する開口部108を有するフォトレジスト(I)107を形成する、フォトレジスト(I)形成工程である。まず、図A(d)に示されるように、銅層106上にフォトレジスト(I)107を形成する。次いで、該フォトレジストを露光、現像することにより、図A(e)に示されるように、シード層の電極102上に設けた箇所と後述するバンプ電極を形成する箇所を含む領域までをつなぐ再配線を形成するための開口部108を有するフォトレジスト(I)107を形成する。
工程A3は、前記開口部108に配線を設けて再配線する、再配線形成工程である。この再配線形成工程により、電極102を有する半導体基板101の該電極102上に配線を形成する再配線の形成がなされる。配線は、銅やニッケルなどの材料が使用され、図A(f)に示されるように、少なくとも銅により形成される銅層109を有することが好ましい。また、配線は通常銅やニッケルを電解めっき処理することにより設けられる。
工程A4は、図A(g)及び(h)で示されるように、工程A3で形成したフォトレジスト(I)107を除去し、シード層及び配線を被覆するようにフォトレジスト(II)110を形成し、さらに露光、現像することによりフォトレジスト(II)110にバンプ電極を形成するための開口部111を形成する、フォトレジスト(II)形成工程である。このフォトレジスト(II)110は、常法により設ければよい。
工程A5は、図A(i)及び(j)に示されるように、前記フォトレジスト(II)110のバンプ電極を形成する箇所に、再配線の銅層109が露出するように開口部111を設け、該開口部111にニッケルからなるニッケル層112を少なくとも一層有するバンプ電極を形成する、バンプ電極形成工程である。
バンプ電極は、錫、鉛やこれらの合金(錫−鉛合金)のほか、金、パラジウム、ニッケル、銅などを用いて、電解めっきにより形成することができ、一層または複数層により形成することができる。例えば、図A(j)のように、ニッケル層112を設けた後に、金層113を設けてバンプ電極を形成することができる。本発明の製造方法においては、バンプ電極を形成する少なくとも一層がニッケルからなるニッケル層112であると、本発明のエッチング液が有するニッケルをエッチングせずに銅を選択的にエッチングできるという性能を有効に活用することができる。
工程A6は、図A(k)のように前記フォトレジスト(II)110を除去してから、さらに図A(l)及び(m)に示されるように、チタン層105や銅層106などのシード層のうち、銅層109のような配線で覆われていない露出部分をエッチングする、エッチング工程である。該エッチング工程においては、本発明のエッチング液が用いられることを要する。本発明のエッチング液を用いることで、エッチング液中の過酸化水素の管理が容易であり、かつ適度なエッチング速度と良好なエッチング性能が得られ、ニッケルをエッチングせずに銅を選択的にエッチングすることが可能となる。
本発明の半導体装置の製造方法の第二の態様(以下、製造方法Bという。)は、シード層成工程B1、フォトレジスト形成工程B2、再配線形成工程B3、本発明のエッチング液を用いるエッチング工程B4、絶縁膜形成工程B5、及びバンプ電極形成工程B6を順に有するものである。本発明の製造方法Bを、図B(a)〜(m)を用いて、詳細に説明する。
工程B1は、電極202が設けられた半導体基板201上に、該電極202が露出する開口部204を有する絶縁膜203を設け、さらに該開口部204及び該絶縁膜203上にシード層を形成する、シード層形成工程であり、図B(a)〜(c)に示されるように、前記工程A1と同じである。
工程B2は、工程B1で設けられたチタン層205及び銅層206からなるシード層の電極202上に設けた箇所及びバンプ電極を形成する箇所を含む領域を開口し、該シード層を露出する開口部208を有するフォトレジスト207を形成する、フォトレジスト形成工程である。工程B2は、図B(d)及び(e)に示されるように、前記工程A2と同じである。
工程B3は、前記開口部208に配線を設けて再配線する、再配線形成工程である。配線は、銅やニッケルなどの材料が使用される。例えば、図B(f)及び(g)に示されるように、銅層209とニッケル層210とを順に積層して再配線を形成することができる。また、配線は通常銅やニッケルを電解めっき処理することにより設けられる。
工程B4は、図B(h)のように前記フォトレジスト207を除去してから、さらに図B(i)及び(j)に示されるように、チタン層205や銅層206などのシード層のうち、銅層209及びニッケル層210のような配線で覆われていない露出部分をエッチングする、エッチング工程である。該エッチング工程においては、本発明のエッチング液が用いられることを要する。本発明のエッチング液を用いることで、エッチング液中の過酸化水素の管理が容易であり、かつ適度なエッチング速度と良好なエッチング性能が得られ、ニッケルをエッチングせずに銅を選択的にエッチングすることが可能となる。工程B4におけるエッチングの諸条件は、工程A6と同じである。
工程B5は、図B(k)に示されるように、バンプ電極を設ける領域に開口部211を有する絶縁膜212を形成する絶縁膜形成工程である。
絶縁膜212の形成には、エポキシやポリイミドなどの有機絶縁材料が好ましく用いられる。絶縁膜212は、該有機絶縁材料をスピンコートなどにより塗工し、再配線部分(図Bの場合はニッケル層210)を露出する開口部211を設けて形成される。絶縁膜212に用いられる有機絶縁材料により、その形成方法は異なるが、例えば有機絶縁材料を塗工した後、フォトレジストを塗布し、該フォトレジストの露光、現像の後、絶縁膜212をエッチングすることにより開口部211を設けたり、あるいは該有機絶縁材料が感光性の材料である場合、該有機絶縁材料を塗工した後、直接露光し、現像することにより、開口部211を有する絶縁膜212を形成することもできる。
工程B6は、開口部211にバンプ電極213を形成する、バンプ電極形成工程である。バンプ電極213は、はんだボールを実装して設けることができる。
本発明の半導体装置の製造方法の第三の態様(以下、製造方法Cという。)は、シード層成工程C1、フォトレジスト形成工程C2、バンプ電極形成工程C3、及び本発明のエッチング液を用いるエッチング工程C4を順に有するものである。本発明の製造方法Cを、図C(a)〜(k)を用いて、詳細に説明する。
工程C1は、電極302が設けられた半導体基板301上に、該電極302が露出する開口部304を有する絶縁膜303を設け、さらに該開口部304及び該絶縁膜303上にシード層を形成する、シード層形成工程であり、図C(a)〜(c)に示されるように、前記工程A1あるいはB1と同じである。
工程C2は、工程C1で設けられたチタン層305及び銅層306からなるシード層の電極302上に設けた箇所を含む領域を開口し、該シード層を露出する開口部308を有するフォトレジスト307を形成する、フォトレジスト形成工程である。工程C2は、図C(d)及び(e)に示されるように、前記工程A2あるいはB2と同じである。
工程C3は、開口部308にニッケルからなるニッケル層309を少なくとも一層有するバンプ電極を形成する、バンプ電極形成工程である。工程C3は、開口部111の形成を除いて工程A5と同じであり、図C(f)及び(g)に示されるように、ニッケル層309を設けた後に、金層310を設けてバンプ電極を形成することができる。
工程C4は、図C(h)のように前記フォトレジスト307を除去してから、さらに図C(i)及び(j)に示されるように、チタン層305や銅層306などのシード層のうち、ニッケル層309や金層310のようなバンプ電極で覆われていない露出部分をエッチングする、エッチング工程である。該エッチング工程においては、本発明のエッチング液が用いられることを要する。本発明のエッチング液を用いることで、エッチング液中の過酸化水素の管理が容易であり、かつ適度なエッチング速度と良好なエッチング性能が得られ、ニッケルをエッチングせずに銅を選択的にエッチングすることが可能となる。工程C4におけるエッチングの諸条件は、工程A6と同じである。
本発明の半導体装置の製造方法の第四の態様(以下、製造方法Dという。)は、シード層成工程D1、フォトレジスト形成工程D2、バンプ電極形成工程D3、及び本発明のエッチング液を用いるエッチング工程D4を順に有するものである。本発明の製造方法Dの書く工程は、図D(a)〜(l)で示される。
図D(a)〜(l)に示されるように、製造方法Dは、バンプ電極形成工程D3において、銅層409、ニッケル層410及び金層411の三層からなるバンプ電極とした以外は、製造方法Cと同じである。
評価項目1.銅層(配線)のエッチングレートの算出
スパッタにより銅を成膜(銅膜の厚さ:5000Å)したシリコン基板を、各実施例及び比較例のエッチング液に、30℃で2分間浸漬し、浸漬前後の膜厚変化を蛍光X線分析装置(「SEA2110L)」,エスエスアイナノテクノロジー社製)を用いて測定し、エッチングレート(μm/分)を算出した。
評価項目2.ニッケルのエッチングレートの算出
鋼材に電解めっきによりニッケルを成膜(ニッケル膜の厚さ:5μm)した基板を、各実施例及び比較例のエッチング液に、30℃で1時間浸漬し、浸漬前後の重量を測定し、エッチングレート(Å/分)を算出した。
評価項目3.エッチング液(過酸化水素)の安定性の評価
各実施例及び比較例のエッチング液を、50℃の条件下で1週間放置した際の、各エッチング液中の過酸化水素の分解率を求め、以下の基準で評価した。分解率が10%未満であれば安定性は優れており、10%以上20%未満であれば経済性の点で十分ではなく、安全面での液管理に注意を要するものの実用上問題ない程度であり、20%以上のときは使用できない程度と判断した。
○ :分解率が10%未満
△ :分解率が10%以上20%未満
× :分解率が20%以上
評価項目4.半導体基板を用いたエッチングの評価
各実施例及び比較例のエッチング液を用い、製造方法A〜Dの手順で半導体装置を製造した。このとき、エッチング温度は30℃であり、エッチング時間は、当該半導体装置におけるシード層としてスパッタによる設けた銅の膜(膜厚:3000Å)を、上記評価項目1で得たエッチングレートで除して算出した時間の2倍とした。
得られた半導体装置について、電解めっきにより設けたニッケル層の凹み部(製造方法A、C及びDの場合)、又は肩削れ(製造方法Bの場合)の状態、及びシード層として設けた銅層のエッチング後の残存状態を、各々下記の基準で評価した。
(ニッケル層の凹み部または肩削れの状態について)
○ :ニッケル層の凹み部又は肩削れは全く確認されなかった
△ :ニッケル層の凹み部又は肩削れは若干あるものの、実用上問題ない
× :ニッケル層の凹み部又は肩削れが著しく、使用できない
(銅層の残存状態)
○ :エッチング後、銅層の残存は全く確認されなかった
△ :エッチング後、銅層の残存がわずかに確認され、実用上支障が生じた
× :エッチング後、銅層の残存が著しく、使用できない
表1及び2に示される配合組成(質量%)に従い、各実施例及び比較例で用いるエッチング液を調整した。
製造方法A(図A(a)〜(n))の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。ここで、図A(k)〜(m)に示されるエッチング工程において、各実施例及び比較例のエッチング液を用いて、フォトレジスト110、銅層106及びチタン層105のエッチングを順に行った。
また、チタン層105及び銅層106はいずれもスパッタにて設け、その層厚はいずれも3000Åであり、再配線の銅層109及びバンプ電極を形成するニッケル層112及び金層113は、いずれも電解めっきにより設け、その層厚は各々3μm、2μm及び5μmである。各実施例及び比較例で得られた半導体装置について、上記評価項目4に従い評価した結果を表1及び表2に示す。また、各実施例及び比較例で用いたエッチング液について、上記評価項目1〜3に従い評価した結果を表1及び表2に示す。
製造方法B(図B(a)〜(l))の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。チタン層205及び銅層106はいずれもスパッタにて設け、その層厚はその層厚はいずれも3000Åであり、再配線工程において設けた銅層209及びニッケル層210は、いずれも電解めっきにより設け、その層厚は各々3μm及び2μmである。
図B(h)〜(j)に示されるエッチング工程において、エッチング液を用いて、フォトレジスト207、銅層206及びチタン層205のエッチングを順に行った。ここで、実施例B1〜B51及び比較例B1〜B49で使用したエッチング液は、各々実施例A1〜A51及び比較例A1〜A49で用いたエッチング液と同じであり、評価項目1〜3の評価も同じである。
各実施例及び比較例で得られた半導体装置について、上記評価項目4に従い評価したところ、実施例B1〜B51及び比較例B1〜B49は、各々同じエッチング液を使用している実施例A1〜A51及び比較例A1〜A49と同じとなった。これらの結果を表1及び表2に示す。
製造方法C(図C(a)〜(j))の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。チタン層305及び銅層306はいずれもスパッタにて設け、その層厚はその層厚はいずれも3000Åであり、バンプ電極として設けたニッケル層309、金層310は、いずれも電解めっきにより設け、その層厚は各々3μm及び10μmである。
図C(h)〜(j)に示されるエッチング工程において、エッチング液を用いて、フォトレジスト307、銅層306及びチタン層305のエッチングを順に行った。ここで、実施例C1〜C51及び比較例C1〜C49で使用したエッチング液は、各々実施例A1〜A51及び比較例A1〜A49で用いたエッチング液と同じであり、評価項目1〜3の評価も同じである。
各実施例及び比較例で得られた半導体装置について、上記評価項目4に従い評価したところ、実施例C1〜C51及び比較例C1〜C49は、各々同じエッチング液を使用している実施例A1〜A51及び比較例A1〜A49と同じとなった。これらの結果を表1及び表2に示す。
製造方法D(図D(a)〜(k))の手順に従い、電極及びバンプ電極を有する半導体装置を作製した。チタン層405及び銅層406はいずれもスパッタにて設け、その層厚はその層厚はいずれも3000Åであり、バンプ電極として設けた銅層409、ニッケル層410、金層411は、いずれも電解めっきにより設け、その層厚は各々10μm、3μm及び5μmである。
図D(i)〜(k)に示されるエッチング工程において、エッチング液を用いて、フォトレジスト407、銅層406及びチタン層405のエッチングを順に行った。ここで、実施例D1〜D51及び比較例D1〜D49で使用したエッチング液は、各々実施例A1〜A51及び比較例A1〜A49で用いたエッチング液と同じであり、評価項目1〜3の評価も同じである。
各実施例及び比較例で得られた半導体装置について、上記評価項目4に従い評価したところ、実施例D1〜D51及び比較例D1〜D49は、各々同じエッチング液を使用している実施例A1〜A51及び比較例A1〜A49と同じとなった。これらの結果を表1及び表2に示す。
Claims (8)
- 過酸化水素とクエン酸とを含み、過酸化水素の含有量が0.75〜12質量%、クエン酸の含有量が1〜20質量%、かつ過酸化水素とクエン酸とのモル比が0.3〜5の範囲内である、電極を有する半導体基板を用いた半導体装置の製造に用いられる、銅の選択的エッチング用エッチング液。
- 過酸化水素とリンゴ酸とを含み、過酸化水素の含有量が0.75〜12質量%、リンゴ酸の含有量が1.5〜25質量%、かつ過酸化水素とリンゴ酸とのモル比が0.2〜6の範囲内である、電極を有する半導体基板を用いた半導体装置の製造に用いられる、銅の選択的エッチング用エッチング液。
- 過酸化水素の含有量が1.5〜7質量%、クエン酸の含有量が2〜15質量%、かつ過酸化水素とクエン酸とのモル比が0.3〜5の範囲内である請求項1に記載の銅の選択的エッチング用エッチング液。
- 過酸化水素の含有量が1.5〜4.5質量%、リンゴ酸の含有量が1〜15質量%、かつ過酸化水素とリンゴ酸とのモル比が0.3〜6の範囲内である請求項2に記載の銅の選択的エッチング用エッチング液。
- 請求項1〜4のいずれかに記載の銅の選択的エッチング用エッチング液を用いるエッチング工程を有する半導体装置の製造方法。
- 半導体装置がバンプ電極を有するものである請求項5に記載の半導体装置の製造方法。
- 電極を有する半導体基板の該電極上に配線を形成する再配線形成工程を有する請求項5又は6に記載の半導体装置の製造方法。
- 半導体装置が銅を用いて形成される配線を有する請求項5〜7のいずれかに記載の半導体装置の製造方法。
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