CN102687251A - 蚀刻液及使用其的半导体装置的制造方法 - Google Patents

蚀刻液及使用其的半导体装置的制造方法 Download PDF

Info

Publication number
CN102687251A
CN102687251A CN201080057354XA CN201080057354A CN102687251A CN 102687251 A CN102687251 A CN 102687251A CN 201080057354X A CN201080057354X A CN 201080057354XA CN 201080057354 A CN201080057354 A CN 201080057354A CN 102687251 A CN102687251 A CN 102687251A
Authority
CN
China
Prior art keywords
semiconductor device
etching
hydrogen peroxide
copper
etching solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201080057354XA
Other languages
English (en)
Other versions
CN102687251B (zh
Inventor
细见彰良
大前健祐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Publication of CN102687251A publication Critical patent/CN102687251A/zh
Application granted granted Critical
Publication of CN102687251B publication Critical patent/CN102687251B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/18—Acidic compositions for etching copper or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/44—Compositions for etching metallic material from a metallic material substrate of different composition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03916—Methods of manufacturing bonding areas involving a specific sequence of method steps a passivation layer being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供在具有电极的半导体基板的再布线中使用的、能选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。含有过氧化氢和柠檬酸、且过氧化氢的含量为0.75~12质量%、柠檬酸的含量为1~20质量%、且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内的在半导体基板的再布线中使用的蚀刻液；含有过氧化氢和苹果酸、且过氧化氢的含量为0.75~12质量%、苹果酸的含量为1.5~25质量%、且过氧化氢和苹果酸的摩尔比在0.2~6的范围内的在半导体基板的再布线中使用的用于选择性蚀刻铜的蚀刻液、及使用这些蚀刻液的半导体装置的制造方法。

Description

蚀刻液及使用其的半导体装置的制造方法
技术领域
本发明涉及在使用了具有电极的半导体基板的半导体装置的制造中使用的、能够选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。
背景技术
近年来，伴随电子设备的小型化的要求，正在加快该设备中使用的半导体装置的小型化、高集成化及多功能化，连接半导体装置和电子设备的电极有增加的倾向。作为这里使用的半导体装置，多使用在由铝等形成的半导体焊盘上再布线、设置凸块电极的半导体装置。为了同时应对如上所述的半导体装置的小型化、及电极数的增加，提出了各种各样的凸块电极的形成方法（例如专利文献1及2）。
这些凸块电极的形成方法中包括设置在半导体焊盘（以下也简称为电极。）上的布线的蚀刻工序，有时必须在不蚀刻布线中使用的镍的条件下蚀刻铜。
更具体而言，专利文献1中公开的凸块电极的形成方法具有如下的蚀刻工序：在设置有由导电性材料构成的电极的基板上设置露出该电极部分的覆盖膜，进而依次设置通过溅射铜等而形成的基底导电膜、具有从该电极处延伸至形成对应的凸块电极处的开口部的光致抗蚀膜，并且在该开口部通过电镀设置铜布线以及镍布线，之后，去除光致抗蚀膜，蚀刻该基底导电膜中未被布线覆盖的部分。该蚀刻工序中，在蚀刻用于形成基底导电膜的铜时，为了确保更高的性能，理想的是不蚀刻通过电镀形成的镍布线。
另外，专利文献2中公开的凸块电极的形成方法具有如下的蚀刻工序：在设置有铝电极的半导体基板上，由钛、铜通过溅射形成晶种层，形成用于形成凸块电极的部分开口的抗蚀层，在该开口处，通过电镀等形成层叠钛、铜、镍等多种金属而成的势垒金属层，进而在其上通过电镀形成成为凸块电极的焊料，之后，去除该抗蚀层，然后蚀刻该晶种层。在该蚀刻工序中，蚀刻用于形成晶种层的钛、铜时，为了确保更高的性能，理想的是不蚀刻用于形成势垒金属层的镍等金属。
但是，在专利文献1、专利文献2的蚀刻工序中，没有对该工序中使用的蚀刻液进行充分的研究，导致了在蚀刻由铜形成的布线等部件时由镍形成的部件也被蚀刻。如上所述，伴随半导体装置的小型化、高集成化及多功能化，使用半导体装置的顾客所要求的性能变严格，这时，利用到目前为止的半导体装置的制造方法制造的半导体装置产生不能充分满足该要求性能的情况的倾向变明显。
专利文献1：日本特开平11-195665号公报
专利文献2：日本特开2005-175128号公报
发明内容
发明要解决的问题
本发明是在这样的情况下进行的发明，其目的在于，提供在使用了具有电极的半导体基板的半导体装置的制造中使用的、能选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。
用于解决问题的方案
本发明人等为了达成上述目的进行了深入研究，结果发现，通过使用以特定组成含有过氧化氢和作为有机酸成分的特定的羟基酸即柠檬酸或苹果酸的蚀刻液，可以解决该课题。即，本发明提供以下的在使用了具有电极的半导体基板的半导体装置的制造中使用的、能选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。
[1]一种用于选择性蚀刻铜的蚀刻液，其在使用了具有电极的半导体基板的半导体装置的制造中使用，其含有过氧化氢和柠檬酸，过氧化氢的含量为0.75~12质量%、柠檬酸的含量为1~20质量%、且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。
[2]一种用于选择性蚀刻铜的蚀刻液，其在使用了具有电极的半导体基板的半导体装置的制造中使用，其含有过氧化氢和苹果酸，过氧化氢的含量为0.75~12质量%、苹果酸的含量为1.5~25质量%、且过氧化氢和苹果酸的摩尔比在0.2~6的范围内。
[3]根据上述1所述的用于选择性蚀刻铜的蚀刻液，其中，过氧化氢的含量为1.5~7质量%、柠檬酸的含量为2~15质量%、且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。
[4]根据上述2所述的用于选择性蚀刻铜的蚀刻液，其中，过氧化氢的含量为1.5~4.5质量%、苹果酸的含量为1~15质量%、且过氧化氢和苹果酸的摩尔比在0.3~6的范围内。
[5]一种半导体装置的制造方法，其具备使用上述1~4中任一项所述的选择性蚀刻铜的蚀刻液的蚀刻工序。
[6]根据上述5所述的半导体装置的制造方法，其中，半导体装置具有凸块电极。
[7]根据上述5或6所述的半导体装置的制造方法，其中，具备在具有电极的半导体基板的该电极上形成布线的再布线形成工序。
[8]根据上述5~7中任一项所述的半导体装置的制造方法，其中，半导体装置具有使用铜形成的布线。
发明的效果
根据本发明，能够提供在使用了具有电极的半导体基板的半导体装置的制造工序中使用的、能选择性蚀刻铜而不蚀刻镍的蚀刻液及使用其的半导体装置的制造方法。
附图说明
图1是用于说明本发明的具有凸块电极的半导体装置的制造方法A的该半导体装置的每个工序的剖面示意图（图A（a）~（h））。
图2是用于说明本发明的具有凸块电极的半导体装置的制造方法A的该半导体装置的每个工序的剖面示意图（图A（i）~（p））。
图3是用于说明本发明的具有凸块电极的半导体装置的制造方法B的该半导体装置的每个工序的剖面示意图（图B（a）~（g））。
图4是用于说明本发明的具有凸块电极的半导体装置的制造方法B的该半导体装置的每个工序的剖面示意图（图B（h）~（m））。
图5是用于说明本发明的具有凸块电极的半导体装置的制造方法C的该半导体装置的每个工序的剖面示意图（图C（a）~（e））。
图6是用于说明本发明的具有凸块电极的半导体装置的制造方法C的该半导体装置的每个工序的剖面示意图（图C（f）~（k））。
图7是用于说明本发明的具有凸块电极的半导体装置的制造方法D的该半导体装置的每个工序的剖面示意图（图D（a）~（g））。
图8是用于说明本发明的具有凸块电极的半导体装置的制造方法D的该半导体装置的每个工序的剖面示意图（图D（h）~（l））。
附图标记说明
101，201，301，401：硅基板
102，202，302，402：电极
103，203，303，403：绝缘膜
104，204，304，404：开口部
105，205，305，405：钛层
106，206，306，406：铜层
107：光致抗蚀层（I）
108，208，308，408：开口部
109，209，409：铜层
110：光致抗蚀层（II）
111，211：开口部
112，210，309，410：镍层
113，310，411：金层
114，212：绝缘膜
116：铜层的残渣
117，311，412：凹部
207，307，407：光致抗蚀层
213：凸块电极
214：肩部脱落
具体实施方式
[蚀刻液]
本发明的蚀刻液是如下的液体：在使用了具有电极的半导体基板的半导体装置的制造工序中的蚀刻工序中使用，含有过氧化氢和作为有机酸成分的属于特定的羟基酸的柠檬酸或苹果酸，具有特定的组成。
本发明的蚀刻液含有作为有机酸成分的柠檬酸时，需要使过氧化氢的含量为0.75~12质量%、柠檬酸的含量为1~20质量%、且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。蚀刻液中的各成分的含量在上述范围时，过氧化氢的管理容易，过氧化氢的浓度稳定，且能够得到适当的蚀刻速度和良好的蚀刻性能，能够选择性蚀刻铜而不蚀刻镍。从同样的观点出发，优选过氧化氢的含量为1~9质量%、柠檬酸的含量为2~20质量%、且过氧化氢和柠檬酸的摩尔比在0.2~6的范围内，更优选过氧化氢的含量为1.5~7质量%、柠檬酸的含量为2~15质量%、且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。
本发明的蚀刻液含有作为有机酸成分的苹果酸时，需要使过氧化氢的含量为0.75~12质量%、苹果酸的含量为1.5~25质量%、且过氧化氢和苹果酸的摩尔比在0.2~6的范围内。蚀刻液中的各成分的含量在上述范围时，过氧化氢的管理容易，过氧化氢的浓度稳定，且能够得到适当的蚀刻速度和良好的蚀刻性能，能够选择性蚀刻铜而不蚀刻镍。从同样的观点出发，优选过氧化氢的含量为1~9质量%、苹果酸的含量为2~20质量%、且过氧化氢和苹果酸的摩尔比在0.2~6的范围内，更优选过氧化氢的含量为1.5~4.5质量%、苹果酸的含量为1~15质量%、且过氧化氢和苹果酸的摩尔比在0.3~6的范围内。
本发明的蚀刻液中，作为过氧化氢及有机酸成分以外的成分，优选包含水。作为水，优选通过蒸馏、离子交换处理、过滤处理、各种吸附处理等去除了金属离子、有机杂质、颗粒等的水，特别优选纯水、超纯水。
本发明的蚀刻液具有选择性蚀刻铜而不蚀刻镍的特征。因此，本发明的蚀刻液适宜在半导体装置制造工序中的蚀刻工序中使用，特别是在使用了镍和铜、需要选择性蚀刻铜而不蚀刻镍的半导体装置制造工序中的蚀刻工序中使用。
[半导体装置的制造方法]
优选的是，本发明的半导体装置的制造方法具有使用本发明的蚀刻液的蚀刻工序，该半导体装置具有凸块电极。另外，从有效发挥能选择性蚀刻铜而不蚀刻镍的本发明的蚀刻液的特征的观点来看，优选该蚀刻工序的特征在于，为由镍形成的部件和由铜形成的部件能同时接触蚀刻液的状态、且蚀刻该由铜形成的部件。以下更具体地说明本发明的制造方法。
《半导体装置的制造方法A》
本发明的半导体装置的制造方法的第一实施方式（以下称为制造方法A。）依次具有：晶种层形成工序A1、光致抗蚀层（I）形成工序A2、再布线形成工序A3、光致抗蚀层（II）形成工序A4、凸块电极形成工序A5、使用本发明的蚀刻液的蚀刻工序A6。使用图A（a）~（p）详细地说明本发明的制造方法A。
（工序A1）
工序A1是在设置有电极的半导体基板上设置具有该电极露出的开口部的绝缘膜、进而在该开口部及该绝缘膜上形成晶种层的晶种层形成工序。这里，设置有电极的半导体基板如图A（a）所示，例如在硅基板101的表面形成通过周知的制造方法制造的包含半导体元件的电路，在形成有该电路的面形成被称为焊盘的例如由铝等导电性材料形成的电极102。作为导电性材料，除铝以外，还可以优选列举出添加有钛、铜的铝合金、铜或铜合金、金等。
在该设置有电极102的半导体基板101上（形成有该电极的面）形成由氧化硅等形成的绝缘膜103，在该绝缘膜103上形成与电极102对应的开口部104使得电极102露出。
然后，如图A（b）及（c）所示，在开口部104及绝缘膜103上，通过通常的溅射形成晶种层。作为用于形成晶种层的金属，可优选列举出钛、铜等，可以如图A（b）及（c）所示地设置多层由这些金属形成的层、钛层105、铜层106等层。另外，从与电极102的密合性、半导体装置的制作管理的观点考虑，优选在基板上设置钛层105。
（工序A2）
工序A2是光致抗蚀层（I）形成工序，其使包含前述晶种层的设置在电极上的部位及用于形成凸块电极的部位的区域开口，形成具有使该晶种层露出的开口部108的光致抗蚀层（I）107。首先，如图A（d）所示，在铜层106上形式光致抗蚀层（I）107。然后，将该光致抗蚀层曝光、显影，形成如图A（e）所示的具有开口部108的光致抗蚀层（I）107，所述开口部108用于形成再布线，所述再布线将包含晶种层的设置在电极102上的部位和用于形成后述的凸块电极的部位的区域连接。
（工序A3）
工序A3是在前述开口部108设置布线进行再布线的再布线形成工序。通过该再布线形成工序，进行在具有电极102的半导体基板101的该电极102上形成布线的再布线形成。布线使用铜、镍等材料，优选如图A（f）所示地至少具有由铜形成的铜层109。另外，布线通常通过电镀处理铜、镍来设置。
（工序A4）
工序A4是光致抗蚀层（II）形成工序，其中，如图A（g）及（h）所示，将在工序A3中形成的光致抗蚀层（I）107去除，以被覆晶种层及布线的方式形成光致抗蚀层（II）110，进而进行曝光、显影，由此在光致抗蚀层（II）110形成用于形成凸块电极的开口部111。该光致抗蚀层（II）110利用常规方法设置即可。
（工序A5）
工序A5是凸块电极形成工序，其中，如图A（i）及（j）所示，在前述光致抗蚀层（II）110的用于形成凸块电极的部位设置开口部111使得再布线的铜层109露出，在该开口部111形成具有至少一层由镍形成的镍层112的凸块电极。
凸块电极可以使用锡、铅、它们的合金（锡-铅合金）以及金、钯、镍、铜等通过电镀来形成，可以由一层或多层形成。例如，可以如图A（j）所示在设置镍层112之后，设置金层113来形成凸块电极。本发明的制造方法中，用于形成凸块电极的至少一层为由镍形成的镍层112时，可以有效地发挥本发明的蚀刻液具有的能选择性蚀刻铜而不蚀刻镍的性能。
（工序A6）
工序A6是蚀刻工序，其中，如图A（k）所示地将前述光致抗蚀层（II）110去除之后，进而如图A（l）及（m）所示地蚀刻钛层105、铜层106等晶种层中未被铜层109这样的布线覆盖的露出部分。该蚀刻工序中，需要使用本发明的蚀刻液。通过使用本发明的蚀刻液，蚀刻液中的过氧化氢的管理容易，且能得到适当的蚀刻速度和良好的蚀刻性能，能选择性蚀刻铜而不蚀刻镍。
使蚀刻液接触蚀刻对象物的方法没有特别限定，例如可以采用：通过滴下、喷射等形式使蚀刻液与对象物接触的方法；使对象物浸渍在蚀刻液中的方法等。本发明中，优选采用向对象物喷射蚀刻液使它们接触的方法。
作为蚀刻液的使用温度，优选为50℃以下的温度，更优选为20~50℃，进一步优选为20~40℃，特别优选为25~35℃。蚀刻液的温度为50℃以上时，蚀刻速度增大，但液体的稳定性变差，难以使蚀刻条件保持固定。通过使蚀刻液的温度为50℃以下，可以使蚀刻液的组成变化较小，得到稳定的蚀刻速度。另外，为20℃以上时，蚀刻速度不会变得过慢，生产效率不会显著降低。
如图A（l）所示，在工序A6的蚀刻工序中蚀刻铜层106时，镍层112的侧面暴露在蚀刻液中。这样的情况下，如果使用本发明的蚀刻液，则不会出现如图A（p）所示的镍层112被蚀刻而形成凹部117的情况，能够选择性地仅蚀刻铜层106。另外，本发明的蚀刻液具有良好的蚀刻性能，因此，也不会产生图A（o）所示的铜层的残渣116。
本发明的制造方法A中，如图A（n）所示，进而可以在形成有凸块电极的区域以外的部分形成绝缘膜114。该绝缘膜114的形成优选使用环氧树脂、聚酰亚胺树脂等绝缘性有机材料等。
《半导体装置的制造方法B》
本发明的半导体装置的制造方法的第二实施方式（以下称为制造方法B。）依次具有：晶种层形成工序B1、光致抗蚀层形成工序B2、再布线形成工序B3、使用本发明的蚀刻液的蚀刻工序B4、绝缘膜形成工序B5、及凸块电极形成工序B6。使用图B（a）~（m）详细地说明本发明的制造方法B。
（工序B1）
工序B1是晶种层形成工序，其在设置有电极202的半导体基板201上设置具有该电极202露出的开口部204的绝缘膜203，进而在该开口部204及该绝缘膜203上形成晶种层，如图B（a）~（c）所示，与前述工序A1相同。
（工序B2）
工序B2是光致抗蚀层形成工序，其使在工序B1中设置的由钛层205及铜层206形成的晶种层的包含设置在电极202上的部位及用于形成凸块电极的部位的区域开口，形成具有使该晶种层露出的开口部208的光致抗蚀层207。工序B2如图B（d）及（e）所示，与前述工序A2相同。
（工序B3）
工序B3是在前述开口部208设置布线进行再布线的再布线形成工序。布线使用铜、镍等材料。例如，可以如图B（f）及（g）所示，依次层叠铜层209和镍层210，形成再布线。另外，布线通常通过电镀处理铜、镍来设置。
（工序B4）
工序B4是蚀刻工序，其中，如图B（h）所示将前述光致抗蚀层207去除之后，进而如图B（i）及（j）所示，蚀刻钛层205、铜层206等晶种层中未被铜层209及镍层210这样的布线覆盖的露出部分。该蚀刻工序中，需要使用本发明的蚀刻液。通过使用本发明的蚀刻液，蚀刻液中的过氧化氢的管理容易，且能够得到适当的蚀刻速度和良好的蚀刻性能，能够选择性蚀刻铜而不蚀刻镍。工序B4中的蚀刻的各条件与工序A6相同。
如图B（i）所示，在工序B4的蚀刻工序中将铜层206蚀刻时，镍层210暴露在蚀刻液中。这种情况下，如果使用本发明的蚀刻液，则不会出现图B（m）所示的镍层210被蚀刻而形成肩部脱落214的情况，能够选择性地仅蚀刻铜层206。另外，本发明的蚀刻液具有良好的蚀刻性能，因此也不会产生铜层的残渣。
（工序B5）
工序B5是如图B（k）所示地形成在用于设置凸块电极的区域具有开口部211的绝缘膜212的绝缘膜形成工序。
绝缘膜212的形成中，优选使用环氧、聚酰亚胺等有机绝缘材料。绝缘膜212如下来形成：通过旋涂等涂覆该有机绝缘材料，并设置使再布线部分（图B的情况为镍层210）露出的开口部211。根据绝缘膜212中使用的有机绝缘材料的不同，开口部的形成方法不同，例如涂覆有机绝缘材料后，涂布光致抗蚀剂，将该光致抗蚀剂曝光、显影，然后蚀刻绝缘膜212从而设置开口部211，或者，在该有机绝缘材料为感光性的材料时，也可以在涂覆该有机绝缘材料之后，直接曝光、显影，形成具有开口部211的绝缘膜212。
（工序B6）
工序B6是在开口部211形成凸块电极213的凸块电极形成工序。凸块电极213可以安装焊锡球而设置。
《半导体装置的制造方法C》
本发明的半导体装置的制造方法的第三实施方式（以下称为制造方法C。）依次具有：晶种层形成工序C1、光致抗蚀层形成工序C2、凸块电极形成工序C3、及使用本发明的蚀刻液的蚀刻工序C4。使用图C（a）~（k）详细地说明本发明的制造方法C。
（工序C1）
工序C1是晶种层形成工序，其在设置有电极302的半导体基板301上设置具有该电极302露出的开口部304的绝缘膜303，进而在该开口部304及该绝缘膜303上形成晶种层，如图C（a）~（c）所示，与前述工序A1或者B1相同。
（工序C2）
工序C2是光致抗蚀层形成工序，其使工序C1中设置的由钛层305及铜层306形成的晶种层的包含设置在电极302上的部位的区域开口，形成具有使该晶种层露出的开口部308的光致抗蚀层307。工序C2如图C（d）及（e）所示，与前述工序A2或者B2相同。
（工序C3）
工序C3是在开口部308形成具有至少一层由镍形成的镍层309的凸块电极的凸块电极形成工序。工序C3除开口部111的形成以外与工序A5相同，可以如图C（f）及（g）所示在设置镍层309之后设置金层310而形成凸块电极。
（工序C4）
工序C4是蚀刻工序，其中，如图C（h）所示地将前述光致抗蚀层307去除之后，进而如图C（i）及（j）所示地蚀刻钛层305、铜层306等晶种层中未被镍层309、金层310这样的凸块电极覆盖的露出部分。该蚀刻工序中，需要使用本发明的蚀刻液。通过使用本发明的蚀刻液，蚀刻液中的过氧化氢的管理容易，且能够得到适当的蚀刻速度和良好的蚀刻性能，能够选择性蚀刻铜而不蚀刻镍。工序C4中的蚀刻的各条件与工序A6相同。
如图C（i）所示，在工序C4的蚀刻工序中蚀刻铜层306时，镍层309暴露在蚀刻液中。这种情况下，如果使用本发明的蚀刻液，则不会出现图C（k）所示的镍层309被蚀刻而形成凹部311的情况，能够选择性地仅蚀刻铜层306。另外，本发明的蚀刻液具有良好的蚀刻性能，因此也不会产生铜层的残渣。
《半导体装置的制造方法D》
本发明的半导体装置的制造方法的第四实施方式（以下称为制造方法D。）依次具有：晶种层形成工序D1、光致抗蚀层形成工序D2、凸块电极形成工序D3、及使用本发明的蚀刻液的蚀刻工序D4。本发明的制造方法D的各工序以图D（a）~（l）表示。
如图D（a）~（l）所示，制造方法D除在凸块电极形成工序D3中设为由铜层409、镍层410及金层411这三层形成的凸块电极以外，与制造方法C相同。
如图D（j）所示，在工序D4的蚀刻工序中蚀刻铜层406时，镍层410暴露在蚀刻液中。这种情况下，如果使用本发明的蚀刻液，则不会出现图D（l）所示的镍层410被蚀刻而形成凹部412的情况，能够选择性地仅蚀刻铜层406。另外，本发明的蚀刻液具有良好的蚀刻性能，因此也不会产生铜层的残渣。
本发明的制造方法中，利用制造方法A及B，能够得到进行了在具有电极的半导体基板的该电极上形成布线的再布线的具有凸块电极的半导体装置。根据这些制造方法，能够使用电极间距为150μm以下、100μm以下、进而50μm以下的窄间距的半导体基板。另外，能够得到凸块电极的间距为500μm以下、250μm以下、进而200μm以下的窄间距的半导体装置。因此，利用本发明的制造方法得到的半导体装置能够充分对应近年来的小型化、高集成化及多功能化。
实施例
以下，通过实施例对本发明进行更详细的说明，但本发明并不受这些例子的任何限定。
《评价方法》
评价项目1.铜层（布线）的蚀刻速率的计算
将通过溅射形成了铜膜（铜膜的厚度：
Figure BDA00001773486800141
）的硅基板在30℃下在各实施例及比较例的蚀刻液中浸渍2分钟，使用荧光X射线分析装置（“SEA2110L）“，エスエスアイナノテクノロジー社制造）测定浸渍前后的膜厚变化，计算蚀刻速率（μm/分钟）。
评价项目2.镍的蚀刻速率的计算
将在钢材上通过电镀形成了镍膜（镍膜的厚度：5μm）的基板在30℃下在各实施例及比较例的蚀刻液中浸渍1小时，测定浸渍前后的重量，计算蚀刻速率（
Figure BDA00001773486800151
/分钟）。
评价项目3.蚀刻液（过氧化氢）的稳定性的评价
求出将各实施例及比较例的蚀刻液在50℃的条件下放置1周时各蚀刻液中的过氧化氢的分解率，按照以下的基准进行评价。分解率不足10%时，判断稳定性优异，为10%以上且不足20%时，判断在经济性方面不充分，在安全方面的液体管理中需要注意，但为实用上没有问题的程度，为20%以上时，判断为无法使用的程度。
○：分解率不足10%
△：分解率为10%以上且不足20%
×：分解率为20%以上
评价项目4.使用半导体基板的蚀刻的评价
使用各实施例及比较例的蚀刻液，按照制造方法A~D的顺序制造半导体装置。此时，蚀刻温度为30℃，蚀刻时间设为用作为该半导体装置的晶种层的通过溅射设置的铜膜（膜厚：
Figure BDA00001773486800153
）除以在上述评价项目1中得到的蚀刻速率而算出的时间的2倍。
对所得半导体装置，分别按照下述基准评价通过电镀设置的镍层的凹部（制造方法A、C及D的情况）、或肩部脱落（制造方法B的情况）的状态、及作为晶种层设置的铜层的蚀刻后的残留状态。
（关于镍层的凹部或肩部脱落的状态）
○：完全没有发现镍层的凹部或肩部脱落
△：存在少许镍层的凹部或肩部脱落，但实用上没有问题
×：镍层的凹部或肩部脱落明显，无法使用
（铜层的残留状态）
○：蚀刻后，完全没有发现铜层的残留
△：蚀刻后，发现少许铜层的残留，实用上产生阻碍
×：蚀刻后，铜层的残留显著，无法使用
《处理液的制备》
按照表1及2所示的配混组成（质量%），制备各实施例及比较例中使用的蚀刻液。
实施例A1~A51及比较例A1~A49（利用制造方法A的半导体装置的制造）
按照制造方法A（图A（a）~（n））的顺序，制作具有电极及凸块电极的半导体装置。这里，在图A（k）~（m）所示的蚀刻工序中，使用各实施例及比较例的蚀刻液，依次进行光致抗蚀层110、铜层106及钛层105的蚀刻。
另外，钛层105及铜层106均通过溅射来设置，其层厚均为
Figure BDA00001773486800161
再布线的铜层109及用于形成凸块电极的镍层112及金层113均通过电镀设置，其层厚分别为3μm、2μm及5μm。对于各实施例及比较例中得到的半导体装置，将按照上述评价项目4进行评价而得到的结果示于表1及表2。另外，对于各实施例及比较例中使用的蚀刻液，将按照上述评价项目1~3进行评价而得到的结果示于表1及表2。
实施例B1~B51及比较例B1~B49
按照制造方法B（图B（a）~（l））的顺序，制作具有电极及凸块电极的半导体装置。钛层205及铜层106均通过溅射来设置，其层厚均为
Figure BDA00001773486800162
在再布线工序中设置的铜层209及镍层210均通过电镀来设置，其层厚分别为3μm及2μm。
图B（h）~（j）所示的蚀刻工序中，使用蚀刻液依次进行光致抗蚀层207、铜层206及钛层205的蚀刻。这里，实施例B1~B51及比较例B1~B49中使用的蚀刻液分别与实施例A1~A51及比较例A1~A49中使用的蚀刻液相同，评价项目1~3的评价也相同。
对于各实施例及比较例中得到的半导体装置，按照上述评价项目4进行评价，结果，实施例B1~B 51及比较例B1~B49分别与使用相同的蚀刻液的实施例A1~A51及比较例A1~A49相同。将这些结果示于表1及表2。
实施例C1~C51及比较例C1~C49
按照制造方法C（图C（a）~（j））的顺序，制作具有电极及凸块电极的半导体装置。钛层305及铜层306均通过溅射来设置，其层厚均为
Figure BDA00001773486800171
作为凸块电极设置的镍层309、金层310均通过电镀来设置，其层厚分别为3μm及10μm。
在图C（h）~（j）所示的蚀刻工序中，使用蚀刻液依次进行光致抗蚀层307、铜层306及钛层305的蚀刻。这里，实施例C1~C51及比较例C1~C49中使用的蚀刻液分别与实施例A1~A51及比较例A1~A49中使用的蚀刻液相同，评价项目1~3的评价也相同。
对于各实施例及比较例中得到的半导体装置，按照上述评价项目4进行评价，结果，实施例C1~C51及比较例C1~C49分别与使用相同蚀刻液的实施例A1~A51及比较例A1~A49相同。将这些结果示于表1及表2。
实施例D1~D51及比较例D1~D49
按照制造方法D（图D（a）~（k））的顺序，制作具有电极及凸块电极的半导体装置。钛层405及铜层406均通过溅射来设置，其层厚均为
Figure BDA00001773486800172
作为凸块电极设置的铜层409、镍层410、金层411均通过电镀来设置，其层厚分别为10μm、3μm及5μm。
在图D（i）~（k）所示的蚀刻工序中，使用蚀刻液依次进行光致抗蚀层407、铜层406及钛层405的蚀刻。这里，实施例D1~D51及比较例D1~D49中使用的蚀刻液分别与实施例A1~A51及比较例A1~A49中使用的蚀刻液相同，评价项目1~3的评价也相同。
对于各实施例及比较例中得到的半导体装置，按照上述评价项目4进行评价，结果，实施例D1~D51及比较例D1~D49分别与使用相同蚀刻液的实施例A1~A51及比较例A1~A49相同。将这些结果示于表1及表2。
[表1]
表1
Figure BDA00001773486800181
[表2]
表2
Figure BDA00001773486800191
产业上的可利用性
本发明的蚀刻液可以在使用了具有电极的半导体基板的半导体装置的制造工序中使用。

Claims (8)

1.一种用于选择性蚀刻铜的蚀刻液,其在使用了具有电极的半导体基板的半导体装置的制造中使用，其含有过氧化氢和柠檬酸，过氧化氢的含量为0.75~12质量%，柠檬酸的含量为1~20质量%，且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。
2.一种用于选择性蚀刻铜的蚀刻液，其在使用了具有电极的半导体基板的半导体装置的制造中使用，其含有过氧化氢和苹果酸，过氧化氢的含量为0.75~12质量%，苹果酸的含量为1.5~25质量%，且过氧化氢和苹果酸的摩尔比在0.2~6的范围内。
3.根据权利要求1所述的用于选择性蚀刻铜的蚀刻液，其中，过氧化氢的含量为1.5~7质量%，柠檬酸的含量为2~15质量%，且过氧化氢和柠檬酸的摩尔比在0.3~5的范围内。
4.根据权利要求2所述的用于选择性蚀刻铜的蚀刻液，其中，过氧化氢的含量为1.5~4.5质量%，苹果酸的含量为1~15质量%，且过氧化氢和苹果酸的摩尔比在0.3~6的范围内。
5.一种半导体装置的制造方法，其具有使用权利要求1~4中任一项所述的用于选择性蚀刻铜的蚀刻液的蚀刻工序。
6.根据权利要求5所述的半导体装置的制造方法，其中，半导体装置具有凸块电极。
7.根据权利要求5或6所述的半导体装置的制造方法，其具备在具有电极的半导体基板的该电极上形成布线的再布线形成工序。
8.根据权利要求5~7中任一项所述的半导体装置的制造方法，其中，半导体装置具有使用铜形成的布线。
CN201080057354.XA 2009-12-15 2010-12-14 蚀刻液及使用其的半导体装置的制造方法 Active CN102687251B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009-284173 2009-12-15
JP2009284173 2009-12-15
PCT/JP2010/072506 WO2011074589A1 (ja) 2009-12-15 2010-12-14 エッチング液及びこれを用いた半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN102687251A true CN102687251A (zh) 2012-09-19
CN102687251B CN102687251B (zh) 2016-02-17

Family

ID=44167341

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080057354.XA Active CN102687251B (zh) 2009-12-15 2010-12-14 蚀刻液及使用其的半导体装置的制造方法

Country Status (6)

Country Link
US (1) US8900478B2 (zh)
EP (1) EP2515326B1 (zh)
JP (1) JP5794147B2 (zh)
CN (1) CN102687251B (zh)
TW (1) TWI515337B (zh)
WO (1) WO2011074589A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2862959A1 (en) 2013-10-21 2015-04-22 ATOTECH Deutschland GmbH Method of selectively treating copper in the presence of further metal
JP6251043B2 (ja) * 2014-01-08 2017-12-20 株式会社荏原製作所 エッチング液、エッチング方法、およびはんだバンプの製造方法
FR3018151A1 (fr) * 2014-07-04 2015-09-04 Commissariat Energie Atomique Procede de realisation d'un niveau d'interconnexion electrique
US20170323963A1 (en) * 2014-12-23 2017-11-09 Intel Corporation Thin channel region on wide subfin
US10332753B2 (en) * 2017-01-13 2019-06-25 International Business Machines Corporation Wet etching of samarium selenium for piezoelectric processing
DE102017110076A1 (de) * 2017-05-10 2018-11-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines strahlungsemittierenden Halbleiterbauelements und strahlungsemittierendes Halbleiterbauelement
TWI831869B (zh) 2018-11-20 2024-02-11 日商三菱瓦斯化學股份有限公司 用以選擇性蝕刻銅及銅合金之蝕刻液及使用此蝕刻液之半導體基板之製造方法
US11121101B2 (en) * 2020-01-30 2021-09-14 International Business Machines Corporation Flip chip packaging rework

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053075A (ja) * 1999-08-10 2001-02-23 Shinko Electric Ind Co Ltd 配線構造及び配線形成方法
JP2006120664A (ja) * 2004-10-19 2006-05-11 Nec Electronics Corp 半導体装置の製造方法
CN101392376A (zh) * 2007-09-19 2009-03-25 长瀬化成株式会社 蚀刻组合物

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3654485B2 (ja) 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6511901B1 (en) * 1999-11-05 2003-01-28 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
US20020048953A1 (en) * 2000-06-16 2002-04-25 Radha Nayak Chemical mixture for copper removal in electroplating systems
TW449813B (en) * 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
US8372757B2 (en) * 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
US7465408B1 (en) * 2003-12-03 2008-12-16 Advanced Micro Devices, Inc. Solutions for controlled, selective etching of copper
JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
JP4393343B2 (ja) * 2004-10-22 2010-01-06 株式会社東芝 半導体装置の製造方法
DE102005038414A1 (de) 2005-08-12 2007-02-15 Basf Aktiengesellschaft Stabilisierte Ätzlösungen zum Ätzen von Cu- und Cu/Ni-Schicht
US7541251B2 (en) * 2006-02-10 2009-06-02 California Micro Devices Wire bond and redistribution layer process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053075A (ja) * 1999-08-10 2001-02-23 Shinko Electric Ind Co Ltd 配線構造及び配線形成方法
JP2006120664A (ja) * 2004-10-19 2006-05-11 Nec Electronics Corp 半導体装置の製造方法
CN101392376A (zh) * 2007-09-19 2009-03-25 长瀬化成株式会社 蚀刻组合物

Also Published As

Publication number Publication date
JP5794147B2 (ja) 2015-10-14
US8900478B2 (en) 2014-12-02
JPWO2011074589A1 (ja) 2013-04-25
TW201127995A (en) 2011-08-16
CN102687251B (zh) 2016-02-17
EP2515326A1 (en) 2012-10-24
WO2011074589A1 (ja) 2011-06-23
EP2515326A4 (en) 2013-07-24
TWI515337B (zh) 2016-01-01
US20120261608A1 (en) 2012-10-18
EP2515326B1 (en) 2018-09-26

Similar Documents

Publication Publication Date Title
CN102687251A (zh) 蚀刻液及使用其的半导体装置的制造方法
CN102696097B (zh) 蚀刻液及使用其的半导体装置的制造方法
JP3065508B2 (ja) Ｃ４製造のためのＴｉＷの選択的エッチング
US6232212B1 (en) Flip chip bump bonding
US5904859A (en) Flip chip metallization
US3761309A (en) Ctor components into housings method of producing soft solderable contacts for installing semicondu
CN102569171A (zh) 改善冠状缺陷的线路结构及其制作方法
US7473459B2 (en) Method of manufacturing a film printed circuit board
JP2643097B2 (ja) 金属コンタクト形成方法
KR20110093621A (ko) Ｃｏｆ 기판의 제조방법
CN108770219B (zh) 无引线板面镀金与osp表面处理的pcb板制作方法
JP2001118872A (ja) バンプの形成方法
KR20060107349A (ko) 구리 배선 또는 범프가 형성된 기판의 제조 방법
JPS6112047A (ja) 半導体装置の製造方法
JP3147698B2 (ja) バンプ電極及びその製造方法
JP2003152007A (ja) バンプ形成方法および半導体装置の実装構造体
US8183692B2 (en) Barrier layer for fine-pitch mask-based substrate bumping
CN1630038A (zh) 蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法
JPH04217323A (ja) 半導体装置用バンプ電極の製造方法
JP2002076046A (ja) 半導体装置の製造方法
JP3703864B2 (ja) プリント配線板の製造方法
JP5788342B2 (ja) 半導体キャリア用フィルムおよびそれを用いた半導体装置、液晶モジュール
JP4850887B2 (ja) 半導体装置の使用方法
JP3471723B2 (ja) ベアチップ実装対応多層配線とその作製方法
JP2004193211A (ja) 電子部品およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant