JPWO2002073697A1 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

By forming the WNX film 24 constituting the barrier layer of the gate electrode 7A having a polymetal structure in an atmosphere containing a high concentration of nitrogen gas, N (N) Nitrogen).

Description

Technical field
The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a MISFET (Metal Insulator Semiconductor Effect Transistor) having a polymetal (Polymetal) structure in which a gate electrode is formed by a stacked film of polycrystalline silicon and a high melting point metal. The present invention relates to a technology that is effective when applied to the manufacture of a semiconductor integrated circuit device.
Background art
With respect to polymetal gates or metal gates in general, JP-A-60-89943, JP-A-61-150236, JP-A-60-72229, JP-A-59-10271, and JP-A-56-50 JP-107552, JP-A-61-127123, JP-A-61-127124, JP-A-60-123060, JP-A-61-152076, JP-A-61-267365, JP-A-1-94657, JP-A-8-264531, JP-A-3-119763, JP-A-7-94716, U.S. Pat. Nos. USP4505028, USP5719410, USP53887540, IEEE Transaction Electron Devices, Vol. 43, NO. 11, November 1996, Akasaka et al, p. 1864-1869, Elsevier, Applied Surface Science 117/118 (1997) 312-316, Nakajima et al, Nakajima et al, Advanced metalization confession, Japan Society. (1995).
US Pat. No. 4,282,270 relates to oxynitriding. Further, regarding the treatment of hydrogen exhaust gas, there are US Pat. No. 5,202,096, US Pat. No. 5,083,314, JP-A-8-83772 and JP-A-9-75651.
Further, regarding the problem of moisture and oxidation, there are JP-A-7-321102, JP-A-60-107840, US Pat. No. 5,693,578 and the like.
Further, regarding water synthesis using a catalyst, JP-A-6-333918, JP-A-6-115903, JP-A-5-152282, JP-A-6-1638671, and JP-A-5-141871. JP-A-5-144804, JP-A-6-120206, Nakamura et al, Proceedings of the 45.^th  Symposium on Semiconductors and Integrated circuit Technology, Tokyo Dec. 1-2, 1993, the Electronic materials committee, P.S. 128-133 and the like.
Disclosure of the invention
In a CMOS LSI in which a circuit is formed by a fine MOSFET having a gate length of 0.18 μm or less or a DRAM using a similar gate layer for a gate electrode and a wiring, gate delay and signal delay in the wiring are reduced to ensure high-speed operation. In addition, it is considered that a gate processing process using a low-resistance conductive material including a metal layer is adopted.
A promising low-resistance gate electrode material of this type is a so-called polymetal in which a refractory metal film is laminated on a polycrystalline silicon film. Since polymetal has a low sheet resistance of about 2Ω / □, it can be used not only as a gate electrode material but also as a wiring material. As the high melting point metal, W (tungsten), Mo (molybdenum), or the like, which exhibits good low resistance even in a low-temperature process of 800 ° C. or less and has high electromigration resistance, is used. In addition, if these refractory metal films are directly laminated on the polycrystalline silicon film, the adhesive strength between them is reduced, or a high-resistance silicide layer is formed at the interface between the two by a high-temperature heat treatment process. The polymetal gate is formed between the polycrystalline silicon film and the refractory metal film by WN._X(Tungsten nitride) or the like, and has a three-layer structure in which a barrier layer made of a metal nitride film such as tungsten nitride is interposed.
However, between the polycrystalline silicon film and the refractory metal film, WN_XWhen the gate electrode is formed in a three-layer structure in which a barrier layer made of a metal nitride film such as (tungsten nitride) is interposed, WN is used in a heat treatment process after processing the gate electrode._XN (nitrogen) is released from the film, and WN_XThe present inventors have found that the loss of the function of the film as a barrier layer results in an increase in the contact resistance at the interface between the refractory metal film and the polycrystalline silicon film.
An object of the present invention is to provide a gate electrode having a three-layer structure in which a barrier layer made of a metal nitride film is interposed between a polycrystalline silicon film and a refractory metal film. It is an object of the present invention to provide a technique for preventing an increase in contact resistance at the interface with the interface.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
The following is a brief description of an outline of typical inventions disclosed in the present application.
A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a first silicon-based film having silicon as one of the main components on the gate insulating film;
(C) doping impurities into the first silicon base film by ion implantation;
(D) after the step (c), forming a non-doped second silicon base film containing silicon as one of the main components on the first silicon base film;
(E) forming a tungsten nitride film by sputtering on the second silicon base film so that the nitrogen element composition at the time of device completion is 7% or more;
(F) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film;
A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming, on the gate insulating film, a first silicon base film doped with impurities, using silicon as one of main components;
(C) forming a non-doped second silicon-based film having silicon as one of the main components on the first silicon-based film;
(D) forming a tungsten nitride film by sputtering on the second silicon base film such that the nitrogen element composition at the time of device completion is 7% or more;
(E) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film;
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.
Furthermore, in the following embodiments, when it is necessary for convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not irrelevant to each other, unless otherwise specified. There is a relationship of some or all of the other modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including numbers, numerical values, amounts, ranges, etc.), unless otherwise specified, and unless the number is clearly limited to a specific number in principle, The number is not limited to the specific number, and may be more than or less than the specific number. Furthermore, in the following embodiments, it is needless to say that the components (including the element steps and the like) are not necessarily essential, unless explicitly stated or considered to be indispensable in principle. No.
Similarly, in the following embodiments, when referring to the shape of components and the like, the positional relationship, etc., the shape and the like of the components and the like are substantially excluded, unless otherwise specified and when it is considered that it is not clearly apparent in principle. And those similar to or similar to This is the same for the above numerical values and ranges.
In addition, a semiconductor integrated circuit wafer or a semiconductor wafer refers to a silicon single crystal substrate (generally a substantially circular shape), a sapphire substrate, a glass substrate, or other insulating, anti-insulating or semiconductor substrates used for manufacturing a semiconductor integrated circuit, or a composite thereof. Refers to a substrate. In addition, the term "semiconductor integrated circuit device" (or "electronic device", "electronic circuit device", etc.) refers not only to those made on a single-crystal silicon substrate, but also to the extent that it is not explicitly stated otherwise. The above-mentioned various substrates, or those formed on other substrates such as an SOI (Silicon On Insulator) substrate, a TFT (Thin Film Transistor) liquid crystal manufacturing substrate, an STN (Super Twisted Nematic) liquid crystal manufacturing substrate, and the like. .
When referring to materials, gas compositions, and the like, unless otherwise indicated, in addition to pure materials, materials that include the material as main constituents, etc., shall be indicated, and the addition of other elements shall be allowed.
For example, regarding the gas composition, in addition to the main reaction gas and the processing gas, addition of an additional gas, a diluting gas, and an auxiliary gas that acts as a secondary gas is allowed.
Further, when referring to a silicon oxide film, various silicon oxide-based films generally containing various additives and auxiliary components, that is, a PSG (Phospho Silicate Glass) film, a BPSG (Boro), unless otherwise specified. -A single film or a composite film such as a Phospho Silicate Glass (TEOS) film, a TEOS (Tetra-Ethoxy Silane) oxide film, a silicon oxynitride film, or the like is included.
Further, when referring to silicon nitride, silicon nitride or silicon nitride,₃N₄Not only that, but an insulating film having a similar composition of silicon nitride is included.
The gate oxide film includes a silicon thermal oxide film, a silicon oxynitride film, other thermal oxide films, a deposited film, and a coating film. Including insulating nitride such as silicon nitride or a composite film thereof.
In addition, when referring to the material of the conductive region on the substrate surface or the conductive region of the deposited film as “silicon” or “silicon base”, unless otherwise specified, relatively pure silicon members are used, and impurities or silicon are added to silicon. A conductive member containing silicon as a main component (for example, a SiGe alloy containing 50% or more of Ge in a silicon base alloy, etc .; for example, a gate polysilicon portion or a channel region) is also included. To SiGe). They also allow high resistance at the beginning of formation, as long as they do not technically contradict.
Some of the deposited films are amorphous at the beginning of the deposition, but may be polycrystalline immediately after the subsequent heat treatment. However, except for when it is deemed particularly necessary, in order to avoid contradictions in expression, from the beginning, It may be displayed in a later form. For example, polycrystalline silicon (polysilicon) is in an amorphous state at the beginning of deposition, and is changed to polycrystalline silicon by a subsequent heat treatment. However, needless to say, polycrystalline silicon can be used from the beginning. An amorphous state at the beginning of deposition has advantages such as prevention of channeling in ion implantation, avoidance of difficulty in workability depending on the shape of agglomerates at the time of dry etching, low sheet resistance after heat treatment, and the like.
Further, other techniques related to the implementation of the present invention are disclosed in detail in the following applications involving the inventor of the present application. That is, Patent Application No. 2000-118491, JP-A-09-172011, JP-A-10-335652, JP-A-10-340909, JP-A-11-330468, JP-A-10-349285, U.S.A. Patent No. 6,066,508, International Publication WO98 / 39802, International Publication WO97 / 28085, and the like.
(Embodiment 1)
FIG. 1 is an overall plan view of a semiconductor chip 1A on which a DRAM (Dynamic Random Access Memory) of the present embodiment is formed. On the main surface of the rectangular semiconductor chip 1A, a DRAM having a storage capacity of, for example, 256 Mbit (megabit) is formed. This DRAM is mainly composed of a storage section composed of a plurality of memory arrays (MARY) and a peripheral circuit section PC arranged around the storage section. At the center of the semiconductor chip 1A, a plurality of bonding pads BP to which connection terminals such as bonding wires are connected are arranged in a row.
FIG. 2 is a plan view of a semiconductor substrate showing a part of a memory array (MARY) of the DRAM, and FIG. 3 is a sectional view of a main part of the semiconductor substrate showing the DRAM. 3 is a cross-sectional view taken along line AA in FIG. 2, a central region is a cross-sectional view taken along line BB in FIG. 2, and a right region is a peripheral circuit portion (PC). It is sectional drawing which shows a part.
For example, an element isolation groove 2, a p-type well 3, and an n-type well are provided on a main surface of a semiconductor substrate (hereinafter, also referred to as a substrate, or sometimes simply a wafer) 1 made of p-type single crystal silicon. 4 are formed. The p-type well of the memory array includes a plurality of memory cells each including an n-channel type memory cell selecting MISFET (Metal Insulator Field Effect Transistor) Qt and an information storage capacitor C formed thereon. Is formed.
The memory cell selection MISFET Qt mainly includes a gate insulating film 6, a gate electrode 7A constituting a word line WL in a region other than the active region L, and a pair of n-type semiconductor regions (source, drain) 9, 9. The gate electrode 7A (word line WL) is formed, for example, on the top of an n-type polycrystalline silicon film doped with P (phosphorus) by WN._XIt is formed of a conductive film having a so-called polymetal structure in which a (tungsten nitride) film and a W film are stacked.
The peripheral circuit portion PC of the DRAM is constituted by a so-called complementary MIS circuit in which a plurality of n-channel MISFETs Qn and a plurality of p-channel MISFETs Qp are combined. The n-channel MISFET Qn is formed in the p-type well 3 and mainly includes a gate insulating film 6, a gate electrode 7B and a pair of n⁺It is constituted by the type semiconductor regions (source, drain) 12, 12. The p-channel type MISFET Qp is formed in the n-type well 4, and mainly includes the gate insulating film 6, the gate electrode 7C and the pair of p-type MISFETs Qp.⁺It is constituted by the type semiconductor regions (source, drain) 13, 13. The gate electrodes 7B and 7C are formed of a conductive film having the same polymetal structure as the gate electrode 7A (word line WL) of the memory cell selecting MISFET Qt. Sidewall spacers 11s made of a silicon nitride film are formed on the side walls of the gate electrodes 7B and 7C.
Above the memory cell selection MISFET Qt, the n-channel MISFET Qn, and the p-channel MISFET Qp, a silicon nitride film 11 and an interlayer insulating film 15 that cover the top and side walls of the gate electrode 7A (word line WL) are formed. The interlayer insulating film 15 is composed of, for example, a spin-on-glass (Spin On Glass) film (a silicon oxide-based insulating film formed by a coating method) and a two-layer silicon oxide film formed thereon.
A contact hole 16 formed by opening an interlayer insulating film 15 and a silicon nitride film 11 thereunder is formed above a pair of n-type semiconductor regions 9 and 9 constituting the source and the drain of the memory cell selecting MISFET Qt. 17 are formed. Plugs 18 made of, for example, an n-type polycrystalline silicon film doped with P (phosphorus) are buried in these contact holes 16 and 17.
A silicon oxide film 19 is formed above the interlayer insulating film 15, and a through hole 20 is formed in the silicon oxide film 19 above one of the pair of contact holes 16 and 17 (contact hole 16). I have. The through-hole 20 is arranged above the element isolation groove 2 deviating from the active region L, and is constituted by a two-layer conductive film in which a W film is laminated on a TiN (titanium nitride) film, for example. Plug 23 is embedded. The plug 23 buried in the through hole 20 is one of the source and the drain of the memory cell selecting MISFET Qt (shared by the two memory cell selecting MISFETs Qt) via the plug 18 buried in the contact hole 16 thereunder. It is electrically connected to the n-type semiconductor region 9).
Contact holes 21 and 22 are formed in the silicon oxide film 19 in the peripheral circuit portion and the interlayer insulating film 15 thereunder. The contact hole 21 is formed by a pair of n forming the source and drain of the n-channel type MISFET Qn.⁺The contact holes 22 are formed on the upper portions of the p-type MISFETs Qp.⁺Formed above the type semiconductor regions (source, drain) 13, 13. Plugs 23 made of the same conductive material as the plugs 23 embedded in the through holes 20 of the memory array are embedded in these contact holes 21 and 22.
Above the silicon oxide film 19 of the memory array, a plurality of bit lines BL for reading data of a memory cell are formed. These bit lines BL are arranged above the element isolation grooves 2 and extend in the direction orthogonal to the gate electrodes 7A (word lines WL) with the same width and the same interval. Each of the bit lines BL is formed through the plug 23 in the through-hole 20 formed in the silicon oxide film 19 below and the plug 18 in the contact hole 16 below it, and one of the source and the drain of the memory cell selecting MISFET Qt ( It is electrically connected to the n-type semiconductor region 9). The bit line BL is, for example, WN_XIt is composed of a conductive film in which a W film is stacked on the film.
First layer wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit section PC. These wirings 30 to 33 are formed of the same conductive film as the bit line BL, and are formed simultaneously with the bit line BL as described later. The wirings 30 and 31 are connected to the source and drain (n) of the n-channel MISFET Qn through the plug 23 in the contact hole 21 formed in the silicon oxide films 19 and 15.⁺Wirings 32 and 33 are connected to the source and drain (p) of the p-channel MISFET Qp via the plug 23 in the contact hole 22 formed in the silicon oxide films 19 and 15.⁺Is electrically connected to the mold semiconductor region 13).
An interlayer insulating film 40 is formed above the bit lines BL and the first-layer wirings 30 to 33. The interlayer insulating film 40 is composed of a spin-on glass film and a two-layer silicon oxide film formed thereon, like the lower interlayer insulating film 15, and the surface thereof has substantially the same height over the entire area of the substrate 1. It is flattened so that
Through holes 43 are formed in the interlayer insulating film 40 of the memory array and the underlying silicon oxide film 19. The through-hole 43 is disposed immediately above the contact hole 17 thereunder, and a plug 44 made of, for example, an n-type polycrystalline silicon film doped with P (phosphorus) is embedded therein. I have.
Above the interlayer insulating film 40, a silicon nitride film 45 and a thick silicon oxide film 46 are formed, and a lower electrode 48 is formed in a deep groove 47 formed in the silicon oxide film 46 of the memory array. , An information storage capacitive element C composed of a capacitive insulating film 49 and an upper electrode 50 is formed. The lower electrode 48 of the information storage capacitance element C is made of, for example, a low-resistance n-type polycrystalline silicon film doped with P (phosphorus), and the memory is formed through the through hole 43 and the contact hole 17 formed thereunder. It is electrically connected to the other of the n-type semiconductor regions (source, drain) 9 of the cell selection MISFET Qt. The capacitance insulating film 49 of the information storage capacitor C is, for example, Ta.₂O₅The upper electrode 50 is made of, for example, a TiN film.
A silicon oxide film 51 is formed on the information storage capacitor C, and about two layers of Al wiring are formed on the silicon oxide film 51, but these are not shown.
Next, an example of a method of manufacturing the DRAM of the present embodiment configured as described above will be described in the order of steps with reference to FIGS.
First, as shown in FIG. 4, a substrate (wafer) 1 made of, for example, p-type single-crystal silicon is prepared, and an element isolation groove 2 is formed on the main surface thereof. After ion implantation of P (phosphorus) into the other part, the substrate 1 is heat-treated at about 950 ° C. for about 10 minutes to diffuse these impurities, thereby forming the p-type well 3 and the n-type well 4. Form. In order to form the element isolation groove 2, for example, an element isolation region of the substrate 1 is etched to form a groove having a depth of about 350 nm, and subsequently, inside the groove and on the substrate 1 by a CVD (Chemical Vapor Deposition) method. After depositing the silicon oxide film 5, the unnecessary silicon oxide film 5 outside the groove is removed by a chemical mechanical polishing (CMP) method. As shown in FIG. 5, by forming the element isolation grooves 4, a plurality of active regions L having an elongated island-shaped pattern surrounded by the element isolation grooves 2 are formed on the substrate 1 of the memory array. Is done.
Next, after cleaning the surface of the substrate 1 with hydrofluoric acid, as shown in FIG. 6, the surface of the p-type well 3 and the surface of the n-type well 4 are formed of a silicon oxide film by steam oxidation of the substrate 1. A clean gate insulating film 6 is formed. The thickness of the gate insulating film 6 is, for example, 6 nm. The gate insulating film 6 may be formed of a silicon oxynitride film, a silicon nitride film, a composite insulating film of a silicon oxide film and a silicon nitride film instead of the silicon oxide film.
Next, as shown in FIG. 7, an n-type polycrystalline silicon film 14n doped with P (phosphorus) is deposited on the gate insulating film 6. The polycrystalline silicon film 14n is made of, for example, monosilane (SiH₄) And phosphine (PH₃) Is deposited by a CVD method using a source gas (film formation temperature = about 630 ° C.), and its film thickness is about 70 nm. The polycrystalline silicon film 14n has a P concentration of 1.0 × 10 4 in order to reduce electric resistance.¹⁹cm³Above.
Instead of the polycrystalline silicon film 14n, a silicon film containing Ge (germanium) at 5% to about 50% at the maximum can be used. When Ge is included in silicon, the upper layer WN is reduced due to a narrow band gap of silicon and a high solid solubility limit of impurities._XThere is an advantage that the contact resistance with the film is reduced. In order to incorporate Ge into silicon, a method of introducing Ge into a silicon film by ion implantation, as well as monosilane (SiH₄) And GeH₄There is a method of depositing a silicon film containing Ge by a CVD method using the above.
Next, after the surface of the polycrystalline silicon film 14n is washed with hydrofluoric acid, as shown in FIG._XA film 24 and a W film 25 having a thickness of about 70 nm are successively deposited, and a silicon nitride film 8 having a thickness of about 160 nm is deposited on the W film 25 by CVD. WN_XThe film 24 functions as a barrier layer that prevents a reaction between the polycrystalline silicon film 14n and the W film 25. When depositing the silicon nitride film 8, in order to suppress oxidation of the surface of the W film 25, about 10 nm is formed on the W film 25 by using a plasma CVD method which can be formed at a relatively low temperature (around 480 ° C.). After depositing a thin silicon nitride film, and then performing lamp annealing at about 950 ° C. for about 10 seconds to remove gas components in the silicon nitride film, a low-pressure CVD method (forming It is preferable to deposit a silicon nitride film with a thickness of about 150 nm using the film temperature of about 780 ° C.). Alternatively, after a silicon oxide film is deposited on the W film 25 using a plasma CVD method, the silicon nitride film 8 may be deposited on the silicon oxide film using a low pressure CVD method.
Next, as shown in FIG. 9, using the photoresist film 26 formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the W film 24, and the WN_XBy sequentially dry-etching the film 25 and the polycrystalline silicon film 14n, a gate electrode 7A (word line WL) is formed on the gate insulating film 6 of the memory array, and a gate electrode 7B is formed on the gate insulating film 6 of the peripheral circuit portion. , 7C. As shown in FIG. 10, the gate electrode 7A (word line WL) is formed to extend in a direction orthogonal to the long side of the active region L. The line width (gate length) of the gate electrode 7A (word line WL) and the interval between adjacent gate electrodes 7A (word line WL) are, for example, 0.13 to 0.14 μm.
As described above, the sheet resistance is 2Ω / □ by forming a part of the conductive material forming the gate electrode 7A (word line WL) and the gate electrodes 7B and 7C into a polymetal structure formed of a low-resistance metal (W). Since the gate delay is suppressed to a degree or less and the gate delay is suppressed, a DRAM operating at high speed can be realized.
In the above-described dry etching process for forming the gate electrodes 7A (word lines WL), 7B, and 7C, as shown in FIG. 11, the substrate 1 around the gate electrodes 7A (word lines WL), 7B, and 7C is formed. It is desirable to leave the gate insulating film 6 thin (for example, about 3 nm) on the surface. When the substrate 1 under the gate insulating film 6 is exposed by this dry etching, contamination (contaminant) containing W, which is a part of the gate electrode material, directly adheres to the surface of the substrate 1 in a later heat treatment step. There is a possibility that a reaction product such as W silicide which is difficult to remove by a normal cleaning process may be generated.
Next, the substrate 1 is transported from the dry etching apparatus to the ashing apparatus, and as shown in FIG.₂The photoresist film 26 is removed by ashing using plasma.
When the substrate 1 is transferred from the dry etching apparatus to the ashing apparatus, the surface of the substrate 1 is exposed to the air in the process. Also, O₂When the photoresist film 26 is removed by ashing using plasma, the surface of the substrate 1 becomes O₂Exposure to plasma atmosphere. Therefore, when the ashing is completed, an undesired oxide (WO) is formed on the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, 7C as shown in FIG._X) 27 is formed. The oxide 27 sublimates in the subsequent heat treatment step, adheres to the inner wall of the heat treatment chamber, and then adheres again to the surface of the substrate 1 to become a contaminant, and deteriorates the characteristics of the element (refresh failure in the case of DRAM). Etc.).
As described above, in the dry etching process for forming the gate electrodes 7A, 7B, and 7C, the gate insulating film 6 in the lower part of the side walls of the gate electrodes 7A, 7B, and 7C and in the peripheral region is also shaved to some extent. Since the thickness is reduced (see FIG. 13), problems such as a reduction in the gate breakdown voltage occur as it is. Therefore, in order to supplement and regenerate the thinned gate insulating film 6, a reoxidation process is performed by the following method.
FIG. 14 is a schematic diagram showing an example of a batch type vertical oxidation furnace used for the re-oxidation treatment of the gate insulating film 6. The vertical oxidation furnace 150 includes a chamber 151 formed of a quartz tube, and a heater 152 for heating the wafer (substrate) 1 is provided around the chamber 151. Inside the chamber 151, a quartz boat 153 that holds a plurality of wafers 1 horizontally is installed. Further, a gas introduction pipe 154 for introducing a water vapor / hydrogen mixed gas and a purge gas and an exhaust pipe 155 for discharging these gases are connected to the bottom of the chamber 151. A gas generator 140 as shown in FIGS. 15 and 16 is connected to the other end of the gas introduction pipe 154.
FIG. 15 is a schematic diagram showing a catalytic steam / hydrogen mixed gas generator connected to the batch type vertical oxidation furnace 150, and FIG. 16 is a piping diagram of the gas generator. The gas generator 140 includes a reactor 141 made of a heat-resistant and corrosion-resistant alloy. Inside the reactor 141, a coil 142 made of a catalytic metal such as Pt (platinum), Ni (nickel), or Pd (palladium) and a coil 142 A heater 143 for heating 142 is provided. A process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen are introduced into the reactor 141 from the gas storage tanks 144a, 144b, 144c through a pipe 145. Further, between the gas storage tanks 144a, 144b, 144c and the pipe 145, mass flow controllers 146a, 146b, 146c for adjusting the amount of gas, and opening / closing valves 147a, 147b, 147c for opening and closing the gas flow path are provided. Thus, the amount and the component ratio of the gas introduced into the reactor 141 are precisely controlled by these.
The process gas (hydrogen and oxygen) introduced into the reactor 141 is excited by contacting the coil 142 heated to about 350 to 450 ° C., and hydrogen radicals are generated from hydrogen molecules (H₂→ 2H *), oxygen radicals are generated from oxygen molecules (O₂→ 2O *). Since these two radicals are chemically very active, they react quickly to form water (2H * + O * → H₂O). Therefore, a steam / hydrogen mixed gas can be obtained by introducing into the reactor 141 a process gas containing hydrogen in excess of the molar ratio (hydrogen: oxygen = 2: 1) at which water (steam) is generated. it can. This mixed gas is mixed with hydrogen supplied from a dilution line 148 shown in FIG. 16 and adjusted to a steam / hydrogen mixed gas having a desired moisture concentration, and then passed through the gas introduction pipe 154 to form a vertical oxidation furnace. 150 chambers 151 are introduced.
Since the catalytic type gas generator 140 as described above can control the amounts of hydrogen and oxygen involved in the generation of water and their ratio with high accuracy, the water vapor in the water vapor / hydrogen mixed gas introduced into the chamber 151 can be controlled. The concentration can be controlled over a wide range from a very low concentration on the order of ppm to a high concentration of about several tens of percent and with high accuracy. In addition, since water is instantaneously generated when the process gas is introduced into the reactor 141, a steam / hydrogen mixed gas having a desired steam concentration can be obtained in real time. This also minimizes the entry of foreign matter, so that a clean steam / hydrogen mixed gas can be introduced into the chamber 151. Note that the catalyst metal in the reactor 141 is not limited to the above-described metals as long as it can radicalize hydrogen and oxygen. In addition to processing the catalyst metal into a coil shape, the catalyst metal may be processed into, for example, a hollow tube or a fine fiber filter, and a process gas may be passed through the inside.
FIG. 17 shows an equilibrium vapor pressure ratio (P) of an oxidation-reduction reaction using a steam / hydrogen mixed gas._H2O/ P_H2) Is a graph showing the temperature dependence of each of the curves, and curves (a) to (e) in the figure show the equilibrium vapor pressure ratios of W, Mo, Ta (tantalum), Si, and Ti (titanium), respectively. As shown in the figure, the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 151 of the vertical oxidation furnace 150 is set within the range between the curves (a) and (d). The W films 25 and WN forming the gate electrodes 7A, 7B, 7C_XThe substrate 1 made of silicon can be selectively oxidized without oxidizing the film 24. As shown in the figure, the oxidation rate of both metals (W, Mo, Ta, Ti) and silicon increases as the water vapor concentration in the water vapor / hydrogen mixture gas increases. Therefore, by increasing the water vapor concentration in the water vapor / hydrogen mixed gas introduced into the chamber 151, silicon can be selectively oxidized by heat treatment in a shorter time. When the metal parts of the gate electrodes 7A, 7B, 7C are made of Mo (molybdenum), the water vapor / hydrogen partial pressure ratio is set within the range between the curves (b) and (d). Thus, only silicon can be selectively oxidized without oxidizing the Mo film.
Next, an example of a reoxidation process sequence using the batch type vertical oxidation furnace 150 will be described with reference to FIG.
First, a quartz boat 153 holding a plurality of wafers 1 is loaded into a chamber 151 filled with a purge gas (nitrogen). The time required for loading the quartz boat 153 is about 10 minutes. At this time, the purge gas (nitrogen) in the chamber 151 is preheated in advance in order to shorten the time for raising the temperature of the wafer 1. However, at high temperatures, the oxide 27 formed on the side walls of the gate electrodes 7A, 7B, 7C tends to sublime, so the upper limit of the preheating temperature should be less than 500 ° C.
Next, hydrogen gas is introduced into the chamber 151 for about 10 minutes through the gas introduction pipe 154, and the gas in the chamber 151 is replaced, so that the atmosphere in the chamber 151 is reduced to an atmosphere in which the W oxide 27 is reduced. Then, the wafer 1 is heated to a temperature of 600 ° C. or more, for example, 800 ° C. over about 30 to 40 minutes while continuously supplying the hydrogen gas into the chamber 151. In order to introduce only hydrogen gas into the chamber 151, the supply of oxygen may be interrupted before the reactor 141 and only hydrogen may be supplied.
As described above, when the temperature of the wafer 1 is increased under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, and 7C is reduced, most of the oxide 27 is reduced to W, so that the chamber 151 It is possible to keep the amount of the oxide 27 sublimed in the inside at an extremely low level. Thereby, the contamination of the substrate 1 in the step of re-oxidizing the gate insulating film 6 can be kept at an extremely low level, so that the reliability and manufacturing yield of the DRAM are improved.
Next, oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a steam / hydrogen mixed gas containing about 10% of water generated from oxygen and hydrogen by a catalytic action in a partial pressure ratio of about 151% is supplied to the chamber 151. To be introduced. Then, the temperature of the water vapor / hydrogen mixed gas in the chamber 151 is maintained at 800 ° C., and the atmospheric pressure is maintained at a normal pressure, or a quasi-normal pressure reduction region (Subatmospheric pressure region) which is a pressure reduction region of about 10% to about 50% of the atmospheric pressure. The surface of the wafer 1 is oxidized for 25 to 30 minutes. Depending on the type of the oxidation furnace, the oxidation treatment may be performed in a lower pressure reduction region. However, if the pressure during the oxidation treatment is low, the oxide 27 remaining on the side walls of the gate electrodes 7A, 7B, and 7C is sublimated. It will be easier. Therefore, it is desirable that the pressure during the oxidation treatment be at least about 1300 Pa or more.
By performing the above-described oxidation treatment, as shown in FIG. 19, the substrate 1 around the gate electrodes 7A, 7B, and 7C is re-oxidized. Therefore, the gate insulating film thinned in the above-described dry etching step. The film thickness of No. 6 is almost equal to the initial film thickness (6 nm). In this oxidation treatment, the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 151 is set within the range between the curves (a) and (d) shown in FIG. The W film 25 and the WN forming the gate electrodes 7A, 7B, 7C_XThe film 24 is not oxidized.
Next, by shutting off the supply of oxygen before the reactor 141, the wafer 1 is cooled to a temperature of less than 500 ° C., for example, 400 ° C. in about 30 to 40 minutes while supplying only hydrogen into the chamber 151. Cool down. Subsequently, the supply of hydrogen gas is stopped, nitrogen gas is introduced into the chamber 151 for about 10 minutes to perform gas replacement, and then the quartz boat 153 is unloaded from the chamber 151. If the temperature at which the inside of the chamber 151 is switched from the hydrogen gas atmosphere to the nitrogen gas atmosphere is high, the W film 25 on the side walls of the gate electrodes 7A, 7B and 7C and the oxide 27 remaining without being reduced may sublime. There is. Therefore, the replacement of the hydrogen gas with the nitrogen gas is preferably performed after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. When the time required for the oxidation treatment is not relatively demanding, it is preferable to switch to the nitrogen gas atmosphere after the temperature of the wafer 1 has dropped to about 100 ° C., more preferably to 70 ° C. to room temperature. Needless to say, the oxidation of the W film 25 can be suppressed.
The above-described re-oxidation treatment of the gate insulating film 6 can also be performed by using a single-wafer oxidation furnace employing an RTA (Rapid Thermal Annealing) method. FIG. 20A is a schematic diagram illustrating an example of a single-wafer oxidation furnace used for the re-oxidation treatment, and FIG. 20B is a cross-sectional view taken along line B-B ′ in FIG.
The single-wafer oxidation furnace 100 includes a chamber 101 formed of a multi-wall quartz tube, and a halogen lamp 107 for heating the wafer 1 is provided below the chamber 101. Inside the chamber 101, a disc-shaped soaking ring 103 for uniformly dispersing the heat supplied from the halogen lamp 107 over the entire surface of the wafer 1 is accommodated, and a susceptor 104 for horizontally holding the wafer 1 is mounted on the ring. Is placed. The heat equalizing ring 103 is made of a heat-resistant material such as quartz or SiC (silicon carbide), and is supported by a support arm 105 extending from a wall surface of the chamber 101. A thermocouple 106 for measuring the temperature of the wafer 1 held by the susceptor 104 is provided near the heat equalizing ring 103.
One end of a gas introduction pipe 108 for introducing a steam / hydrogen mixed gas and a purge gas into the chamber 101 is connected to a part of the wall surface of the chamber 101. The other end of the gas introduction pipe 108 is connected to the catalytic gas generator 140 shown in FIGS. A partition 110 having a large number of through holes 109 is provided in the vicinity of the gas introduction pipe 108, and gas introduced into the chamber 101 passes through the through holes 109 of the partition 110 and enters the chamber 101. Spread evenly. One end of an exhaust pipe 111 for discharging the gas introduced into the chamber 101 is connected to another part of the wall surface of the chamber 101.
The reoxidation process using the single-wafer oxidation furnace 100 is almost the same as the reoxidation process using the batch vertical oxidation furnace 150 except that the wafers 1 are oxidized one by one. However, since the temperature rise and fall of the wafer 1 by lamp heating is performed in a very short time (normally, about several seconds), the loading / unloading of the wafer 1 is performed at room temperature.
An example of the re-oxidation process using the above single-wafer oxidation furnace 100 will be described. First, a chamber 101 previously filled with a purge gas (nitrogen) at room temperature is opened to process the gate electrodes 7A, 7B, and 7C. Is loaded on the susceptor 104. Next, the chamber 101 is closed and a hydrogen gas is introduced, and after the inside of the chamber 101 is set to a hydrogen gas atmosphere, the wafer 1 is heated to a temperature of 600 ° C. or more, for example, 950 ° C. over about 5 seconds while maintaining this atmosphere. Warm up.
Next, oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a steam / hydrogen mixed gas containing about 10% of water generated by the catalytic action at a partial pressure ratio is introduced into the chamber 101. Then, the halogen lamp 107 is turned on, and the surface of the wafer 1 is oxidized for about 3 minutes while maintaining the temperature of the steam / hydrogen mixed gas in the chamber 101 at 950 ° C.
Next, the halogen lamp 107 is turned off, the supply of the water vapor / hydrogen mixed gas is stopped, and the inside of the chamber 101 is returned to a hydrogen atmosphere. Thereafter, the wafer 1 is kept at a temperature lower than 500 ° C. for about 10 seconds while maintaining this atmosphere. , For example, to 400 ° C. Next, after the supply of hydrogen gas is stopped and nitrogen gas is introduced into the chamber 101 to perform gas replacement, the wafer 1 is unloaded when the temperature in the chamber 101 falls to about room temperature. Also in this case, the replacement of the hydrogen gas with the nitrogen gas is preferably performed after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. When the time required for the oxidation treatment is not relatively demanding, it is preferable to switch to the nitrogen gas atmosphere after the temperature of the wafer 1 has dropped to about 100 ° C., more preferably to 70 ° C. to room temperature. Needless to say, the oxidation of the W film 25 can be suppressed.
By performing the reoxidation process as described above, the W film 25 and the WN constituting the gate electrodes 7A, 7B, and 7C can be obtained similarly to the reoxidation process using the batch type vertical oxidation furnace 150._XThe gate insulating film 6 can be made thicker without oxidizing the film 24. Further, by raising and lowering the temperature of the wafer 1 under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, 7C is reduced, the amount of the oxide 27 sublimated in the chamber 151 can be kept at an extremely low level. Therefore, contamination of the substrate 1 in the step of re-oxidizing the gate insulating film 6 can be kept at an extremely low level. According to the experiments of the present inventors, even when the batch type vertical oxidation furnace 150 is used or when the single-wafer type oxidation furnace 100 is used, the temperature rise to the desired temperature and the subsequent temperature decrease are reduced. It was confirmed that the amount of the oxide 27 adhering to the surface of the substrate 1 was reduced by about two to three orders by performing the heat treatment in a hydrogen atmosphere as compared with the case where the temperature was raised and lowered in a nitrogen atmosphere.
In the reoxidation process described above, the temperature of the wafer 1 was raised and lowered in a hydrogen atmosphere. However, another gas capable of reducing an oxide of W, for example, ammonia (NH₃), CO, N₂It may be performed in a gas atmosphere such as O. However, when these gases are used, it is necessary to increase the piping system of the oxidation furnace. In addition, a rare gas such as argon (Ar), helium (He), or xenon (Xe) can be used as the purge gas in addition to nitrogen.
In the re-oxidation process described above, the wafer 1 was oxidized using a water vapor / hydrogen mixed gas. However, another gas that can oxidize silicon without oxidizing the W film or the Mo film, for example, oxygen (O 2)₂), NO, CO, CO₂For example, an oxidizing gas such as the above, or a mixed gas of these oxidizing gases and a mixed gas of water vapor and hydrogen may be used. However, CO and CO₂May react with W or Mo during the heat treatment to generate foreign matter such as carbide. Therefore, it is necessary to pay attention to this point.
According to the above reoxidation process, the oxide contamination on the surface of the substrate 1 is kept at an extremely low level, so that the temperature rise to a desired temperature and the subsequent temperature fall are performed in a nitrogen atmosphere. The amount of the oxide 27 adhering to the surface of No. 1 could be reduced by about 2 to 3 digits.
However, even if the temperature of the wafer 1 is raised and lowered in a reducing atmosphere in the above reoxidation process, slight oxide contamination may be attached during the reoxidation process. In this case, oxide contamination may be knocked on in the gate insulating film 6 during the next step of ion implantation of impurities, which may deteriorate the electrical characteristics of the device.
Therefore, it is effective to wet-clean the surface of the substrate (wafer) 1 before moving to the next ion implantation step to further reduce the level of oxide contamination. However, the cleaning here needs to be performed under the condition that the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, 7C is not oxidized. In particular, the surface of the W film 25 exposed to the reducing atmosphere in the reoxidation process is more active than the normal W film, and the surface area of the W film 25 is increased by the reduction of the oxide 27. It is more easily oxidized than the W film 25 before the process.
Therefore, it is necessary to avoid using an oxidizing solution also in this washing step. That is, it is desirable to wash with a reducing solution and also remove the W oxide present on the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, 7C at the same time. In order to realize this condition, the present inventors have proposed a redox potential and pH phase diagram of the tungsten-water system shown in FIG. : Electrochemistry of Chemical Vapor Deposited Tungsten Films with Relevance to Chemical Mechanical Polishing in J. Electrochem., J. Electrochem., Vol. And WO₄It has been found that it is desirable to use water having properties near the boundary of the negative ion existence region.
As a result of the experiment, by using such water, the W oxide (WO_X) Is WO₄Eluted in water as negative ions, and thereafter the surface of the W film was hardly oxidized. Such desirable effects can be obtained by using substantially neutral or weakly alkaline pure water or a chemical solution having a pH of 6.5 or more and less than 12, more preferably a pH of 7 or more and less than 10.5. Was the case. In addition, oxide contamination could be removed by about three orders of magnitude only by washing with ultrapure water. Further, when the ultrapure water is washed with hydrogen-containing water in which hydrogen gas is added at about 0.2 mg / l to about 2 mg / l, the removal rate of oxide contamination is reduced by one in comparison with the case of using pure water. It was able to increase about 0.5 times.
In order to increase the elution efficiency of oxide contamination, an aqueous solution which is made weakly alkaline by adding ammonia to the above-described ultrapure water or hydrogen-containing water may be used. As a result of the experiment, it was possible to increase the pH to 11.5 and the oxidation-reduction potential to a reduction potential of 580 to 870 mV by adding 0.2 to 120 mmol of ammonia to water. The W oxide formed on the surface could be eluted into water and removed without performing. This result indicates that the WO adhered on the silicon oxide film around the gate electrode_XCan be removed by elution. As a result, the amount of sublimation of W oxide in the next heat treatment step can be reduced, and contamination of the LSI can be suppressed.
It is preferable to use the above-mentioned water or chemical solution which does not substantially contain hydrogen peroxide which easily oxidizes the W film. In addition, even if a small amount of hydrogen peroxide is contained, when the concentration of hydrogen peroxide at a concentration of 30% by weight is set to 100%, not more than 0.3% by volume of hydrogen peroxide is contained. Should be used.
Further, when cleaning the wafer 1 using the above-mentioned water or chemical solution, the efficiency of removing contamination can be further improved by applying mechanical vibration such as ultrasonic waves. Further, in order to prevent the removed contaminants from re-adhering, it is better to perform the cleaning in a flowing water state, not in a still water state. When washing with running water, water-SiO₂Adhesion WO due to the electric double layer formed at the interface and the electrokinetic potential (zeta (ポ テ ン シ ャ ル) potential) of the flowing water_XIt is considered that the effect of removing the contamination increases the effect of reducing contamination.
As described above, the W film exposed to the reducing atmosphere in the reoxidation process is more easily oxidized than the ordinary W film, and thus the above-described cleaning should be performed immediately after the reoxidation treatment. In this case, measures to prevent oxidation due to contact with the air being transported, such as by directly connecting the oxidation furnace to the cleaning device, are also effective.
FIG. 22 is a graph showing the result of measuring the removal effect of the natural oxide film formed on the surface of the W film by washing with water by total reflection X-ray fluorescence. As the W film, those formed at room temperature and those formed at 500 ° C. were used. Since the W film formed at 500 ° C. has higher crystallinity than the W film formed at room temperature, a natural oxide film is hardly formed. In any case, the natural oxide film increases as the water temperature rises from room temperature. However, when the temperature exceeds about 60 ° C., the cleaning effect is higher than the increase in the natural oxide film, so that the removal effect increases. The result was obtained. From this, the temperature of the water or chemical solution at the time of cleaning is from room temperature to less than 50 degrees Celsius, or 70 degrees Celsius or more, more preferably from room temperature to less than 45 degrees Celsius, or 75 degrees Celsius or more, so that the natural oxide film is formed. It can be removed efficiently.
Next, as shown in FIG. 23, the upper part of the p-type well 3 is covered with a photoresist film 28, and B (boron) is ion-implanted into the n-type well 4. Subsequently, after the photoresist film 28 is removed by ashing, as shown in FIG. 24, the upper portion of the n-type well 4 is covered with a photoresist film 29, and As (arsenic) is ion-implanted into the p-type well 3. The dose of B and As is, for example, 3 × 10^Thirteenatoms / cm²It is.
Next, after removing the photoresist film 29 by ashing, the surface of the substrate 1 is wet-cleaned in order to remove ashing residues attached to the surface of the substrate 1. Since this wet cleaning needs to be performed under the condition that the W film (25) exposed on the side walls of the gate electrodes 7A, 7B and 7C is not oxidized, the pure water or the chemical used in the cleaning step immediately after the re-oxidation process is used. I do.
Next, in a nitrogen gas atmosphere at about 950 ° C., the substrate 1 is heat-treated by lamp annealing for about 10 seconds to electrically activate the above impurities, thereby forming both sides of the gate electrodes 7A and 7B as shown in FIG. N in p-type well 3⁻Semiconductor region 9 is formed, and p-type wells 4 are formed in n-type wells 4 on both sides of gate electrode 7C.⁻A type semiconductor region 10 is formed. Thereafter, the surface of the substrate 1 is sublimated from the side walls of the gate electrodes 7A, 7B, 7C by the above-described heat treatment for activating the impurities, and the surface of the substrate 1 is removed in order to remove an extremely small amount of oxide contamination re-adhered to the surface of the substrate 1. May be washed. For this cleaning, it is desirable to use the pure water or the chemical used in the cleaning step immediately after the reoxidation process.
Next, as shown in FIG. 26, a silicon nitride film 11 having a thickness of about 50 nm is deposited on the substrate 1. The silicon nitride film 11 is made of, for example, monosilane (SiH₄) And ammonia (NH₃) Are deposited by a low pressure CVD method using a source gas. The flow of forming the silicon nitride film 11 is, for example, as follows.
First, the wafer 1 is loaded into a chamber of a low-pressure CVD apparatus previously filled with nitrogen. The preheating temperature in the chamber is less than 500 ° C. Next, only ammonia which is a part of the source gas is supplied into the chamber, and the inside of the chamber is set to an atmosphere in which the oxide of W is reduced. Then, the wafer 1 is heated to a temperature of 600 ° C. or more, for example, 730 ° C. to 780 ° C., while continuously supplying ammonia into the chamber. Next, ammonia and monosilane are supplied into the chamber, and these gases are reacted to deposit the silicon nitride film 11. The deposition time of the silicon nitride film 11 is about 10 minutes. Next, the supply of monosilane is stopped, the temperature of the wafer 1 is lowered to less than 500 ° C., for example, 400 ° C. while only supplying ammonia to the chamber, and then the chamber is replaced with nitrogen and the wafer is unloaded. If the temperature at which the inside of the chamber is switched from the ammonia gas atmosphere to the nitrogen gas atmosphere is high, there is a possibility that the W film 25 on the side walls of the gate electrodes 7A, 7B and 7C and the oxide 27 remaining without being reduced will sublime. is there. Therefore, it is more desirable that the replacement of the ammonia gas with the nitrogen gas is performed after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. If the time required for the formation of the silicon nitride film 11 is not relatively severe, the temperature of the wafer 1 is reduced to about 100 ° C., more preferably 70 ° C. to room temperature, and then the wafer 1 is cooled to a nitrogen gas atmosphere. Needless to say, the switching can suppress the oxidation of the W film 25.
By depositing the silicon nitride film 11 by the method described above, the W film 25 and the WN constituting the gate electrodes 7A, 7B, 7C are formed._XThe silicon nitride film 11 can be deposited in a high temperature atmosphere without oxidizing the film 24. Further, since the temperature of the wafer 1 is raised under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, 7C is reduced, the amount of the oxide 27 sublimated in the chamber can be kept at an extremely low level. The contamination of the substrate 1 in the step of forming the silicon nitride film 11 can be kept at an extremely low level.
In the above-described process of depositing the silicon nitride film 11, the temperature of the wafer 1 is raised and lowered in an ammonia atmosphere, but other gases capable of reducing the oxide of W, for example, hydrogen, CO, N₂The temperature of the wafer 1 may be raised and lowered in a gas atmosphere such as O. However, when these gases are used, it is necessary to add a piping system of the CVD apparatus. Further, a rare gas such as argon (Ar), helium (He), or xenon (Xe) can be used as the purge gas. Further, dichlorosilane (SiH₂Cl₂) And ammonia.
By the above process, the concentration of W oxide contamination on the surface of the substrate 1 is reduced to a detection limit level of 1 × 10¹⁰Pieces / cm²As a result, the refresh time of the DRAM has been improved from 50 ms before the countermeasure to 200 ms or more.
The silicon nitride film 11 can be deposited by a plasma CVD method instead of the low pressure CVD method. The plasma CVD method has an advantage in that a film can be formed at a lower temperature (400 ° C. to 500 ° C.) than the low-pressure CVD method, and thus has an advantage in that an oxide of W is hard to be generated. Inferior to CVD method. Also in this case, by raising and lowering the temperature in an atmosphere in which the oxide of W is reduced, the contamination of the substrate 1 in the step of forming the silicon nitride film 11 can be kept at an extremely low level. When a silicon nitride film is deposited by a plasma CVD method, plasma treatment is performed in a reducing atmosphere containing the above-mentioned ammonia or hydrogen in order to remove an oxide formed on the surface of the W film 25 in a preceding step. After that, it is effective to form a film.
Hereinafter, a process after depositing the silicon nitride film 11 will be briefly described. First, as shown in FIG. 27, the upper portion of the substrate 1 of the memory array is covered with a photoresist film (not shown), and the silicon nitride film 11 of the peripheral circuit portion is anisotropically etched to thereby form the peripheral circuit portion. Sidewall spacers 11c are formed on the side walls of the gate electrodes 7B and 7C.
Next, As or P is ion-implanted into the p-type well 3 in the peripheral circuit portion to thereby form a high impurity concentration n.⁺A semiconductor region (source, drain) 12 is formed, and B is ion-implanted into the n-type well 4 to form a p-type semiconductor having a high impurity concentration.⁺Form semiconductor regions (source, drain). Through the steps so far, the n-channel MISFET Qn and the p-channel MISFET Qp in the peripheral circuit section are completed.
Next, as shown in FIG. 28, after forming an interlayer insulating film 15 composed of a spin-on-glass film and two silicon oxide films on the gate electrodes 7A to 7C, a photoresist film (not shown) N by dry etching using⁻The silicon nitride film 11 above the type semiconductor region 9 is removed, and n⁻The contact holes 16 and 17 are formed by exposing the surface of the mold semiconductor region 9. The etching of the silicon nitride film 11 is performed under such a condition that the etching rate of the silicon nitride film 11 with respect to the silicon oxide film 5 buried in the element isolation groove 2 is increased, so that the element isolation groove 5 is not etched deeply. This etching is performed under the condition that the silicon nitride film 11 is anisotropically etched so that the silicon nitride film 11 is left on the side wall of the gate electrode 7A (word line WL). As a result, contact holes 16 and 17 having a fine diameter are formed in a self-aligned manner with respect to gate electrode 7A (word line WL).
Next, as shown in FIG. 29, a plug 18 is formed inside the contact holes 16 and 17. In order to form the plug 18, a P-doped polycrystalline silicon film is deposited inside the contact holes 16 and 17 and the upper part of the interlayer insulating film 15 by a CVD method. The crystalline silicon film is removed by dry etching.
Next, the substrate 1 is heat-treated in a nitrogen gas atmosphere, and P in the polycrystalline silicon film forming the plug 18 is changed to n.⁻The n-type semiconductor region 9 (source, drain) having a low resistance is formed by diffusing it into the type semiconductor region 9. Through the steps so far, the memory cell selecting MISFET Qt is formed in the memory array.
Next, as shown in FIGS. 30 and 31, a silicon oxide film 19 is deposited on the interlayer insulating film 15 by the CVD method, and then the peripheral circuit portion is dry-etched using a photoresist film (not shown) as a mask. Of the n-channel type MISFET Qn by dry etching the silicon oxide film 19 and the interlayer insulating film 15 thereunder.⁺A contact hole 21 is formed in the upper part of the p-type MISFET Qp.⁺A contact hole 22 is formed above the mold semiconductor region 13). At the same time, a through hole 20 is formed above the contact hole 16 by etching the silicon oxide film 19 of the memory array.
Next, as shown in FIG. 32, plugs 23 are formed inside the contact holes 21 and 22 formed in the peripheral circuit portion and the through holes 20 formed in the memory array. In order to form the plug 23, for example, a TiN film and a W film are deposited on the silicon oxide film 19 including the insides of the contact holes 21, 22 and the through hole 20 by a sputtering method and a CVD method. Unnecessary upper W film and TiN film are removed by chemical mechanical polishing.
Next, as shown in FIG. 33, a bit line BL is formed on the silicon oxide film 19 of the memory array, and wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit portion. The bit line BL and the wirings 30 to 33 are formed, for example, on the silicon oxide film 19 by sputtering with a W film and WN._XFilms are deposited and patterned by dry etching using a photoresist film as a mask.
Next, as shown in FIG. 34, an interlayer insulating film 40 composed of a spin-on-glass film and two layers of silicon oxide films is formed on the bit line BL and the wirings 30 to 33, and then the interlayer insulating film 40 is formed. After the silicon oxide film 19 underneath is dry-etched to form a through hole 43 above the contact hole 17, a plug 44 made of a polycrystalline silicon film is formed inside the through hole 43. To form the plug 44, a P-doped polycrystalline silicon film is deposited inside the through hole 43 and on the interlayer insulating film 40 by a CVD method, and then unnecessary polycrystalline silicon on the interlayer insulating film 40 is deposited. The film is removed by dry etching.
Next, as shown in FIG. 35, a silicon nitride film 45 is deposited on the interlayer insulating film 40 by the CVD method, and a silicon oxide film 46 is deposited on the silicon nitride film 45 by the CVD method. Using the resist film as a mask, the silicon oxide film 46 of the memory array is dry-etched, and then the silicon nitride film 45 thereunder is dry-etched to form a groove 47 above the through hole 44.
Next, as shown in FIG. 36, the lower electrode 48 of the information storage capacitor C composed of a polycrystalline silicon film is formed on the inner wall of the groove 47. In order to form the lower electrode 48, first, an amorphous silicon film (not shown) doped with P (phosphorus) is deposited inside the groove 47 and on the silicon oxide film 46 by a CVD method. Unnecessary amorphous silicon film on the upper part is removed by dry etching. Next, the surface of the amorphous silicon film remaining inside the groove 47 is wet-cleaned with a hydrofluoric acid-based cleaning solution, and then monosilane (SiH₄), And then heat-treats the substrate 1 to polycrystallize the amorphous silicon film and grow silicon grains on its surface. Thus, lower electrode 48 made of a polycrystalline silicon film having a roughened surface is formed. Since the surface of the polycrystalline silicon film whose surface is roughened is large, the amount of charge stored in the miniaturized information storage capacitor C can be increased.
Next, as shown in FIG. 37, on the surface on the lower electrode 48 formed inside the groove 47 and on the surface of the silicon oxide film 46 outside the groove 47, a capacitance insulating film 49 of the information storage capacitor C is formed. Ta₂O₅A (tantalum oxide) film is deposited by a CVD method, and then the substrate 1 is subjected to a heat treatment in an oxygen atmosphere.₂O₅Modify and crystallize the film. Then, Ta₂O₅A TiN film to be the upper electrode 50 of the information storage capacitor C is deposited on the film, and a Ta₂O₅The film and the TiN film are removed by etching. Thereby, the upper electrode 50 made of a TiN film, Ta₂O₅An information storage capacitor C constituted by a capacitor insulating film 49 made of a film and a lower electrode 48 made of a polycrystalline silicon film is formed. Further, by the above steps, a DRAM memory cell including the memory cell selecting MISFET Qt and the information storage capacitor C connected in series to the MISFET Qt is completed.
Thereafter, a silicon oxide film 50 is deposited on the information storage capacitor C by the CVD method, and about two layers of Al wiring (not shown) are formed on the silicon oxide film 50, thereby forming the embodiment shown in FIGS. Form of DRAM is completed.
(Embodiment 2)
The present embodiment is applied to a DRAM with embedded logic, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS. The left part of each cross-sectional view showing the manufacturing method shows a part of a DRAM memory array, and the right part shows a part of a logic part.
First, as shown in FIG. 38, a substrate 1 made of, for example, p-type single crystal silicon is prepared, and an element isolation groove 2 is formed on the main surface of the substrate 1 in the same manner as in the first embodiment. A p-type well 3 is formed in one part and an n-type well 4 is formed in another part, and then the substrate 1 is subjected to steam oxidation to form a film on the surface of the p-type well 3 and the surface of the n-type well 4. A clean gate insulating film 6 made of a silicon oxide film having a thickness of about 6 nm is formed. The gate insulating film 6 may be formed of a silicon oxynitride film, a silicon nitride film, a composite insulating film of a silicon oxide film and a silicon nitride film instead of the silicon oxide film.
Next, as shown in FIG. 39, a non-doped amorphous silicon film 14a is deposited on the gate insulating film 6. The amorphous silicon film 14a is made of, for example, monosilane (SiH₄) Is deposited by a CVD method using a source gas, and its film thickness is about 70 nm. Monosilane (SiH₄When the amorphous silicon film 14a is formed by the CVD method using ()) as a source gas, the film formation temperature is set in the range of 500 ° C. to 550 ° C., for example, 530 ° C. When the film formation temperature is set to 600 ° C. or higher, a polycrystalline silicon film 14n is obtained as in the first embodiment. In addition, dinosilane (Si₂H₆In the case where is deposited by a CVD method using a source gas, the amorphous silicon film 14a can be obtained by forming the film at a temperature lower than the temperature at which the polycrystalline silicon film can be obtained, for example, at about 520 ° C. Instead of the non-doped amorphous silicon film 14a, a silicon film containing about 50% of Ge (germanium) at the maximum may be used. For example, a polycrystalline silicon film is deposited by a CVD method, and then Ge is introduced into the polycrystalline silicon film by an ion implantation method, whereby an amorphous silicon film containing Ge can be obtained.
As will be described later, the logic-embedded DRAM of the present embodiment uses a polycrystalline part which is a part of the gate electrode of the n-channel MISFET in order to make both the n-channel MISFET and the p-channel MISFET of the logic part a surface channel type. The silicon film is formed of n-type, and the polycrystalline silicon film, which is a part of the gate electrode of the p-channel MISFET, is formed of p-type. In this case, a non-doped polycrystalline silicon film is deposited on the gate insulating film 6, and then boron (B) is ion-implanted to make the polycrystalline silicon film in the p-channel MISFET formation region into a p-type. In some cases, there is a possibility that part of boron may penetrate through the polycrystalline silicon film and the gate insulating film 6 due to the channeling phenomenon and be introduced into the channel region of the substrate 1.
Therefore, when a part of the gate electrode of the p-channel MISFET is formed of a p-type polycrystalline silicon film as in the present embodiment, it is desirable to use the amorphous silicon film 14a, which is unlikely to cause the channeling phenomenon. On the other hand, when the silicon films of all the gate electrodes (7A, 7B, 7C) are made of an n-type conductive silicon film as in the DRAM of the first embodiment, the problem of the penetration of boron described above is caused. Therefore, a polycrystalline silicon film may be used instead of the amorphous silicon film 14a.
Next, as shown in FIG. 40, the upper part of the p-type well 3 is covered with a photoresist film 60, and B (boron) is ion-implanted into the amorphous silicon film 14a on the upper part of the n-type well 4. The dose amount of B is, for example, 2 × 10^Fifteenatoms / cm²The implantation energy is, for example, 5 keV. Subsequently, after the photoresist film 60 is removed by ashing, as shown in FIG. 41, the upper part of the n-type well 4 is covered with a photoresist film 61, and P (phosphorus) is added to the amorphous silicon film 14a on the p-type well 3. ) Is ion-implanted. The dose amount of P is, for example, 2 × 10^Fifteenatoms / cm²The implantation energy is, for example, 10 keV.
Next, the photoresist film 61 is removed by ashing, the surface of the polycrystalline silicon film 14n is washed with hydrofluoric acid, and lamp annealing is performed in a nitrogen atmosphere at about 950 ° C. for about 1 minute to perform an amorphous silicon film. 14a is crystallized and the impurities (B and P) are electrically activated. Thereby, as shown in FIG. 42, the amorphous silicon film 14a in the n-channel MISFET formation region becomes an n-type polycrystalline silicon film 14n, and the amorphous silicon film 14a in the p-channel MISFET formation region becomes p-type polycrystalline silicon. It becomes the film 14p.
Note that a WN is formed on the amorphous silicon film 14a._XWhen a heat treatment for crystallizing the amorphous silicon film 14a is performed after the film or the W film is deposited, a change in stress due to the crystallization of silicon causes WN._XThere is a possibility that the film or the W film may peel off. Before the impurities (B, P) in the amorphous silicon film 14a diffuse to the interface with the gate insulating film 6, WN_XSince it is taken into the film or the W film, depletion occurs near the interface of the gate insulating film 6, and there is a possibility that desired device characteristics may not be obtained. Therefore, the above-mentioned heat treatment forms WN on the amorphous silicon film 14a._XIt is desirable to perform this before depositing a film or a W film.
Next, after the surfaces of the polycrystalline silicon films 14n and 14p are cleaned using hydrofluoric acid, as shown in FIG. 43, an amorphous silicon film 34a is deposited on the polycrystalline silicon films 14n and 14p. The amorphous silicon film 34a is made of, for example, monosilane (SiH₄) Is deposited by CVD using a source gas (film formation temperature = about 530 ° C.), and its film thickness is about 10 nm. The amorphous silicon film 34a has an initial impurity concentration of 1.0 × 10¹⁷cm³Amorphous silicon with an extremely low impurity concentration of less than 1.0 × 10¹⁴cm³Less than substantially non-doped amorphous silicon. The amorphous silicon film 34a is composed of an extremely thin natural oxide film formed on the surface of the polycrystalline silicon films 14n and 14p, and a WN deposited on the natural oxide film in the next step._XIt is formed to block contact with the film 24. The amorphous silicon film 34a may not be in a completely amorphous state, but may be, for example, an aggregate of extremely small silicon crystal grains.
Next, after cleaning the surface of the amorphous silicon film 34a using hydrofluoric acid, as shown in FIG._XA film 24 and a W film 25 are successively deposited, and then a silicon nitride film 8 is deposited on the W film 25 by a CVD method. WN_XThe thickness of the film 24 is about 5 nm to 10 nm. Also, WN_XThe thickness of the W film 25 deposited on the film 24 is about 70 nm to 80 nm, and the thickness of the silicon nitride film 8 is about 160 nm. WN_XOn top of the film 24, a Mo film may be deposited instead of the W film 25.
In the present embodiment, the WN_XWhen the film 24 is formed by a sputtering method, WN is applied under such a condition that the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more, more preferably 18% or more._XA film 24 is formed. Such a WN_XTo form the film 24, use WN_XThe film may be formed in an atmosphere in which the film 24 contains a high concentration of nitrogen. That is, sputtering may be performed by setting the atmosphere in the chamber to a gas atmosphere in which the flow ratio of nitrogen gas to argon gas is 1.0 or more. Specifically, for example, a film is formed under the conditions of a nitrogen gas flow rate = 50 sccm to 80 sccm, an argon gas flow rate = 20 sccm to 30 sccm, a degree of vacuum in the chamber = 0.5 Pa, and a temperature = 200 ° C. to 500 ° C.
In addition, WN during film formation_XIt is desirable that the thickness of the film 24 be in the range of 5 nm to 10 nm. WN during film formation_XBy setting the film thickness of the film 24 to 5 nm or more, WN_XEven if a part of the film 24 reacts with the underlying silicon layer, the remaining film thickness when the device is completed is at least 1 nm or more, so that the function as a barrier layer is secured. On the other hand, WN during film formation_XIf the thickness of the film 24 exceeds 10 nm, the wiring resistance of the gate electrode increases, which is disadvantageous for high-speed operation of the circuit.
Also, WN_XEven when the film is formed in an atmosphere in which the film 24 contains a high concentration of nitrogen, excessive nitrogen is diffused and separated in a heat treatment process after the film formation, so_XThe film 24 has the most stoichiometrically stable W₂N is the main subject. However, WN_XSince part of the film 24 reacts with the underlying silicon layer during the heat treatment,_XThe film 24 is made of W₂N and other WN_XIn some cases, the mixed crystal further contains WSiN.
Next, as shown in FIG. 45, using the photoresist film 62 formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the W film 24, WN_XBy sequentially dry-etching the film 25, the amorphous silicon film 34a and the polycrystalline silicon films 14n and 14p, a gate electrode 7A (word line WL) is formed on the gate insulating film 6 of the memory array, and the gate insulating film of the logic section is formed. The gate electrodes 7D and 7E are formed on 6.
After that, the memory cell selecting MISFET Qt is formed in the memory array by the method described in the first embodiment, and the n-channel MISFET and the p-channel MISFET are formed in the logic section. Also in this case, the re-oxidation treatment, the cleaning treatment, the deposition of the silicon nitride film, and the like of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W can be reduced to an extremely low level. Can be kept.
FIG. 46 is a view showing WN constituting a part of the gate electrodes 7A, 7D and 7E._XNitrogen flow rate and WN when forming film 24_X6 is a graph showing the results of X-ray diffraction measurement of the relationship with the crystal structure of the film 24 immediately after the formation of the WNx film 24 and after heat treatment in a nitrogen gas at 950 ° C. for 1 minute. As shown, WN_XIf the flow rate of nitrogen at the time of forming the film 24 is 10 sccm, WN_XSince nitrogen in the film 24 is released to become a W film, WN_XThe function of the film 24 as a barrier layer is lost.
FIG. 47 shows a WN film formed by changing the flow rate of nitrogen gas while keeping the flow rate of argon gas constant (40 sccm)._XIt is the graph which measured the film stress when the film was heat-treated at various temperatures, (a) shows the case where the film was formed at a substrate temperature of 400 ° C., and (b) shows the case where the film was formed at a substrate temperature of 200 ° C. . As shown, WN_XWhen the nitrogen flow rate at the time of forming the film is small, it is found that nitrogen is released by the subsequent heat treatment and the film shrinks, so that the film stress increases.
FIG. 48 shows a WN film formed by changing the flow ratio of nitrogen gas and argon gas._XWithstand voltage of gate electrode including film, and WN_XThe result of examining the relationship between the contact resistance of the film / polycrystalline silicon film interface is shown. As shown in the figure, the WN film was formed under the condition that the flow rate ratio of the nitrogen gas was small._XIn the case of a film, the withstand voltage of the gate electrode decreases,_XThe contact resistance at the film / polycrystalline silicon film interface increases.
Thus, WN_XAccording to the present embodiment in which the film 24 is formed in an atmosphere containing a high concentration of nitrogen, the WN_XSince N remains in the film, WN_XThe function of the film 24 as a barrier layer is not lost. Also, WN_XBy interposing an amorphous silicon film 34a between the film 24 and the polycrystalline silicon films 14n and 14p, an extremely thin natural oxide film formed on the surfaces of the polycrystalline silicon films 14n and 14p and WN_XThe formation of a high-resistance layer due to contact with the film 24 can be suppressed. The amorphous silicon film 34a that has undergone the heat treatment process becomes a polycrystalline film having a smaller average crystal grain size than the underlying polycrystalline silicon films 14n and 14p.
By the above process, the WN forming the gate electrodes 7A, 7D, 7E_XThe contact resistance at the interface between the film 24 and the polycrystalline silicon films 14n and 14p is set to 5 kΩ / μm²〜１０10 kΩ / μm²From 1 kΩ / μm²Was able to be reduced.
Further, the re-oxidation process, the cleaning process, the deposition of the silicon nitride film, and the like of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W is kept at an extremely low level. As a result, the refresh time of the DRAM was significantly improved.
(Embodiment 3)
In the second embodiment, WN_XBy interposing an amorphous silicon film 34a between the film 24 and the polycrystalline silicon films 14n and 14p,_XAlthough the contact resistance between the film 24 and the polycrystalline silicon films 14n and 14p is reduced, in the present embodiment, WN_XBy interposing a thin W film 62 between the film 24 and the polycrystalline silicon films 14n and 14p,_XThe contact resistance between the film 24 and the polycrystalline silicon films 14n and 14p is reduced.
This process will be described. First, as shown in FIG. 49, an n-type polycrystalline silicon film 14n is formed on the gate insulating film 6 in the n-channel MISFET formation region, and the gate insulating film 6 in the p-channel MISFET formation region is formed. A p-type polycrystalline silicon film 14p is formed thereon. The steps so far are the same as the steps shown in FIGS. 38 to 42 of the second embodiment.
Next, after the surfaces of the polycrystalline silicon films 14n and 14p are cleaned using hydrofluoric acid, as shown in FIG. 50, a W film 65 is deposited on the polycrystalline silicon films 14n and 14p. The W film 65 is deposited by, for example, a sputtering method, and has a thickness of about 5 nm.
Next, as shown in FIG. 51, WN is formed on the W film 65 in the same manner as in the second embodiment._XA film 24, a W film 25 and a silicon nitride film 8 are sequentially deposited. WN_XThe thickness of the film 24 is about 5 nm to 10 nm, the thickness of the W film 25 is about 70 nm to 80 nm, and the thickness of the silicon nitride film 8 is about 160 nm. WN_XOn top of the film 24, a Mo film may be deposited instead of the W film 25. Also, WN_XThe film 24 is formed in an atmosphere containing a high concentration of nitrogen, as in the second embodiment, and the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more. More preferably, it is 18% or more. Subsequent steps are the same as in the second embodiment.
Thus, WN_XBy interposing the W film 62 between the film 24 and the polycrystalline silicon films 14n and 14p, the W film 62 reacts with the polycrystalline silicon films 14n and 14p in the subsequent heat treatment process, and the W silicide (WSi_X) Is formed. Thereby, the natural oxide film formed on the surfaces of the polycrystalline silicon films 14n and 14p and the WN_XSince the formation of the high-resistance layer due to contact with the film 24 is suppressed, substantially the same effects as in the second embodiment can be obtained.
By the above process, the WN forming the gate electrodes 7A, 7D, 7E_XThe contact resistance at the interface between the film 24 and the polycrystalline silicon films 14n and 14p is set to 5 kΩ / μm²〜１０10 kΩ / μm²From 1 kΩ / μm²Was able to be reduced.
Further, the re-oxidation process, the cleaning process, the deposition of the silicon nitride film, and the like of the gate insulating film 6 are performed in the same manner as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W is kept at an extremely low level. As a result, the refresh time of the DRAM was significantly improved.
In the present embodiment, WN_XA W film 62 is interposed between the film 24 and the polycrystalline silicon films 14n and 14p, and the W film 62 and the polycrystalline silicon films 14n and 14p react during the subsequent heat treatment to form a conductive material mainly composed of W silicide. Although a layer was formed, a thin W silicide film was formed on the polycrystalline silicon films 14n and 14p, and a WN_XThe film 24 and the W film 25 may be deposited. With this, WN_XThe problem that nitrogen in the film 24 diffuses into the interface with the polycrystalline silicon films 14n and 14p to form a high-resistance silicon nitride layer can be prevented. In the case where the W silicide layer is formed by reacting the W film 62 with the polycrystalline silicon films 14n and 14p during the heat treatment, the reaction may occur locally and the gate breakdown voltage may decrease. When a W silicide film is deposited, such a local reaction hardly occurs. The thickness of the W silicide film may be about 5 to 20 nm. Also, WSi_XX is preferably about 2.0 to 2.7.
(Embodiment 4)
The present embodiment is applied to a CMOS logic LSI in which a circuit is formed by an n-channel MISFET and a p-channel MISFET, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS.
First, as shown in FIG. 52, a substrate 1 made of, for example, p-type single-crystal silicon is prepared, and element isolation grooves 2, p-type wells 3, and p-type wells 3 are formed on the main surface of the substrate 1 in the same manner as in the first embodiment. An n-type well 4 and a gate insulating film 6 are sequentially formed.
Next, as shown in FIG. 53, a 1.0 × 10¹⁹cm³After depositing a low-resistance n-type polycrystalline silicon film 14n doped with P (phosphorus) at the above concentration and cleaning the surface of the polycrystalline silicon film 14n using hydrofluoric acid, the polycrystalline silicon film 14n is formed on the polycrystalline silicon film 14n. WN with a film thickness of about 5 to 10 nm by sputtering_XA film 24 is deposited.
As in the second embodiment, WN_XThe film 24 is formed in an atmosphere containing a high concentration of nitrogen, and the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more, more preferably 18% or more. To do. Also, WN_XThe film 24 is deposited to a thickness such that the remaining film thickness when the device is completed is at least 1 nm or more.
Also, as in the third embodiment, the natural oxide film formed on the surface of the polycrystalline silicon film 14n and the WN_XIn order to suppress formation of a high resistance layer due to contact with the film 24, WN_XA W film 62 may be formed between the film 24 and the polycrystalline silicon film 14n.
Next, as shown in FIG. 54, P (phosphorus) is ion-implanted into the main surface of the substrate 1. In this ion implantation, P is WN_XThe energy is applied so as to penetrate the film 24 and reach a region of 10 nm or less from the surface of the polycrystalline silicon film 14n. For example, WN_XWhen the thickness of the film 24 is about 3 nm to 15 nm, the implantation energy of P is 2 keV to 10 keV.
This ion implantation is performed when the P concentration in the surface region of the polycrystalline silicon film 14n is 5 × 10¹⁹atoms / cm³The dose is set as described above. After the ion implantation, lamp annealing may be performed for about one minute in a nitrogen atmosphere at about 950 ° C. to electrically activate the impurities (P) in the polycrystalline silicon film 14n. Note that the impurity (P) in the polycrystalline silicon film 14n is electrically activated in a later heat treatment step, so that the heat treatment here may be omitted.
In the above ion implantation, after depositing the polycrystalline silicon film 14n,_XThis may be performed before the film 24 is deposited. Also, WN_XWhen the W film 62 is formed between the film 24 and the polycrystalline silicon film 14n, this ion implantation is performed after the W film is formed, and thereafter, the WN is formed on the W film._XA film 24 may be deposited.
Next, as shown in FIG._XAfter depositing a W film 25 having a thickness of about 70 nm on the film 24 by sputtering, a silicon nitride film 8 having a thickness of about 160 nm is deposited on the W film 25 by CVD. Note that WN_XOn top of the film 24, a Mo film may be deposited instead of the W film 25. After the W film 25 is deposited, ion implantation is again performed on the main surface of the substrate 1 to remove the W film 25 and WN._XBy doping the polycrystalline silicon film 14n with P through the film 24, the resistance of the surface region of the polycrystalline silicon film 14n may be further reduced.
Next, as shown in FIG. 56, using the photoresist film 63 formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the W film 24, WN_XThe film 25 and the polycrystalline silicon film 14n are sequentially dry-etched to form an n-channel MISFET gate electrode 7F on the p-type well 3 and a p-channel MISFET gate electrode 7G on the n-type well 4. I do.
Thereafter, in order to keep the contamination of the substrate 1 by the oxide of W at an extremely low level, the gate insulating film 6 re-oxidized by the above-mentioned dry etching is subjected to a re-oxidation process, a subsequent cleaning process, and a deposition of a silicon nitride film. This is performed in the same manner as in the first embodiment.
In the present embodiment, the polycrystalline silicon film, which is a part of each of the gate electrodes 7F and 7G, is formed of the n-type. However, in order to make both the n-channel MISFET and the p-channel MISFET of the surface channel type, The polycrystalline silicon film that is a part of the gate electrode 7F of the channel MISFET may be formed of n-type, and the polycrystalline silicon film that is a part of the gate electrode 7G of the p-channel MISFET may be formed of p-type. In this case, as in the second embodiment, a non-doped amorphous silicon film is deposited on the gate insulating film 6 and then ion-implanted using a photoresist film as a mask to form an amorphous silicon film in the n-channel MISFET formation region. By introducing P into the amorphous silicon film in the p-channel MISFET formation region, it is possible to prevent the penetration of B due to the channeling phenomenon.
(Embodiment 5)
In the fourth embodiment, the surface region of the polycrystalline silicon film 14n is reduced in resistance by the ion implantation of impurities. However, the surface region of the polycrystalline silicon film 14n can be reduced in the following method. .
First, as shown in FIG. 57, an element isolation groove 2, a p-type well 3, an n-type well 4, and a gate insulating film 6 are sequentially formed on a main surface of a substrate 1 made of, for example, p-type single crystal silicon. 1.0 × 10 on the gate insulating film 6¹⁹cm³A low-resistance n-type polycrystalline silicon film 14n doped with P (phosphorus) at the above concentration is deposited. The steps so far are the same as in the fourth embodiment.
Next, as shown in FIG. 58, a 5.0 × 10¹⁹cm³After depositing a low-resistance n-type polycrystalline silicon film 64 doped with P at the above concentration by the CVD method, the substrate 1 is heat-treated, and P in the n-type polycrystalline silicon film 64 is changed to the surface of the polycrystalline silicon film 14n. To a surface region of 10 nm or less, and the P concentration of this surface region is 5 × 10¹⁹atoms / cm³Above. After performing this thermal diffusion treatment, P in the polycrystalline silicon film 14n may be electrically activated by performing lamp annealing for about 1 minute in a nitrogen atmosphere at about 950 ° C. Since P in the film 14n is electrically activated in a later heat treatment step, this heat treatment may be omitted.
Next, as shown in FIG. 59, after removing the n-type polycrystalline silicon film 64 by dry etching, the surface of the polycrystalline silicon film 14n exposed on the surface of the substrate 1 is washed with hydrofluoric acid.
Next, as shown in FIG. 60, a WN film having a thickness of about 5 nm to 10 nm is formed on the polycrystalline silicon film 14n by a sputtering method._XA film 24 is deposited. As in the fourth embodiment, WN_XThe film 24 is formed in an atmosphere containing a high concentration of nitrogen, and the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more, more preferably 18% or more. To do. Also, WN_XThe film 24 is deposited to a thickness such that the remaining film thickness when the device is completed is at least 1 nm or more.
Also, as in the third embodiment, the natural oxide film formed on the surface of the polycrystalline silicon film 14n and the WN_XIn order to suppress formation of a high resistance layer due to contact with the film 24, WN_XA W film may be formed between the film 24 and the polycrystalline silicon film 14n.
Thereafter, as shown in FIG._XAfter depositing a W film 25 having a thickness of about 70 nm on the film 24 by sputtering, a silicon nitride film 8 having a thickness of about 160 nm is deposited on the W film 25 by CVD.
Next, as shown in FIG. 62, using a photoresist film 63 formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the W film 24, and the WN_XThe film 25 and the polycrystalline silicon film 14n are sequentially dry-etched to form an n-channel MISFET gate electrode 7F on the p-type well 3 and a p-channel MISFET gate electrode 7G on the n-type well 4. I do.
Thereafter, in order to keep the contamination of the substrate 1 by the oxide of W at an extremely low level, the gate insulating film 6 re-oxidized by the above-mentioned dry etching is subjected to a re-oxidation process, a subsequent cleaning process, a silicon nitride film deposition, etc. This is performed in the same manner as in the first embodiment.
In the present embodiment, P in the polycrystalline silicon film 64 deposited on the polycrystalline silicon film 14n is thermally diffused to reduce the resistance of the surface region of the polycrystalline silicon film 14n. P is introduced into the surface region of the polycrystalline silicon film 14n by ion implantation, then an insulating film such as a silicon oxide film is formed on the polycrystalline silicon film 14n, and heat treatment is performed to introduce P into the surface region of the polycrystalline silicon film 14n. After the P is segregated near the interface with the insulating film, the insulating film may be removed to lower the resistance of the surface region of the polycrystalline silicon film 14n. The insulating film is composed of, for example, a silicon oxide film formed by thermally oxidizing the surface of the polycrystalline silicon film 14n, or a silicon oxide film deposited on the polycrystalline silicon film 14n by a CVD method, but is not limited thereto. Not something.
(Embodiment 6)
The present embodiment is applied to a flash memory, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS.
First, as shown in FIG. 63, after forming the element isolation groove 2, the p-type well 3, and the gate insulating film 6 on the main surface of the substrate 1 by the same method as in the first embodiment, FIGS. As shown, an n-type polycrystalline silicon film 66n having a thickness of about 70 nm to 100 nm is deposited on the substrate 1 by the CVD method. The polycrystalline silicon film 66n is doped with an n-type impurity, for example, phosphorus (P) during the deposition process. Alternatively, an n-type impurity may be doped by ion implantation after depositing a non-doped polycrystalline silicon film. The polycrystalline silicon film 66n is used as a floating gate electrode of a MISFET forming a memory cell.
Next, as shown in FIGS. 66 and 67, the polycrystalline silicon film 66n is dry-etched using the photoresist film as a mask, so that the polycrystalline silicon film 66n extends over the active region L along the extending direction. A polycrystalline silicon film 66n having a band-like planar pattern is formed.
Next, as shown in FIGS. 68 and 69, an ONO film 67 made of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the substrate 1 on which the polycrystalline silicon film 66n is formed. The ONO film 67 is used as a second gate insulating film of a MISFET constituting a memory cell. For example, a 5-nm-thick silicon oxide film, a 7-nm-thick silicon nitride film, and a 4-nm-thick oxide film are formed on the substrate 1 by CVD. It is formed by sequentially depositing silicon films.
Next, as shown in FIGS. 70 and 71, an n-type polycrystalline silicon film 14n doped with P (phosphorus) is_XA film 24, a W film 25 and a silicon nitride film 8 are sequentially deposited. Polycrystalline silicon film 14n, W film 25 and silicon nitride film 8 are deposited by the same method as in the first embodiment. Also, WN_XThe film 24 is deposited by the same method as in the second embodiment in order to reduce the contact resistance with the polycrystalline silicon film 14n. That is, WN_XThe film 24 is formed under such conditions that the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more, more preferably 18% or more. In order to make the remaining film thickness at the time of completion of the element at least 1 nm or more,_XIt is desirable that the thickness of the film 24 be in the range of 5 nm to 10 nm. Also, WN_XIn order to reduce the contact resistance between the film 24 and the polycrystalline silicon film 14n, the process described in the third, fourth or fifth embodiment may be employed.
The polycrystalline silicon film 14n is used as a control gate electrode and a word line WL of a MISFET forming a memory cell. The silicon nitride film 8 is used as an insulating film for protecting the upper part of the control gate electrode. The polycrystalline silicon film 14n can also be formed of a silicon film containing about 50% of Ge (germanium) at the maximum.
Next, as shown in FIG. 72, using a photoresist film (not shown) formed on the silicon nitride film 8 as a mask, the silicon nitride film 8, the W film 24, WN_XThe film 25, the polycrystalline silicon film 14n, the ONO film 67, and the polycrystalline silicon film 66n are sequentially dry-etched to form a floating gate electrode 68 made of polycrystalline silicon 66n, the W film 24, WN_XA control gate electrode 69 (word line WL) having a polymetal structure composed of the film 25 and the polycrystalline silicon film 14n is formed.
Next, as shown in FIG. 73, an n-type semiconductor region 70 forming the source and drain of the MISFET is formed. The n-type semiconductor region 70 is formed by implanting an n-type impurity (for example, arsenic (As)) into the p-type well 3 and then heat-treating the substrate 1 at about 900 ° C. to diffuse the n-type impurity into the p-type well 3. To form.
In the steps so far, the gate insulating film 6 in the space region of the gate electrode (the floating gate electrode 68 and the control gate electrode 69) has been damaged by the gate electrode processing step and the impurity ion implantation step. This damage degrades the quality of the gate insulating film 6, such as a path in which electrons injected into the floating gate electrode 68 leak from the end of the floating gate electrode 68 to the substrate 1. Therefore, it is necessary to sufficiently remove the damage. There is.
Therefore, after the gate insulating film 6 is etched using hydrofluoric acid, a re-oxidation process for filling and regenerating the thinned gate insulating film 6 is performed. By performing this reoxidation treatment in the same manner as in the first embodiment, the W film 25 and the WN_XOxidation of the film 24 can be prevented, and oxide contamination on the surface of the substrate 1 can be kept at an extremely low level. By this reoxidation process, as shown in FIG. 74, the space region of the gate electrode (floating gate electrode 68 and control gate electrode 69), that is, the surface of n-type semiconductor region (source, drain) 70 and the side wall of floating gate electrode 68 The gate insulating film 6 is formed again at the lower end.
Next, after cleaning the surface of the substrate 1, a silicon nitride film 11 is deposited on the substrate 1 by a low pressure CVD method as shown in FIG. By performing the cleaning process and the deposition of the silicon nitride film 11 in the same manner as in the first embodiment, the contamination of the substrate 1 by the oxide of W can be kept at an extremely low level.
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
In the above-described embodiment, the case where the present invention is applied to a DRAM, a DRAM-embedded logic LSI, a CMOS logic LSI, and a flash memory has been described. However, the present invention is not limited to these LSIs. Can be widely applied to an LSI having a MISFET formed with.
In addition, since the essence of the invention described in the present application is deeply tied to the polysilicon layer, it can be applied to a non-polysilicon metal gate electrode without a polysilicon layer unless the polysilicon layer is essential. Not even.
Industrial applicability
The present invention can be used, for example, for manufacturing an integrated circuit device having a polymetal gate.
[Brief description of the drawings]
FIG. 1 is an overall plan view of a semiconductor chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed.
FIG. 2 is a plan view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 3 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 5 is a plan view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 7 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 10 is a plan view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 11 is an enlarged sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 12 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 13 is a fragmentary enlarged cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 14 is a schematic view of a batch type vertical oxidation furnace used for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 15 is a schematic diagram showing a catalytic steam / hydrogen mixed gas generator connected to the batch type vertical oxidation furnace shown in FIG.
FIG. 16 is a piping diagram of the steam / hydrogen mixed gas generator shown in FIG.
FIG. 17 shows an equilibrium vapor pressure ratio (P) of an oxidation-reduction reaction using a steam / hydrogen mixed gas._{H 2O}/ P_H23 is a graph showing the temperature dependence of FIG.
FIG. 18 is an explanatory diagram of a reoxidation process sequence using the batch type vertical oxidation furnace shown in FIG.
FIG. 19 is an enlarged cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 20A is a schematic view of a single-wafer oxidation furnace used for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 20B is a view taken along line BB ′ of FIG. It is sectional drawing.
FIG. 21 is a state diagram showing the relationship between the oxidation-reduction potential of tungsten-water system and pH.
FIG. 22 is a graph showing the result of measuring the removal effect of the natural oxide film formed on the surface of the W film by washing with water by total reflection X-ray fluorescence.
FIG. 23 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 24 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 25 is a main-portion cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 27 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 28 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 30 is a cross-sectional view of a principal part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 31 is a plan view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 33 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 35 is a main-portion cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 37 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 38 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 39 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 40 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 41 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 42 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 43 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 44 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 45 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 46 shows a structure of WN forming a part of the gate electrode._XNitrogen flow rate and WN during film formation_X6 is a graph showing the result of examining the relationship with the crystal structure of a film by X-ray diffraction measurement.
FIGS. 47 (a) and (b) show WN films formed by changing the flow rate of nitrogen gas while keeping the flow rate of argon gas constant._X5 is a graph showing the measured film stress when the film is heat-treated at various temperatures.
FIG. 48 shows a WN film formed by changing the flow ratio of nitrogen gas and argon gas._XWithstand voltage of gate electrode including film, and WN_X6 is a graph showing the result of examining the relationship between the contact resistance of the film / polycrystalline silicon film interface.
FIG. 49 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 50 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 51 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 52 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 53 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 54 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 55 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 56 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 57 is a cross-sectional view of a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 58 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 59 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 60 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 61 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 62 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 63 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 64 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 65 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 66 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 67 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 68 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 69 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 70 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 71 is a cross-sectional view of a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 72 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 73 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 74 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 75 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

Claims (57)

Semiconductor integrated circuit device including:
(A) a semiconductor integrated circuit chip having a first main surface;
(B) a silicon-based surface region where silicon on the first main surface is one of the main components;
(C) a gate insulating film on the silicon base surface region;
(D) a silicon base film comprising silicon on the gate insulating film as one of the main components;
(E) a tungsten nitride film provided on the silicon base film, containing W ₂ N, and having a thickness of 1 nm or more and an elemental composition of nitrogen of 7% or more;
(F) A refractory metal film containing tungsten or molybdenum as a main component on the nitride film. 2. The semiconductor integrated circuit device according to claim 1, wherein said nitride film has an elemental composition of nitrogen of 10% or more. 3. The semiconductor integrated circuit device according to claim 2, wherein said nitride film has an elemental composition of nitrogen of 13% or more. 4. The semiconductor integrated circuit device according to claim 3, wherein the nitride film has an elemental composition of nitrogen of 18% or more. 2. The semiconductor integrated circuit device according to claim 1, further comprising:
(G) a tungsten silicide layer provided between the silicon base film and the nitride film. Semiconductor integrated circuit device including:
(A) a semiconductor integrated circuit chip having a first main surface;
(B) a silicon-based surface region where silicon on the first main surface is one of the main components;
(C) a gate insulating film on the silicon base surface region;
(D) a first silicon-based polycrystalline film having silicon on the gate insulating film as one of the main components;
(E) a second silicon-based polycrystalline film provided on the first silicon-based polycrystalline film and having an average crystal grain size smaller than that, and having silicon as one of main components;
(F) a tungsten nitride film provided on the second silicon-based polycrystalline film, containing W ₂ N, and having a thickness of 1 nm or more and an elemental composition of nitrogen of 7% or more;
(G) A refractory metal film containing tungsten or molybdenum as a main component on the nitride film. 7. The semiconductor integrated circuit device according to claim 6, wherein said nitride film has an elemental composition of nitrogen of 10% or more. 8. The semiconductor integrated circuit device according to claim 7, wherein the nitride film has an elemental composition of nitrogen of 13% or more. 9. The semiconductor integrated circuit device according to claim 8, wherein said nitride film has an elemental composition of nitrogen of 18% or more. 7. The semiconductor integrated circuit device according to claim 6, wherein said first silicon-based polycrystalline film partially contains germanium. 7. The semiconductor integrated circuit device according to claim 6, wherein the second silicon-based polycrystalline film contains germanium in a part thereof. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a first silicon-based film having silicon as one of the main components on the gate insulating film;
(C) doping impurities into the first silicon base film by ion implantation;
(D) after the step (c), forming a non-doped second silicon base film containing silicon as one of the main components on the first silicon base film;
(E) forming a tungsten nitride film by sputtering on the second silicon base film so that the nitrogen element composition at the time of device completion is 7% or more;
(F) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film; 13. The method according to claim 12, wherein an impurity concentration of the non-doped second silicon base film at the beginning of formation is less than 1.0 × 10 ¹⁷ cm ³ . 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the non-doped second silicon base film is in an amorphous state or an aggregate of extremely small crystal grains at the beginning of the formation. ^{14. The} method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the non-doped second silicon base film has an impurity concentration of less than 1.0 × 10 ¹⁴ cm ^{3 at the} beginning of formation. 13. The method according to claim 12, wherein the nitride film has an elemental composition of nitrogen of 10% or more. 17. The method according to claim 16, wherein the nitride film has an elemental composition of nitrogen of 13% or more. The method according to claim 17, wherein the nitride film has an elemental composition of nitrogen of 18% or more. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming, on the gate insulating film, a first silicon base film doped with impurities, using silicon as one of main components;
(C) forming a non-doped second silicon-based film having silicon as one of the main components on the first silicon-based film;
(D) forming a tungsten nitride film by sputtering on the second silicon base film such that the nitrogen element composition at the time of device completion is 7% or more;
(E) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film; 20. The method according to claim 19, wherein an impurity concentration of the non-doped second silicon-based film at the beginning of formation is less than 1.0 × 10 ¹⁷ cm ³ . 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the non-doped second silicon base film is in an amorphous state or an aggregate of ultrafine crystal grains at the beginning of the formation. 21. The method according to claim 20, wherein an initial impurity concentration of the non-doped second silicon base film is less than 1.0 * 10 < ¹⁴ > cm < ³ >. 20. The method according to claim 19, wherein the nitride film has a nitrogen element composition of 10% or more when the element is completed. 24. The method according to claim 23, wherein the nitride film has a nitrogen element composition of 13% or more when the element is completed. 25. The method according to claim 24, wherein the nitride film has a nitrogen element composition of 18% or more when the element is completed. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein an impurity concentration of the first silicon base film at the beginning of formation is 1.0 × 10 ¹⁹ cm ³ or more. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a silicon base film having silicon as one of the main components on the gate insulating film;
(C) forming a first refractory metal film containing tungsten as one of the main components on the silicon base film;
(D) forming a nitride film containing a nitride of tungsten on the first refractory metal film;
(E) after the step (c) or (d), doping an impurity into the silicon base film by ion implantation;
(F) forming a second refractory metal film containing tungsten or molybdenum as a main component on the nitride film; 28. The method according to claim 27, further comprising, after the step (f), doping an impurity into the silicon base film by ion implantation. 28. The method according to claim 27, wherein the step (e) is performed before the step (d). 28. The method according to claim 27, wherein the nitride film has a nitrogen element composition of 10% or more when the element is completed. 31. The method for manufacturing a semiconductor integrated circuit device according to claim 30, wherein the nitride film has a nitrogen element composition of 13% or more when the element is completed. The method for manufacturing a semiconductor integrated circuit device according to claim 31, wherein the nitride film has a nitrogen element composition of 18% or more when the element is completed. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a silicon base film having silicon as one of the main components on the gate insulating film;
(C) forming a film containing tungsten silicide as a main component on the silicon base film;
(D) forming a nitride film containing a nitride of tungsten on the first refractory metal film;
(E) forming a second refractory metal film containing tungsten or molybdenum as a main component on the nitride film. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a silicon base film having silicon as one of the main components on the gate insulating film;
(C) forming a nitride film containing a nitride of tungsten on the silicon base film;
(D) after the step (c), doping impurities into the silicon base film by ion implantation;
(E) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film; 35. The method according to claim 34, further comprising, after the step (e), doping an impurity into the silicon base film by ion implantation. 35. The method according to claim 34, wherein the step (d) is performed before the step (c). After the step (b), prior to the step (c), a step of forming a refractory metal film containing tungsten or molybdenum as a main component on the silicon base film is further included. 35. The method for manufacturing a semiconductor integrated circuit device according to item 34. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming a silicon base film having silicon as one of the main components on the gate insulating film;
(C) forming a tungsten nitride film containing a tungsten nitride on the silicon base film;
(D) after the step (c), doping impurities into the silicon base film by ion implantation;
(E) a step of subjecting the tungsten to a heat treatment to change at least an upper half thereof into a film containing tungsten as a main component. After the step (b), prior to the step (c), a step of forming a refractory metal film containing tungsten or molybdenum as a main component on the silicon base film is further included. 39. The method for manufacturing a semiconductor integrated circuit device according to item 38. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming an n-type or p-type silicon-based film having silicon as one of the main components on the gate insulating film;
(C) after the step (b), introducing an impurity of the same conductivity type as an impurity contained in the silicon base film into a surface region of the silicon base film by an ion implantation method;
(D) after the step (c), forming a first refractory metal film containing tungsten as one of the main components on the silicon base film;
(E) forming a nitride film containing a nitride of tungsten on the first refractory metal film;
(F) forming a second refractory metal film containing tungsten or molybdenum as a main component on the nitride film; 41. The method according to claim 40, wherein the impurity concentration of the silicon base film after performing the ion implantation in the step (c) is 5 * 10 < ¹⁹ > atoms / cm < ³ > or more. . The region where the impurity concentration is 5 × 10 ¹⁹ atoms / cm ³ or more is secured in a silicon-based region at least 10 nm or less from an interface with a metal-based conductor layer such as a metal, a metal nitride, or a metal compound. The method for manufacturing a semiconductor integrated circuit device according to claim 41, wherein: The step (b) includes forming a silicon base film containing n-type impurities or p-type impurities using silicon as one of the main components on the gate insulating film, and performing a heat treatment on the silicon base film. 41. The method of manufacturing a semiconductor integrated circuit device according to claim 40, further comprising: electrically activating said n-type impurity or p-type impurity. After the step (b), prior to the step (d), a step of forming a refractory metal film containing tungsten or molybdenum as a main component on the silicon base film is further included. 41. The method for manufacturing a semiconductor integrated circuit device according to item 40. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming an n-type or p-type silicon-based film having silicon as one of the main components on the gate insulating film;
(C) after the step (b), forming a film on the silicon base film containing an impurity of the same conductivity type as an impurity contained in the silicon base film;
(D) heat-treating the film to diffuse the impurities contained in the film into a surface region of the silicon-based film;
(E) removing the film on the silicon base film after the step (d);
(F) after the step (e), forming a first refractory metal film containing tungsten as one of the main components on the silicon base film;
(G) forming a nitride film containing tungsten nitride on the first refractory metal film;
(H) forming a second refractory metal film containing tungsten or molybdenum as a main component on the nitride film; 46. The semiconductor integrated circuit device according to claim 45, wherein the impurity concentration in the surface region of the silicon base film after performing the heat treatment in the step (d) is 5 × 10 ¹⁹ atoms / cm ³ or more. Production method. The surface region having the impurity concentration of 5 × 10 ¹⁹ atoms / cm ³ or more is secured in a silicon base region of at least 10 nm or less from an interface with a metal-based conductor layer of at least a metal, a metal nitride, or a metal compound. The method of manufacturing a semiconductor integrated circuit device according to claim 46, wherein: The step (b) includes forming a silicon base film containing n-type impurities or p-type impurities using silicon as one of the main components on the gate insulating film, and performing a heat treatment on the silicon base film. 47. A method of manufacturing a semiconductor integrated circuit device according to claim 45, further comprising: electrically activating said n-type impurity or p-type impurity. The method according to claim 45, wherein the film is a film containing silicon as a main component. A method for manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a gate insulating film on a silicon base surface region where silicon is one of the main components on the first main surface of the wafer;
(B) forming an n-type conductive silicon-based film having silicon as one of the main components on the gate insulating film;
(C) after the step (b), introducing an n-type impurity into the surface region of the silicon base film by an ion implantation method;
(D) after the step (c), forming a film on the silicon base film;
(E) heat-treating the silicon-based film to segregate the n-type impurities introduced into the surface region of the silicon-based film near an interface with the film;
(F) after the step (e), removing the film on the silicon base film;
(G) after (f), forming a nitride film containing tungsten nitride on the silicon base film;
(H) forming a high melting point metal film containing tungsten or molybdenum as a main component on the nitride film; The method of manufacturing a semiconductor integrated circuit device according to claim 50, wherein the concentration of the n-type impurity segregated in the vicinity of the interface with the silicon oxide film is 5 × 10 ¹⁹ atoms / cm ³ or more. The step (b) includes a step of forming a silicon base film containing n-type impurities on the gate insulating film using silicon as one of the main constituents, and a heat treatment of the silicon base film to form the n-type The method of manufacturing a semiconductor integrated circuit device according to claim 50, further comprising: a step of electrically activating an impurity. After the step (f), prior to the step (g), a step of forming a refractory metal film containing tungsten or molybdenum as a main component on the silicon base film is further included. 50. A method for manufacturing a semiconductor integrated circuit device according to item 50. The method of manufacturing a semiconductor integrated circuit device according to claim 50, wherein the nitride film has a nitrogen element composition of 10% or more when the element is completed. 55. The method according to claim 54, wherein the nitride film has a nitrogen element composition of 13% or more when the element is completed. The method according to claim 55, wherein the nitride film has a nitrogen element composition of 18% or more when the element is completed. The method according to claim 1, wherein the film is a silicon oxide film formed by thermally oxidizing a surface of the silicon base film, or a silicon oxide film deposited on the silicon base film by a chemical vapor deposition method. 50. The method for manufacturing a semiconductor integrated circuit device according to 50.

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