JP2005277427A - Method for producing semiconductor integated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep oxide contamination on the surface of a substrate, after polymetal gate working at a low level. <P>SOLUTION: A gate electrode comprising a tungsten (W) film is formed; then after performing re-oxidation treatment, the oxide contamination in a gate insulating film during ion implantation of impurities is prevented from subjected to knock on, by wet cleaning the surface of a wafer, using water or liquid chemicals which have the property close to the borderline of a W-existing region and negative ions existing region of WO<SB>4</SB>, and exists in a region of reduction potential in a pH range of 6.5 to 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and is particularly effective when applied to the manufacture of a semiconductor integrated circuit device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate electrode including a refractory metal film. Regarding technology.

  As an improved technique for forming a MISFET having a polymetal structure, there is JP-A-11-31666 (Patent Document 1). This gazette is a technology that suppresses the growth of wire thinning and acicular crystals that occur during heat treatment by reducing the natural oxide formed on the tungsten surface once and then performing a desired heat treatment. Disclosure.

  Japanese Patent Application Laid-Open No. 11-26395 (Patent Document 2) discloses a method for reducing the electric field concentration at the end of the gate electrode by making the gate electrode into a W / WSixNy / W0x structure and heat-treating in a reducing atmosphere. In which the bottom end of the gate electrode is rounded.

  Japanese Patent Laid-Open No. 2000-331978 (Patent Document 3) discloses that after processing a gate electrode having a polymetal structure containing W, it is washed with an acidic or alkaline solution substantially free of hydrogen peroxide. Disclosed is a technique for preventing the dissolution of sucrose.

  In addition, regarding polymetal gates or metal gates in general, JP-A-60-89943 (Patent Document 4), JP-A-61-15236 (Patent Document 5), JP-A-60-72229 (Patent Document 4) Document 6), JP 59-10271 (Patent Document 7), JP 56-107552 (Patent Document 8), JP 61-127123 (Patent Document 9), JP 61 JP-A-127124 (Patent Document 10), JP-A-60-123060 (Patent Document 11), JP-A-61-152076 (Patent Document 12), JP-A-61-267365 (Patent Document 13). ), JP-A-1-94657 (Patent Document 14), JP-A-8-264431 (Patent Document 15), JP-A-3-119863 (Patent Document 16), JP-A-7- No. 4716 (Patent Literature 17), US Patent Publication No. USP4505028 (Patent Literature 18), USP5719410 (Patent Literature 19), USP5387540 (Patent Literature 20), IEEE Transaction Electron devices, Vol.43, N0.11, November 1996, Akasaka et al, p.1864-1869, Elsevier, Applied Surface Science 117/118 (1997) 312-316, Nakajima et al, Nakajima et al, Advanced metalization conference, Japan Session, Tokyo Univ. (1995) (non-patent literature) 1) etc.

  In addition, there is USP 4282270 (Patent Document 21) regarding oxynitriding treatment. Further, regarding hydrogen exhaust gas treatment, there are USP5202096 (Patent Document 22), USP5088314 (Patent Document 23), JP-A-8-83772 (Patent Document 24), JP-A-9-75651 (Patent Document 25), and the like. .

  Further, regarding the problem of moisture and oxidation, there are JP-A-7-321102 (Patent Document 26), JP-A-60-107840 (Patent Document 27), US Pat. No. 5,693,578 (Patent Document 28), and the like.

Furthermore, regarding water synthesis using a catalyst, JP-A-6-333918 (Patent Document 29), JP-A-6-115903 (Patent Document 30), JP-A-5-152282 (Patent Document 31), JP-A-6-163871 (Patent Document 32), JP-A-5-141187 (Patent Document 33), JP-A-5-144804 (Patent Document 34), JP-A-6-120206 (Patent Document 35) ), Nakamura et al, Proceedings of the 45 th Symposium on Semiconductors and Integrated circuit Technology, Tokyo Dec.1-2, 1993, the Electronic materials committee, P.128-133 ( non-Patent Document 2), and the like.
JP 11-31666 A Japanese Patent Laid-Open No. 11-26395 JP 2000-331978 A JP 60-89943 A JP-A 61-150236 JP-A-60-72229 JP 59-10271 A JP-A-56-107552 JP 61-127123 A JP 61-127124 A JP 60-123060 A JP 61-152076 A JP-A 61-267365 Japanese Unexamined Patent Publication No. 1-94657 JP-A-8-264531 Japanese Patent Laid-Open No. 3-119963 JP-A-7-94716 USP4505028 USP 5719410 USP 5387540 USP 4282270 USP5202096 USP 5088314 Japanese Patent Laid-Open No. 8-83772 JP-A-9-75651 JP 7-321102 A Japanese Patent Laid-Open No. 60-107840 USP 569578 JP-A-6-333918 JP-A-6-115903 JP-A-5-152282 JP-A-6-163871 Japanese Patent Laid-Open No. 5-141871 JP-A-5-144804 JP-A-6-120206 IEEE Transaction Electron devices, Vol.43, N0.11, November 1996, Akasaka et al, p.1864-1869, Elsevier, Applied Surface Science 117/118 (1997) 312-316, Nakajima et al, Nakajima et al, Advanced metalization conference, Japan Session, Tokyo Univ. (1995) Nakamura et al, Proceedings of the 45th Symposium on Semiconductors and Integrated circuit Technology, Tokyo Dec. 1-2, 1993, the Electronic materials committee, P.128-133

  In a CMOS LSI that forms a circuit with a fine MOSFET having a gate length of 0.18 μm or less, and a DRAM that uses a gate electrode and a gate electrode layer with a width of 0.18 μm or less as wiring, the gate delay is reduced even during low-voltage operation. In order to ensure high-speed operation, it is considered that a gate processing process using a low-resistance conductive material including a metal layer is adopted.

What is regarded as a promising low-resistance gate electrode material is a so-called polymetal in which a refractory metal film is laminated on a polycrystalline silicon film. Polymetal can be used not only as a gate electrode material but also as a wiring material because its sheet resistance is as low as about 2Ω / □. As the refractory metal, W (tungsten), Mo (molybdenum), or the like, which shows good low resistance even at a low temperature process of 800 ° C. or less and has high electromigration resistance, is used. Note that if these refractory metal films are laminated directly on the polycrystalline silicon film, the adhesive strength between the two will decrease, or a high-resistance silicide layer will be formed at the interface between the two due to the high-temperature heat treatment process. The polymetal gate has a three-layer structure in which a barrier layer made of a metal nitride film such as WN _x (tungsten nitride) is interposed between a polycrystalline silicon film and a refractory metal film.

  However, when a gate electrode is formed by etching with a conductive film including a refractory metal film, an undesired oxide is formed on the surface of the refractory metal film exposed on the side wall of the gate electrode. This oxide formed on the side wall of the gate electrode is sublimated in the subsequent heat treatment process and adheres to the silicon or insulating film surface around the electrode, and the sublimated metal oxide adheres to the inner wall of the processing chamber and then again. Sublimation or reattachment to the surface of the substrate from the part in contact with the holding table becomes a contaminant, causing deterioration of the device characteristics.

  An object of the present invention is to provide a technique capable of keeping oxide contamination on a substrate surface after polymetal gate processing at a low level.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method for manufacturing a semiconductor integrated circuit device according to one aspect of the present application includes the following steps.
(A) forming a film pattern including a refractory metal film on the first main surface of the wafer and exposing a side surface of the refractory metal film;
(B) raising the temperature of the first main surface of the wafer on which the film pattern has been formed to a first temperature of 600 degrees Celsius or higher under the condition of reducing the oxide of the refractory metal;
(C) forming an insulating film on the first main surface of the wafer on which the film pattern is formed by chemical vapor deposition at the first temperature;
(D) A second main surface of less than 500 degrees Celsius is formed on the first main surface of the wafer on which the insulating film is formed by the chemical vapor deposition under conditions for reducing oxides of the refractory metal film. The process of cooling to a temperature and switching from a reducing atmosphere to a nitrogen gas atmosphere.

A method for manufacturing a semiconductor integrated circuit device according to another invention of the present application includes the following steps.
(A) forming a film pattern including a refractory metal film on the first main surface of the wafer and exposing a side surface of the refractory metal film;
(B) a step of performing a plasma treatment on the first main surface of the wafer on which the film pattern is formed under a condition for reducing the oxide of the refractory metal;
(C) forming an insulating film on the first main surface of the plasma-treated wafer by plasma chemical vapor deposition;

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  After polymetal gate processing, oxide contamination on the substrate surface can be kept at a low level prior to the ion implantation process, so that the oxide contamination is knocked into the gate insulating film during the ion implantation process, degrading the electrical characteristics of the device It is possible to prevent malfunctions.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), except when explicitly stated and in principle limited to a specific number in principle. It is not limited to the specific number, and may be a specific number or more. Furthermore, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated and clearly considered essential in principle. Yes.

  Similarly, in the following embodiments, when referring to the shapes and positional relationships of components and the like, the shapes and the like of the components are substantially the same unless explicitly stated or otherwise apparent in principle. Including those that are approximate or similar to. The same applies to the above numerical values and ranges.

  Further, a semiconductor integrated circuit wafer or a semiconductor wafer is a silicon single crystal substrate (generally almost circular), a sapphire substrate, a glass substrate or other insulating, anti-insulating or semiconductor substrate used for manufacturing a semiconductor integrated circuit, and a composite thereof. A substrate. In addition, “semiconductor integrated circuit device” (or “electronic device”, “electronic circuit device”, etc.) is not limited to those made on a single crystal silicon substrate, unless specifically stated otherwise. In addition, the above-mentioned various substrates, or those made on other substrates such as SOI (Silicon On Insulator) substrate, TFT (Thin Film Transistor) liquid crystal manufacturing substrate, STN (Super Twisted Nematic) liquid crystal manufacturing substrate, etc. .

  When referring to materials, gas compositions, etc., unless otherwise specified, materials other than pure ones, etc., whose materials are the main components, are indicated and other elements can be added.

  For example, with respect to the gas composition, addition of an additive gas, a dilution gas, an auxiliary gas, or the like that has a secondary effect in addition to the main reaction gas and processing gas is allowed.

  Further, when referring to a silicon oxide film, unless otherwise specified, generally, various silicon oxide films containing various additives and auxiliary components, that is, PSG (Phospho Silicate Glass) film, BPSG (Boro It shall include other single films or composite films such as -Phospho Silicate Glass) film, TEOS (Tetra-Ethoxy Silane) oxide film, silicon oxynitride film.

Furthermore, the term “silicon nitride”, “silicon nitride” or “silicon nitride” includes not only Si ₃ N ₄ but also a nitride of silicon and an insulating film having a similar composition.

  The gate oxide film includes a silicon thermal oxide film, a silicon oxynitride film, other thermal oxide films, a deposited film, and a coating system film. In terms of materials, non-silicon metal oxide other than the silicon oxide film, Insulating nitride such as silicon nitride, or a composite film thereof is included.

  In addition, regarding the material of the conductive region on the substrate surface and the conductive region of the deposited film, the term “silicon” or “silicon base” refers to impurities or impurities in silicon other than relatively pure silicon members, unless otherwise specified. Additives added, conductive members containing silicon as a main component (for example, SiGe alloys containing 50% or more of Ge based silicon alloys, etc., for example, gate polysilicon portions and channel regions) Etc.). They also allow a high resistance at the beginning of formation unless there is a technical contradiction.

  In addition, although the deposited film is amorphous at the beginning of deposition, it may become polycrystalline immediately after the subsequent heat treatment. It may be displayed in a later form. For example, polycrystalline silicon (polysilicon) is in an amorphous state at the beginning of deposition and is changed to polycrystalline silicon by a subsequent heat treatment. However, it goes without saying that polycrystalline silicon can be used from the beginning. The amorphous state at the beginning of deposition has advantages such as prevention of channeling in ion implantation, avoidance of difficulty in workability depending on the shape of agglomerates during dry etching, and low sheet resistance after heat treatment.

  Further, other techniques related to the implementation of the present invention are disclosed in detail in the following applications involving the inventor of the present application. That is, Japanese Patent Application No. 2000-118491, Japanese Patent Application Laid-Open No. 09-172011, Japanese Patent Application Laid-Open No. 10-335652, Japanese Patent Application Laid-Open No. 10-340909, Japanese Patent Application Laid-Open No. 11-330468, Japanese Patent Application Laid-Open No. 10-349285, US Patent No. 6066508, International Publication No. WO98 / 39802, International Publication No. WO97 / 28085, and the like.

(Embodiment 1)
FIG. 1 is an overall plan view of a semiconductor chip 1A on which a DRAM (Dynamic Random Access Memory) of this embodiment is formed. A DRAM having a storage capacity of, for example, 256 Mbit is formed on the main surface of the rectangular semiconductor chip 1A. This DRAM is mainly composed of a storage unit composed of a plurality of memory arrays (MARY) and a peripheral circuit unit PC arranged around them. A plurality of bonding pads BP to which connection terminals such as bonding wires are connected are arranged in one row at the center of the semiconductor chip 1A.

  FIG. 2 is a plan view of a semiconductor substrate showing a part of the memory array (MARY) of the DRAM, and FIG. 3 is a cross-sectional view of a main part of the semiconductor substrate showing the DRAM. 3 is a cross-sectional view taken along the line AA in FIG. 2, the central area is a cross-sectional view taken along the line BB in FIG. 2, and the right area is a peripheral circuit portion (PC). It is sectional drawing which shows a part.

  For example, an element isolation trench 2, a p-type well 3, and an n-type well are formed on the main surface of a semiconductor substrate (hereinafter referred to as a substrate, also referred to as a semiconductor wafer or simply a wafer) 1 made of p-type single crystal silicon. 4 is formed. A p-type well of the memory array includes a plurality of memory cells each including an n-channel type memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qt and an information storage capacitive element C formed thereon. Is formed.

The memory cell selecting MISFET Qt is mainly composed of a gate insulating film 6, a gate electrode 7A constituting a word line WL in a region other than the active region L, and a pair of n-type semiconductor regions (source, drain) 9, 9. The gate electrode 7A (word line WL) has a so-called polymetal structure in which, for example, a WN _x (tungsten nitride) film and a W film are stacked on top of an n-type polycrystalline silicon film doped with P (phosphorus). It is comprised by the electrically conductive film.

The peripheral circuit portion PC of the DRAM is constituted by a so-called complementary MIS circuit in which a plurality of n-channel type MISFETs Qn and a plurality of p-channel type MISFETs Qp are combined. The n-channel type MISFET Qn is formed in the p-type well 3 and is mainly composed of a gate insulating film 6, a gate electrode 7B, and a pair of n ⁺ -type semiconductor regions (source and drain) 12 and 12. The p-channel type MISFET Qp is formed in the n-type well 4 and is mainly composed of a gate insulating film 6, a gate electrode 7C, and a pair of p ⁺ -type semiconductor regions (source, drain) 13 and 13. The gate electrodes 7B and 7C are composed of a conductive film having the same polymetal structure as the gate electrode 7A (word line WL) of the memory cell selecting MISFET Qt. Sidewall spacers 11s made of a silicon nitride film are formed on the side walls of the gate electrodes 7B and 7C.

  Over the memory cell selection MISFET Qt, n-channel type MISFET Qn, and p-channel type MISFET Qp, a silicon nitride film 11 and an interlayer insulating film 15 are formed to cover the top and side walls of the gate electrode 7A (word line WL). The interlayer insulating film 15 is composed of, for example, a spin on glass film (a silicon oxide insulating film formed by a coating method) and a two-layered silicon oxide film formed thereon.

  Contact holes 16 formed by opening an interlayer insulating film 15 and a silicon nitride film 11 therebelow above the pair of n-type semiconductor regions 9 and 9 constituting the source and drain of the memory cell selection MISFET Qt, 17 is formed. In these contact holes 16 and 17, a plug 18 made of, for example, an n-type polycrystalline silicon film doped with P (phosphorus) is buried.

  A silicon oxide film 19 is formed on the interlayer insulating film 15, and a through hole 20 is formed in the silicon oxide film 19 on one of the pair of contact holes 16 and 17 (contact hole 16). Yes. The through hole 20 is disposed above the element isolation trench 2 that is out of the active region L. The through hole 20 is formed by, for example, a two-layer conductive film in which a W film is stacked on a TiN (titanium nitride) film. Plug 23 is embedded. The plug 23 embedded in the through hole 20 is one of the source and drain of the memory cell selection MISFET Qt (shared by the two memory cell selection MISFETs Qt) via the plug 18 embedded in the contact hole 16 therebelow. It is electrically connected to the n-type semiconductor region 9).

Contact holes 21 and 22 are formed in the silicon oxide film 19 in the peripheral circuit portion and the interlayer insulating film 15 therebelow. The contact hole 21 is formed above a pair of n ⁺ type semiconductor regions (source and drain) 12 and 12 constituting the source and drain of the n-channel type MISFET Qn, and the contact hole 22 is formed of the source and drain of the p-channel type MISFET Qp. Are formed above the pair of p ⁺ type semiconductor regions (source, drain) 13, 13. Plugs 23 made of the same conductive material as the plugs 23 embedded in the through holes 20 of the memory array are embedded in the contact holes 21 and 22.

A plurality of bit lines BL for reading data of memory cells are formed on the silicon oxide film 19 of the memory array. These bit lines BL are arranged above the element isolation trench 2 and extend in the direction orthogonal to the gate electrode 7A (word line WL) with the same width and the same interval. Each of the bit lines BL is formed on the silicon oxide film 19 below the bit line BL, and is connected to one of the source and drain of the memory cell selection MISFET Qt via the plug 23 in the through hole 20 and the plug 18 in the contact hole 16 below the bit line BL. It is electrically connected to the n-type semiconductor region 9). For example, the bit line BL is formed of a conductive film in which a W film is stacked on a WN _X film.

First-layer wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit portion PC. These wirings 30 to 33 are made of the same conductive film as the bit line BL, and are formed simultaneously with the bit line BL as will be described later. The wirings 30 and 31 are electrically connected to the source and drain (n ⁺ type semiconductor region 12) of the n-channel type MISFET Qn through the plugs 23 in the contact holes 21 formed in the silicon oxide films 19 and 15, 32 and 33 are electrically connected to the source and drain (p ⁺ type semiconductor region 13) of the p-channel type MISFET Qp through the plug 23 in the contact hole 22 formed in the silicon oxide films 19 and 15.

  An interlayer insulating film 40 is formed above the bit line BL and the first layer wirings 30 to 33. Similar to the lower interlayer insulating film 15, the interlayer insulating film 40 is composed of a spin-on-glass film and a two-layered silicon oxide film formed on the spin-on glass film. It is flattened so that it will be.

  Through holes 43 are formed in the interlayer insulating film 40 of the memory array and the underlying silicon oxide film 19. The through-hole 43 is disposed immediately above the contact hole 17 below, and a plug 44 made of, for example, an n-type polycrystalline silicon film doped with P (phosphorus) is buried therein. Yes.

A silicon nitride film 45 and a thick silicon oxide film 46 are formed on the interlayer insulating film 40, and a lower electrode 48 is formed inside the deep groove 47 formed in the silicon oxide film 46 of the memory array. An information storage capacitive element C constituted by the capacitive insulating film 49 and the upper electrode 50 is formed. The lower electrode 48 of the information storage capacitive element C is formed of, for example, a low-resistance n-type polycrystalline silicon film doped with P (phosphorus), and the memory is formed through the through-hole 43 and the contact hole 17 formed thereunder. The n-type semiconductor region (source, drain) 9 of the cell selection MISFET Qt is electrically connected to the other. Further, the capacitive insulating film 49 of the information storage capacitive element C is made of, for example, a Ta ₂ O ₅ (tantalum oxide) film, and the upper electrode 50 is made of, for example, a TiN film.

  A silicon oxide film 51 is formed on the information storage capacitor C, and about two layers of Al wirings are formed on the silicon oxide film 51, but these are not shown.

  Next, an example of a manufacturing method of the DRAM of the present embodiment configured as described above will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 4, a substrate (wafer) 1 made of, for example, p-type single crystal silicon is prepared, an element isolation groove 2 is formed on the main surface thereof, and then B (boron) is partially formed on the substrate 1. Then, after P (phosphorus) is ion-implanted into other parts, the substrate 1 is heat-treated at about 950 ° C. for about 10 minutes to diffuse these impurities, thereby forming the p-type well 3 and the n-type well 4. Form. In order to form the element isolation groove 2, for example, an element isolation region of the substrate 1 is etched to form a groove having a depth of about 350 nm, and then the inside of the groove and on the substrate 1 are formed by a CVD (Chemical Vapor Deposition) method. After the silicon oxide film 5 is deposited, the unnecessary silicon oxide film 5 outside the trench is removed by a chemical mechanical polishing (CMP) method. As shown in FIG. 5, by forming the element isolation grooves 4, a plurality of active regions L having a long and narrow island pattern surrounded by the element isolation grooves 2 are formed on the substrate 1 of the memory array. Is done.

  Next, after cleaning the surface of the substrate 1 with hydrofluoric acid, the surface of the p-type well 3 and the surface of the n-type well 4 are made of a silicon oxide film by subjecting the substrate 1 to steam oxidation as shown in FIG. A clean gate insulating film 6 is formed. The film thickness of the gate insulating film 6 is, for example, 6 nm. The gate insulating film 6 may be formed of a silicon oxynitride film, a silicon nitride film, a composite insulating film of a silicon oxide film and a silicon nitride film, or the like instead of the silicon oxide film.

Next, as shown in FIG. 7, an n-type polycrystalline silicon film 14 n doped with P (phosphorus) is deposited on the gate insulating film 6. The polycrystalline silicon film 14n is deposited by a CVD method using, for example, monosilane (SiH ₄ ) and phosphine (PH ₃ ) as a source gas (film formation temperature = about 630 ° C.), and the film thickness is set to about 70 nm. The polycrystalline silicon film 14n has a P concentration of 1.0 × 10 ¹⁹ cm ³ or more in order to reduce electric resistance.

Further, instead of the polycrystalline silicon film 14n, a silicon film containing Ge (germanium) from about 5% to about 50% at the maximum can be used. When Ge is contained in silicon, there is an advantage that the contact resistance with the upper WN _x film is reduced due to the narrow band gap of silicon and the increase of the solid solution limit of impurities. . In order to contain Ge in silicon, there is a method of depositing a silicon film containing Ge by a CVD method using monosilane (SiH ₄ ) and GeH ₄ in addition to a method of introducing Ge into the silicon film by ion implantation. .

Next, after cleaning the surface of the polycrystalline silicon film 14n with hydrofluoric acid, as shown in FIG. 8, a WN _x film 24 having a thickness of about 7 nm and a thickness of about 70 nm are formed on the polycrystalline silicon film 14n by sputtering. A silicon nitride film 8 having a thickness of about 160 nm is deposited on the W film 25 by a CVD method. The WN _x film 24 functions as a barrier layer that prevents the reaction between the polycrystalline silicon film 14 n and the W film 25. When the silicon nitride film 8 is deposited, about 10 nm is formed on the W film 25 using a plasma CVD method that can be formed at a relatively low temperature (around 480 ° C.) in order to suppress oxidation of the surface of the W film 25. A thin silicon nitride film is deposited, and then lamp annealing is performed at about 950 ° C. for about 10 seconds to remove gas components in the silicon nitride film. A silicon nitride film with a thickness of about 150 nm may be deposited using a film temperature of around 780 ° C. Alternatively, a silicon oxide film may be deposited on the W film 25 using a plasma CVD method, and then the silicon nitride film 8 may be deposited on the upper portion using a low pressure CVD method.

Next, as shown in FIG. 9, the silicon nitride film 8, the W film 24, the WN _x film 25, and the polycrystalline silicon film 14n are sequentially dry etched using the photoresist film 26 formed on the silicon nitride film 8 as a mask. Thus, the gate electrode 7A (word line WL) is formed on the gate insulating film 6 of the memory array, and the gate electrodes 7B and 7C are formed on the gate insulating film 6 of the peripheral circuit portion. As shown in FIG. 10, the gate electrode 7 </ b> A (word line WL) is formed to extend in a direction orthogonal to the long side of the active region L. The line width (gate length) of the gate electrode 7A (word line WL) and the distance from the adjacent gate electrode 7A (word line WL) are, for example, 0.13 to 0.14 μm.

  Thus, by using a polymetal structure in which part of the conductive material constituting the gate electrode 7A (word line WL) and the gate electrodes 7B and 7C is made of a low-resistance metal (W), the sheet resistance is 2Ω / □. Since the gate delay is suppressed to a degree or less and the gate delay is suppressed, a DRAM operating at high speed can be realized.

  In the dry etching process for forming the gate electrodes 7A (word lines WL), 7B, and 7C, as shown in FIG. 11, the substrate 1 around the gate electrodes 7A (word lines WL), 7B, and 7C is formed. It is desirable to leave the gate insulating film 6 thin (for example, about 3 nm) on the surface. When the substrate 1 under the gate insulating film 6 is exposed by this dry etching, contamination (contaminant) containing W which is a part of the gate electrode material adheres directly to the surface of the substrate 1 in a later heat treatment process. There is a possibility that a reaction product such as W silicide, which is difficult to be removed by a normal cleaning process, is generated.

Next, the substrate 1 is transferred from the dry etching apparatus to the ashing apparatus, and as shown in FIG. 12, the photoresist film 26 is removed by ashing using O ₂ plasma.

When the substrate 1 is transported from the dry etching apparatus to the ashing apparatus, the surface of the substrate 1 is exposed to the atmosphere in the process. Further, when the photoresist film 26 is removed by ashing using O ₂ plasma, the surface of the substrate 1 is exposed to the O ₂ plasma atmosphere. Therefore, when the above ashing is completed, an undesired oxide (WO _x ) 27 is formed on the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C, as shown in FIG. The oxide 27 is sublimated in the subsequent heat treatment process, adheres to the inner wall of the heat treatment chamber, etc., and then reattaches to the surface of the substrate 1 to become a contaminant, deteriorating device characteristics (in the case of DRAM, a refresh failure). Etc.).

  As described above, in the dry etching process for forming the gate electrodes 7A, 7B, and 7C, the gate insulating films 6 in the lower portions of the side walls and in the peripheral regions of the gate electrodes 7A, 7B, and 7C are also cut to some extent, Since the thickness is reduced (see FIG. 13), problems such as a decrease in the gate breakdown voltage occur. Therefore, in order to compensate and regenerate the thinned gate insulating film 6, a re-oxidation process is performed by the following method.

  FIG. 14 is a schematic view showing an example of a batch type vertical oxidation furnace used for the re-oxidation treatment of the gate insulating film 6. The vertical oxidation furnace 150 includes a chamber 151 formed of a quartz tube, and a heater 152 for heating the wafer (substrate) 1 is installed around the chamber 151. A quartz boat 153 that holds a plurality of wafers 1 horizontally is installed inside the chamber 151. Further, a gas introduction pipe 154 for introducing a steam / hydrogen mixed gas and a purge gas and an exhaust pipe 155 for discharging these gases are connected to the bottom of the chamber 151. A gas generation device 140 as shown in FIGS. 15 and 16 is connected to the other end of the gas introduction pipe 154.

  FIG. 15 is a schematic view showing a catalytic steam / hydrogen mixed gas generating apparatus connected to the batch type vertical oxidation furnace 150, and FIG. 16 is a piping system diagram of the gas generating apparatus. The gas generator 140 includes a reactor 141 made of a heat-resistant and corrosion-resistant alloy, and a coil 142 made of a catalytic metal such as Pt (platinum), Ni (nickel), or Pd (palladium) is included in the reactor 141. A heater 143 for heating 142 is installed. A process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen are introduced into the reactor 141 from a gas storage tank 144a, 144b, 144c through a pipe 145. Between the gas storage tanks 144a, 144b, 144c and the pipe 145, mass flow controllers 146a, 146b, 146c for adjusting the amount of gas and open / close valves 147a, 147b, 147c for opening and closing the gas flow path are installed. Thus, the amount of gas introduced into the reactor 141 and the component ratio are precisely controlled by these.

The process gas (hydrogen and oxygen) introduced into the reactor 141 is excited in contact with the coil 142 heated to about 350 to 450 ° C., and hydrogen radicals are generated from hydrogen molecules (H ₂ → 2H). *) Oxygen radicals are generated from oxygen molecules (O ₂ → 2O *). Since these two radicals are chemically very active, they react rapidly to produce water (2H * + O * → H ₂ O). Therefore, a steam / hydrogen mixed gas can be obtained by introducing a process gas containing hydrogen in excess of the molar ratio (hydrogen: oxygen = 2: 1) generated by water (steam) into the reactor 141. it can. This mixed gas is mixed with hydrogen supplied from the dilution line 148 shown in FIG. 16 and adjusted to a steam / hydrogen mixed gas having a desired moisture concentration, and then passes through the gas introduction pipe 154 to a vertical oxidation furnace. 150 chambers 151 are introduced.

  The catalyst-type gas generator 140 as described above can control the amount of hydrogen and oxygen involved in the generation of water and the ratio thereof with high accuracy, so that the water vapor in the water vapor / hydrogen mixed gas introduced into the chamber 151 can be controlled. The concentration can be controlled over a wide range and with high accuracy from a very low concentration of the order of ppm to a high concentration of about several tens of percent. Further, when process gas is introduced into the reactor 141, water is instantly generated, so that a water vapor / hydrogen mixed gas having a desired water vapor concentration can be obtained in real time. This also minimizes contamination by foreign matter, so that a clean steam / hydrogen mixed gas can be introduced into the chamber 151. Note that the catalyst metal in the reactor 141 is not limited to the metals described above as long as hydrogen and oxygen can be radicalized. Further, the catalyst metal may be processed into a coil shape and used, for example, processed into a hollow tube or a fine fiber filter, and the process gas may be passed through the inside.

FIG. 17 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio (P _H2O / P _H2 ) of the oxidation-reduction reaction using a steam / hydrogen mixed gas, and the curves (a) to (e) in the figure are respectively The equilibrium vapor pressure ratios of W, Mo, Ta (tantalum), Si, and Ti (titanium) are shown. As shown in the figure, the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 151 of the vertical oxidation furnace 150 is set within a range between the curves (a) and (d). Accordingly, the gate electrode 7A, 7B, the W film 25 and WN _X film 24 constituting 7C without oxidation, it is possible to selectively oxidize a substrate 1 made of silicon. Further, as shown in the drawing, the oxidation rate of both metals (W, Mo, Ta, Ti) and silicon increases as the water vapor concentration in the water vapor / hydrogen mixed gas increases. Accordingly, by increasing the water vapor concentration in the water vapor / hydrogen mixed gas introduced into the chamber 151, silicon can be selectively oxidized in a shorter heat treatment. When the metal portions of the gate electrodes 7A, 7B, and 7C are made of Mo (molybdenum), the water vapor / hydrogen partial pressure ratio is set within a range between the curves (b) and (d). As a result, only silicon can be selectively oxidized without oxidizing the Mo film.

  Next, an example of a reoxidation process sequence using the batch type vertical oxidation furnace 150 will be described with reference to FIG.

  First, a quartz boat 153 holding a plurality of wafers 1 is loaded into a chamber 151 filled with purge gas (nitrogen). The time required for loading the quartz boat 153 is about 10 minutes. At this time, the purge gas (nitrogen) in the chamber 151 is preheated in advance in order to shorten the heating time of the wafer 1. However, since the oxide 27 formed on the side walls of the gate electrodes 7A, 7B, and 7C easily sublimes at high temperatures, the upper limit of the preheating temperature should be less than 500 ° C.

  Next, hydrogen gas is introduced into the chamber 151 through the gas introduction pipe 154 for about 10 minutes, and the gas in the chamber 151 is replaced, whereby the atmosphere in the chamber 151 is reduced to the W oxide 27. Then, while supplying hydrogen gas into the chamber 151, the wafer 1 is heated to a temperature of 600 ° C. or higher, for example, 800 ° C. over about 30 to 40 minutes. In order to introduce only hydrogen gas into the chamber 151, it is only necessary to shut off the supply of oxygen before the reactor 141 and supply only hydrogen.

  Thus, by heating the wafer 1 under conditions where the oxide 27 on the side walls of the gate electrodes 7A, 7B, and 7C is reduced, most of the oxide 27 is reduced to W, so that the chamber 151 It is possible to keep the amount of the oxide 27 sublimated in the inside at a very low level. Thereby, the contamination of the substrate 1 in the re-oxidation treatment process of the gate insulating film 6 can be kept at a very low level, so that the reliability and manufacturing yield of the DRAM are improved.

  Next, oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a steam / hydrogen mixed gas containing about 10% of water generated from oxygen and hydrogen by a catalytic action in a partial pressure ratio is chamber 151. To introduce. Then, the temperature of the steam / hydrogen mixed gas in the chamber 151 is kept at 800 ° C., the atmospheric pressure is normal pressure, or a subatmospheric reduced pressure region (Subatmospheric region) that is a reduced pressure region of about 10% to 50% of atmospheric pressure, The surface of the wafer 1 is oxidized over 25 to 30 minutes. Depending on the type of the oxidation furnace, oxidation may be performed in a lower pressure reduction region. However, when the pressure during the oxidation is low, the oxide 27 remaining on the side walls of the gate electrodes 7A, 7B, and 7C is sublimated. It becomes easy. Therefore, it is desirable that the pressure during the oxidation treatment is at least about 1300 Pa or more.

By performing the oxidation treatment as described above, as shown in FIG. 19, the substrate 1 around the gate electrodes 7A, 7B, and 7C is reoxidized. Therefore, the gate insulating film thinned by the above-described dry etching process The film thickness of 6 is approximately the same as the initial film thickness (6 nm). Further, in this oxidation treatment, the water vapor / hydrogen partial pressure ratio of the water vapor / hydrogen mixed gas introduced into the chamber 151 is within the range between the curves (a) and (d) shown in FIG. Since the setting is performed, the W film 25 and the WN _x film 24 constituting the gate electrodes 7A, 7B, and 7C are not oxidized.

  Next, by shutting off the supply of oxygen before the reactor 141, while supplying only hydrogen into the chamber 151, the wafer 1 is heated to a temperature below 500 ° C., for example, 400 ° C. over about 30 to 40 minutes. Lower the temperature. Subsequently, the supply of hydrogen gas is stopped, nitrogen gas is introduced into the chamber 151 for about 10 minutes to perform gas replacement, and then the quartz boat 153 is unloaded from the chamber 151. When the temperature at which the inside of the chamber 151 is switched from the hydrogen gas atmosphere to the nitrogen gas atmosphere is high, the W film 25 on the side walls of the gate electrodes 7A, 7B, and 7C and the oxide 27 remaining without reduction may be sublimated. There is. Therefore, it is better to replace the hydrogen gas with the nitrogen gas after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. Further, when the requirement for the time required for the oxidation treatment is not relatively strict, it is preferable to switch to the nitrogen gas atmosphere after the temperature of the wafer 1 is lowered to about 100 ° C., more preferably from 70 ° C. to room temperature. Needless to say, the oxidation of the W film 25 can be suppressed.

  The above-described re-oxidation treatment of the gate insulating film 6 can also be performed using a single wafer oxidation furnace employing an RTA (Rapid Thermal Annealing) method. FIG. 20A is a schematic view showing an example of a single wafer oxidation furnace used for the reoxidation treatment, and FIG. 20B is a cross-sectional view taken along the line B-B ′ of FIG.

  This single wafer oxidation furnace 100 includes a chamber 101 composed of a multi-walled quartz tube, and a halogen lamp 107 for heating the wafer 1 is installed below the chamber 101. Housed in the chamber 101 is a disc-shaped heat equalizing ring 103 that uniformly distributes the heat supplied from the halogen lamp 107 over the entire surface of the wafer 1, and a susceptor 104 that holds the wafer 1 horizontally is mounted on the ring 101. Is placed. The soaking ring 103 is made of a heat-resistant material such as quartz or SiC (silicon carbide), and is supported by a support arm 105 extending from the wall surface of the chamber 101. A thermocouple 106 that measures the temperature of the wafer 1 held by the susceptor 104 is installed in the vicinity of the soaking ring 103.

  One end of a gas introduction pipe 108 for introducing a steam / hydrogen mixed gas and a purge gas into the chamber 101 is connected to a part of the wall surface of the chamber 101. The other end of the gas introduction pipe 108 is connected to the catalyst type gas generator 140 shown in FIGS. 15 and 16. A partition wall 110 having a large number of through holes 109 is provided in the vicinity of the gas introduction pipe 108, and the gas introduced into the chamber 101 passes through the through holes 109 of the partition wall 110 and enters the chamber 101. Spread evenly. One end of an exhaust pipe 111 for discharging the gas introduced into the chamber 101 is connected to the other part of the wall surface of the chamber 101.

  The reoxidation process using the single wafer oxidation furnace 100 is substantially the same as the reoxidation process using the batch type vertical oxidation furnace 150 except that the wafers 1 are oxidized one by one. However, since the temperature raising / lowering of the wafer 1 by lamp heating is performed in a very short time (usually about several seconds), the loading / unloading of the wafer 1 is performed at room temperature.

  An example of the re-oxidation process using the single-wafer oxidation furnace 100 as described above will be described. First, the chamber 101 previously filled with a purge gas (nitrogen) at room temperature is opened, and the gate electrodes 7A, 7B, and 7C are processed. Then, the wafer 1 is loaded on the susceptor 104. Next, after the chamber 101 is closed and hydrogen gas is introduced to make the inside of the chamber 101 a hydrogen gas atmosphere, the wafer 1 is raised to a temperature of 600 ° C. or higher, for example, 950 ° C. over about 5 seconds while maintaining this atmosphere. Warm up.

  Next, oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and a water vapor / hydrogen mixed gas containing about 10% of water generated by the catalytic action in a partial pressure ratio is introduced into the chamber 101. Then, the halogen lamp 107 is turned on, and the surface of the wafer 1 is oxidized over about 3 minutes while maintaining the temperature of the steam / hydrogen mixed gas in the chamber 101 at 950 ° C.

  Next, the halogen lamp 107 is turned off, the supply of the water vapor / hydrogen mixed gas is stopped, the inside of the chamber 101 is made a hydrogen atmosphere again, and the temperature of the wafer 1 is kept below 500 ° C. for about 10 seconds while maintaining this atmosphere. For example, the temperature is lowered to 400 ° C. Next, after the supply of hydrogen gas is stopped and nitrogen gas is introduced into the chamber 101 to perform gas replacement, the wafer 1 is unloaded when the temperature in the chamber 101 falls to about room temperature. Also in this case, the replacement of the hydrogen gas with the nitrogen gas is preferably performed after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. Further, when the requirement for the time required for the oxidation treatment is not relatively strict, it is preferable to switch to the nitrogen gas atmosphere after the temperature of the wafer 1 is lowered to about 100 ° C., more preferably from 70 ° C. to room temperature. Needless to say, the oxidation of the W film 25 can be suppressed.

By performing the re-oxidation process as described above, the W film 25 and the WN _x film 24 constituting the gate electrodes 7A, 7B, and 7C are oxidized as in the re-oxidation process using the batch type vertical oxidation furnace 150. The gate insulating film 6 can be made thicker. Further, by raising and lowering the temperature of the wafer 1 under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, and 7C is reduced, the amount of the oxide 27 sublimated in the chamber 151 can be kept at a very low level. Therefore, the contamination of the substrate 1 in the process of reoxidizing the gate insulating film 6 can be kept at an extremely low level. According to the experiments of the present inventors, even when the batch type vertical oxidation furnace 150 or the single wafer oxidation furnace 100 is used, the temperature rise to a desired temperature and the subsequent temperature fall are reduced. It was confirmed that the amount of the oxide 27 adhering to the surface of the substrate 1 is reduced by about two to three orders of magnitude in comparison with the case of raising and lowering the temperature in a nitrogen atmosphere.

In the above-described reoxidation process, the temperature of the wafer 1 is raised and lowered in a hydrogen atmosphere, but other gases that can reduce the oxide of W, such as ammonia (NH ₃ ), CO, N ₂ O, etc. The gas atmosphere may be used. However, when these gases are used, it is necessary to increase the piping system of the oxidation furnace. In addition to nitrogen, a rare gas such as argon (Ar), helium (He), or xenon (Xe) can also be used as the purge gas.

In the above-described reoxidation process, the wafer 1 is oxidized using the water vapor / hydrogen mixed gas. However, another gas capable of oxidizing silicon without oxidizing the W film or the Mo film, for example, oxygen (O _2). ), Oxidizing gas such as NO, CO, CO _2, or a gas obtained by mixing these oxidizing gas and water vapor / hydrogen mixed gas may be used. However, since CO and CO ₂ may react with W and Mo during the heat treatment to generate foreign substances such as carbide, it is necessary to pay attention to this point.

  According to the above re-oxidation process, the oxide contamination on the surface of the substrate 1 is kept at a very low level, so that the substrate is heated as compared with the case where the temperature is raised to a desired temperature and the temperature is lowered thereafter in a nitrogen atmosphere. The amount of oxide 27 adhering to the surface of 1 could be reduced by 2 to 3 digits.

  However, even if the temperature of the wafer 1 is raised and lowered in the reducing atmosphere in the above-described reoxidation process, slight oxide contamination may adhere during the reoxidation process. In this case, oxide contamination may be knocked on in the gate insulating film 6 at the time of ion implantation of impurities, which is the next step, and there is a possibility that the electrical characteristics of the device will be deteriorated.

  Therefore, it is effective to wet-clean the surface of the substrate (wafer) 1 before proceeding to the next ion implantation step to further reduce the level of oxide contamination. However, the cleaning here needs to be performed under the condition that the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C is not oxidized. In particular, since the surface of the W film 25 exposed to the reducing atmosphere in the reoxidation process is more active than the normal W film and the surface area is increased by the reduction of the oxide 27, the reoxidation is performed. It is more easily oxidized than the W film 25 before the process.

Therefore, the use of an oxidizing solution must be avoided also in this cleaning step. That is, it is desirable that the W oxide present on the surface of the W film 25 exposed on the side walls of the gate electrodes 7A, 7B, and 7C can be removed at the same time by washing with a reducing solution. In order to realize this condition, the present inventors have made the oxidation-reduction potential and pH state diagram of the tungsten-water system shown in FIG. 21 (this state diagram shows Emil A. Knee, Chilkunda Raghunath, Srini Raghavan and Joong S. Jeon : Electrochmistry of Chemical Vapor Deposited Tungsten Films with Relevance to Chemical Mechanical Polishing, J. Electrochem. Soc., Vol. 143, No. 12, pp. 4095-4100, December, 1996) It was found that it is desirable to use water having properties in the vicinity of the boundary between the negative ion existing region of WO ₄ and WO ₄ .

As a result of the experiment, by using such water, the W oxide (WO _x ) present on the surface of the W film is eluted into the water as negative ions of WO ₄ , and then the surface of the W film is almost oxidized. There wasn't. Moreover, such a desirable effect can be obtained by using substantially neutral or weakly alkaline pure water or a chemical solution in the range of pH 6.5 or more and less than 12, more preferably pH 7 or more and less than 10.5. Was the case. In addition, the oxide contamination could be removed by about three orders of magnitude only by washing with ultrapure water. In addition, when cleaning with hydrogen-containing water obtained by adding about 0.2 mg / l to about 2 mg / l of hydrogen gas to the ultrapure water, the removal rate of oxide contamination is 1 as compared with the case of using pure water. It was able to increase about 5 times.

In order to increase the elution efficiency of oxide contamination, an aqueous solution made weakly alkaline by adding ammonia to the above-described ultrapure water or hydrogen-containing water may be used. As a result of the experiment, by adding 0.2 to 120 mmol of ammonia to water, the pH can be reduced to 11.5 and the redox potential can be reduced to 580 mV to 870 mV, thereby oxidizing the W film. The W oxide that had been formed on the surface without elution could be removed by elution into water. This result shows that WO _X adhering to the silicon oxide film around the gate electrode can be eluted and removed. Thereby, the amount of W oxide sublimation in the next heat treatment step can be reduced, and contamination of the LSI can be suppressed.

  It is preferable to use the water or chemical solution described above that does not substantially contain hydrogen peroxide that easily oxidizes the W film. In addition, even if it contains a small amount of hydrogen peroxide, when hydrogen peroxide with a concentration of 30% by weight is taken as 100%, hydrogen peroxide does not contain 0.3% or more by volume. Should be used.

Further, when cleaning the wafer 1 using the above-described water or chemical solution, the removal efficiency of contamination can be further enhanced by applying mechanical vibration such as ultrasonic waves. Further, in order to prevent the removed contamination from adhering again, it is better to perform the washing in a flowing water state rather than a static water state. When washed with running water, the electrical double layer that can be water -SiO ₂ interface, the effect of removing attached WO _X by an interfacial electrokinetic potential of the streaming water (Tsueta (zeta) potential), the contamination reduction effect is increased Conceivable.

  As described above, since the W film exposed to the reducing atmosphere in the reoxidation process is more easily oxidized than the normal W film, the above cleaning should be performed immediately after the reoxidation treatment. In this case, it is also effective to take measures to prevent oxidation due to contact with the air being conveyed, such as by directly connecting the oxidation furnace and the cleaning device.

  FIG. 22 is a graph showing the results of measuring the removal effect of the natural oxide film formed on the surface of the W film by washing with total reflection X-ray fluorescence. As the W film, one formed at room temperature and one formed at 500 ° C. were used. The W film formed at 500 ° C. is characterized in that a natural oxide film is difficult to form because the film has higher crystallinity than the W film formed at room temperature. In any case, the natural oxide film increases as the water temperature rises from room temperature. However, when the temperature exceeds about 60 ° C., the detergency is higher than the increase in the natural oxide film, so that the removal effect is enhanced. Results were obtained. From this, the natural oxide film can be formed by setting the temperature of water or chemicals during cleaning to room temperature to less than 50 degrees Celsius, or 70 degrees Celsius or more, more preferably from room temperature to less than 45 degrees Celsius, or 75 degrees Celsius or more. It can be removed efficiently.

Next, as shown in FIG. 23, the upper portion of the p-type well 3 is covered with a photoresist film 28, and B (boron) is ion-implanted into the n-type well 4. Subsequently, after removing the photoresist film 28 by ashing, as shown in FIG. 24, the upper portion of the n-type well 4 is covered with a photoresist film 29, and As (arsenic) is ion-implanted into the p-type well 3. The dose amount of B and As is, for example, 3 × 10 ¹³ atoms / cm ² .

  Next, after removing the photoresist film 29 by ashing, the surface of the substrate 1 is wet-cleaned in order to remove the ashing residue adhering to the surface of the substrate 1. Since this wet cleaning needs to be performed under the condition that the W film (25) exposed on the side walls of the gate electrodes 7A, 7B, and 7C is not oxidized, the pure water or the chemical solution used in the cleaning step immediately after the re-oxidation process is used. To do.

Next, the substrate 1 is heat-treated for about 10 seconds by lamp annealing in a nitrogen gas atmosphere at about 950 ° C., and the impurities are electrically activated, whereby both sides of the gate electrodes 7A and 7B are obtained as shown in FIG. An n ⁻ type semiconductor region 9 is formed in the p type well 3 and a p ⁻ type semiconductor region 10 is formed in the n type well 4 on both sides of the gate electrode 7C. Thereafter, the surface of the substrate 1 is sublimated from the side walls of the gate electrodes 7A, 7B, and 7C by the heat treatment for activating the impurities, and the surface of the substrate 1 is removed for the purpose of removing a very small amount of oxide contamination reattached to the surface of the substrate 1. You may wash. For this cleaning, it is desirable to use the pure water or chemical used in the cleaning step immediately after the reoxidation process.

Next, as shown in FIG. 26, a silicon nitride film 11 having a thickness of about 50 nm is deposited on the substrate 1. The silicon nitride film 11 is deposited by a low pressure CVD method using, for example, monosilane (SiH ₄ ) and ammonia (NH ₃ ) as source gases. The deposition flow of the silicon nitride film 11 is, for example, as follows.

  First, the wafer 1 is loaded into a chamber of a low-pressure CVD apparatus previously filled with nitrogen. The preheating temperature in the chamber is less than 500 ° C. Next, only ammonia, which is part of the source gas, is supplied into the chamber, and the inside of the chamber is brought into an atmosphere in which W oxide is reduced. Then, while continuing to supply ammonia into the chamber, the temperature of the wafer 1 is raised to a temperature of 600 ° C. or higher, for example, 730 ° C. to 780 ° C. Next, ammonia and monosilane are supplied into the chamber, and the silicon nitride film 11 is deposited by reacting these gases. The deposition time of the silicon nitride film 11 is about 10 minutes. Next, the supply of monosilane is stopped and the temperature of the wafer 1 is lowered to less than 500 ° C., for example, 400 ° C. while continuing to supply only ammonia into the chamber, and then the inside of the chamber is replaced with nitrogen to unload the wafer. In addition, when the temperature at which the inside of the chamber is switched from the ammonia gas atmosphere to the nitrogen gas atmosphere is high, there is a possibility that the W film 25 on the side walls of the gate electrodes 7A, 7B, 7C and the oxide 27 remaining without being reduced are sublimated. is there. Therefore, it is more desirable to replace the ammonia gas with nitrogen gas after the temperature of the wafer 1 is lowered to about 300 ° C. to 200 ° C. When the time required for forming the silicon nitride film 11 is not relatively strict, the temperature of the wafer 1 is lowered to about 100 ° C., more preferably from 70 ° C. to room temperature, and then the nitrogen gas atmosphere is changed. Needless to say, the switching can suppress the oxidation of the W film 25.

By depositing the method a silicon nitride film 11 as described above, the gate electrode 7A, 7B, without oxidizing the W film 25 and WN _X film 24 constituting 7C, the silicon nitride film 11 in a high temperature atmosphere deposition can do. Further, since the temperature of the wafer 1 is raised under the condition that the oxide 27 on the side walls of the gate electrodes 7A, 7B, and 7C is reduced, the amount of the oxide 27 that sublimates in the chamber can be kept at a very low level. Contamination of the substrate 1 in the process of forming the silicon nitride film 11 can be kept at an extremely low level.

In the above-described deposition process of the silicon nitride film 11, the temperature of the wafer 1 is raised and lowered in an ammonia atmosphere, but other gases that can reduce the oxide of W, for example, gases such as hydrogen, CO, and N ₂ O The wafer 1 may be raised and lowered in the atmosphere. However, when these gases are used, it is necessary to increase the piping system of the CVD apparatus. A rare gas such as argon (Ar), helium (He), or xenon (Xe) can also be used as the purge gas. Further, a mixed gas of dichlorosilane (SiH ₂ Cl ₂ ) and ammonia can be used as the source gas.

As a result of the above process, the W oxide contamination concentration on the surface of the substrate 1 can be reduced to a detection limit level of 1 × 10 ¹⁰ pieces / cm ² or less. Improved from 50 ms to over 200 ms.

  The silicon nitride film 11 can be deposited by plasma CVD instead of low pressure CVD. The plasma CVD method has an advantage that a film can be formed at a lower temperature (400 ° C. to 500 ° C.) than the low pressure CVD method, and therefore has an advantage that an oxide of W is difficult to be formed. It is inferior to the CVD method. Also in this case, the contamination of the substrate 1 in the process of forming the silicon nitride film 11 can be kept at a very low level by raising and lowering the temperature in an atmosphere in which the oxide of W is reduced. Further, when the silicon nitride film is deposited by the plasma CVD method, the plasma treatment is performed in the reducing atmosphere containing ammonia, hydrogen, etc. in order to remove the oxide formed on the surface of the W film 25 in the preceding process. It is effective to form a film after the deposition.

  Hereinafter, a process after the silicon nitride film 11 is deposited will be briefly described. First, as shown in FIG. 27, the upper portion of the substrate 1 of the memory array is covered with a photoresist film (not shown), and the silicon nitride film 11 in the peripheral circuit portion is anisotropically etched, thereby forming the peripheral circuit portion. Sidewall spacers 11c are formed on the side walls of the gate electrodes 7B and 7C.

Next, As or P is ion-implanted into the p-type well 3 of the peripheral circuit portion to form a high impurity concentration n ⁺ -type semiconductor region (source, drain) 12, and B is ion-implanted into the n-type well 4. As a result, a p ⁺ type semiconductor region (source, drain) with a high impurity concentration is formed. Through the steps up to here, the n-channel MISFET Qn and the p-channel MISFET Qp in the peripheral circuit section are completed.

Next, as shown in FIG. 28, an interlayer insulating film 15 composed of a spin-on-glass film and a two-layer silicon oxide film is formed on the gate electrodes 7A to 7C, and then a photoresist film (not shown). the upper portion of the silicon nitride film 11 of the semiconductor region 9 is removed, n ^{- -} the n by dry etching using a mask by exposing the surface of the semiconductor region 9 is formed a contact hole 16, 17. The etching of the silicon nitride film 11 is performed under such a condition that the etching rate of the silicon nitride film 11 with respect to the silicon oxide film 5 embedded in the element isolation trench 2 is increased so that the element isolation trench 5 is not deeply etched. This etching is performed under the condition that the silicon nitride film 11 is anisotropically etched so that the silicon nitride film 11 is left on the side wall of the gate electrode 7A (word line WL). As a result, contact holes 16 and 17 having a fine diameter are formed in a self-alignment with respect to the gate electrode 7A (word line WL).

  Next, as shown in FIG. 29, plugs 18 are formed inside the contact holes 16 and 17. In order to form the plug 18, a polycrystalline silicon film doped with P is deposited inside the contact holes 16, 17 and on the interlayer insulating film 15 by the CVD method, and then an unnecessary many layers on the interlayer insulating film 15 are deposited. The crystalline silicon film is removed by dry etching.

Next, the substrate 1 is heat-treated in a nitrogen gas atmosphere, and P in the polycrystalline silicon film constituting the plug 18 is diffused into the n ⁻ type semiconductor region 9, whereby the low resistance n type semiconductor region 9 (source, Drain). Through the steps so far, the memory cell selection MISFET Qt is formed in the memory array.

Next, as shown in FIGS. 30 and 31, a silicon oxide film 19 is deposited on the interlayer insulating film 15 by the CVD method, and then the peripheral circuit portion is formed by dry etching using a photoresist film (not shown) as a mask. The silicon oxide film 19 and the underlying interlayer insulating film 15 are dry-etched to form contact holes 21 above the source and drain (n ⁺ type semiconductor region 12) of the n-channel type MISFET Qn, and the p-channel type MISFET Qp A contact hole 22 is formed above the source and drain (p ⁺ type semiconductor region 13). At the same time, the through hole 20 is formed above the contact hole 16 by etching the silicon oxide film 19 of the memory array.

  Next, as shown in FIG. 32, plugs 23 are formed inside the contact holes 21 and 22 formed in the peripheral circuit portion and the through holes 20 formed in the memory array. In order to form the plug 23, for example, a TiN film and a W film are deposited on the silicon oxide film 19 including the insides of the contact holes 21 and 22 and the through hole 20 by a sputtering method and a CVD method, and then the silicon oxide film 19 is formed. The unnecessary upper W film and TiN film are removed by chemical mechanical polishing.

Next, as shown in FIG. 33, bit lines BL are formed on the silicon oxide film 19 of the memory array, and wirings 30 to 33 are formed on the silicon oxide film 19 of the peripheral circuit portion. The bit lines BL and the wirings 30 to 33 are formed, for example, by depositing a W film and a WN _x film on the silicon oxide film 19 by sputtering and patterning these films by dry etching using a photoresist film as a mask. To do.

  Next, as shown in FIG. 34, an interlayer insulating film 40 composed of a spin-on-glass film and a two-layer silicon oxide film is formed on the bit line BL and the wirings 30 to 33, and then the interlayer insulating film 40 is formed. Then, the silicon oxide film 19 underneath is dry-etched to form a through hole 43 above the contact hole 17, and then a plug 44 made of a polycrystalline silicon film is formed inside the through hole 43. In order to form the plug 44, a polycrystalline silicon film doped with P is deposited in the through hole 43 and on the interlayer insulating film 40 by the CVD method, and then unnecessary polycrystalline silicon on the interlayer insulating film 40 is deposited. The film is removed by dry etching.

  Next, as shown in FIG. 35, a silicon nitride film 45 is deposited on the interlayer insulating film 40 by a CVD method, and then a silicon oxide film 46 is deposited on the silicon nitride film 45 by a CVD method. Using the resist film as a mask, the silicon oxide film 46 of the memory array is dry-etched, and then the silicon nitride film 45 underneath is dry-etched to form a groove 47 above the through hole 44.

Next, as shown in FIG. 36, the lower electrode 48 of the information storage capacitor C formed of a polycrystalline silicon film is formed on the inner wall of the groove 47. In order to form the lower electrode 48, first, an amorphous silicon film (not shown) doped with P (phosphorus) is deposited in the trench 47 and on the silicon oxide film 46 by the CVD method, and then the silicon oxide film 46. The unnecessary amorphous silicon film on the upper portion of the silicon film is removed by dry etching. Next, the surface of the amorphous silicon film remaining in the groove 47 is wet-cleaned with a hydrofluoric acid-based cleaning liquid, and then monosilane (SiH ₄ ) is supplied to the surface of the amorphous silicon film in a reduced-pressure atmosphere. 1 is heat-treated to polycrystallize the amorphous silicon film, and silicon grains are grown on the surface. As a result, a lower electrode 48 made of a polycrystalline silicon film having a roughened surface is formed. Since the polycrystalline silicon film having a roughened surface has a large surface area, the amount of charges stored in the miniaturized information storage capacitor C can be increased.

Next, as shown in FIG. 37, on the surface of the lower electrode 48 formed inside the groove 47 and the surface of the silicon oxide film 46 outside the groove 47, the capacitive insulating film 49 of the information storage capacitive element C and A Ta ₂ O ₅ (tantalum oxide) film to be formed is deposited by the CVD method, and then the substrate 1 is heat-treated in an oxygen atmosphere to modify and crystallize the Ta ₂ O ₅ film. Subsequently, by depositing a TiN film serving as the Ta ₂ O ₅ film upper electrode 50 upper portion of the information storage capacitor C in, and the Ta ₂ O ₅ film and the TiN film of the peripheral circuit portion is removed by etching. As a result, an information storage capacitive element C constituted by the upper electrode 50 made of a TiN film, the capacitive insulating film 49 made of a Ta ₂ O ₅ film, and the lower electrode 48 made of a polycrystalline silicon film is formed. Further, through the steps so far, a DRAM memory cell comprising the memory cell selection MISFET Qt and the information storage capacitive element C connected in series is completed.

  Thereafter, a silicon oxide film 50 is deposited on the upper part of the information storage capacitor element C by the CVD method, and further, an Al wiring of about two layers (not shown) is formed on the upper part thereof, thereby implementing the present embodiment shown in FIGS. Form of DRAM is completed.

(Embodiment 2)
The present embodiment is applied to a logic-embedded DRAM, and an example of the manufacturing method will be described in the order of steps with reference to FIGS. The left part of each cross-sectional view showing the manufacturing method shows a part of the DRAM memory array, and the right part shows a part of the logic part.

  First, as shown in FIG. 38, a substrate 1 made of, for example, p-type single crystal silicon is prepared, and an element isolation groove 2 is formed on the main surface of the substrate 1 by the same method as in the first embodiment. A p-type well 3 is formed in one part and an n-type well 4 is formed in another part, and then the substrate 1 is steam oxidized to form a film on the surface of the p-type well 3 and the surface of the n-type well 4. A clean gate insulating film 6 made of a silicon oxide film having a thickness of about 6 nm is formed. The gate insulating film 6 may be formed of a silicon oxynitride film, a silicon nitride film, a composite insulating film of a silicon oxide film and a silicon nitride film, or the like instead of the silicon oxide film.

Next, as shown in FIG. 39, a non-doped amorphous silicon film 14 a is deposited on the gate insulating film 6. The amorphous silicon film 14a is deposited by, for example, a CVD method using monosilane (SiH ₄ ) as a source gas, and has a thickness of about 70 nm. When the amorphous silicon film 14a is formed by the CVD method using monosilane (SiH ₄ ) as a source gas, the film forming temperature is set in the range of 500 ° C. to 550 ° C., for example, 530 ° C. When the film forming temperature is set to 600 ° C. or higher, the polycrystalline silicon film 14n is obtained as in the first embodiment. Also, when depositing dinosilane (Si ₂ H ₆ ) by a CVD method using a source gas, amorphous silicon is formed by forming a film at a temperature lower than the temperature at which a polycrystalline silicon film is obtained, for example, about 520 ° C. A film 14a is obtained. Instead of the non-doped amorphous silicon film 14a, a silicon film containing up to about 50% Ge (germanium) may be used. For example, a polycrystalline silicon film is deposited by CVD, and then Ge is introduced into the polycrystalline silicon film by ion implantation to obtain an amorphous silicon film containing Ge.

  As will be described later, the logic-embedded DRAM according to the present embodiment is a polycrystal which is a part of the gate electrode of the n-channel MISFET in order to make both the n-channel MISFET and the p-channel MISFET of the logic portion a surface channel type. The silicon film is made of n-type, and the polycrystalline silicon film which is a part of the gate electrode of the p-channel type MISFET is made of p-type. In this case, a non-doped polycrystalline silicon film is deposited on top of the gate insulating film 6, and then boron (B) is ion-implanted to make the polycrystalline silicon film in the p-channel MISFET formation region p-type. There is a possibility that part of boron penetrates the polycrystalline silicon film and the gate insulating film 6 due to the channeling phenomenon and is introduced into the channel region of the substrate 1.

  Therefore, when a part of the gate electrode of the p-channel type MISFET is formed of a p-type polycrystalline silicon film as in the present embodiment, it is desirable to use the amorphous silicon film 14a that hardly causes a channeling phenomenon. On the other hand, when the silicon films of all the gate electrodes (7A, 7B, 7C) are composed of n-type conductive silicon films as in the DRAM of the first embodiment, the above-described problem of boron penetration Therefore, a polycrystalline silicon film may be used in place of the amorphous silicon film 14a.

Next, as shown in FIG. 40, the upper portion of the p-type well 3 is covered with a photoresist film 60, and B (boron) is ion-implanted into the amorphous silicon film 14 a on the upper portion of the n-type well 4. The dose amount of B is, for example, 2 × 10 ¹⁵ atoms / cm ² , and the implantation energy is, for example, 5 keV. Subsequently, after removing the photoresist film 60 by ashing, as shown in FIG. 41, the upper portion of the n-type well 4 is covered with a photoresist film 61, and P (phosphorus) is formed on the amorphous silicon film 14a on the upper portion of the p-type well 3. ) Is ion-implanted. The dose amount of P is, for example, 2 × 10 ¹⁵ atoms / cm ² , and the implantation energy is, for example, 10 keV.

  Next, the photoresist film 61 is removed by ashing, and the surface of the polycrystalline silicon film 14n is cleaned using hydrofluoric acid, and then lamp annealing is performed in a nitrogen atmosphere at about 950 ° C. for about 1 minute. 14a is crystallized and the impurities (B and P) are electrically activated. As a result, as shown in FIG. 42, the amorphous silicon film 14a in the n-channel type MISFET formation region becomes the n-type polycrystalline silicon film 14n, and the amorphous silicon film 14a in the p-channel type MISFET formation region becomes the p-type polycrystalline silicon. The film 14p is formed.

If a heat treatment for crystallizing the amorphous silicon film 14a is performed after the WN _x film or W film is deposited on the amorphous silicon film 14a, the WN _x film or W film is caused by a stress change caused by the crystallization of silicon. There is a possibility that the film peels off. Further, since the impurities (B, P) in the amorphous silicon film 14a are taken into the WN _x film and the W film before diffusing to the interface with the gate insulating film 6, depletion occurs near the interface of the gate insulating film 6. As a result, the desired device characteristics may not be obtained. Therefore, it is desirable to perform the heat treatment before depositing a WN _x film or a W film on the amorphous silicon film 14a.

Next, after cleaning the surfaces of the polycrystalline silicon films 14n and 14p using hydrofluoric acid, an amorphous silicon film 34a is deposited on the polycrystalline silicon films 14n and 14p as shown in FIG. The amorphous silicon film 34a is deposited, for example, by a CVD method using monosilane (SiH ₄ ) as a source gas (film formation temperature = about 530 ° C.), and the film thickness is about 10 nm. In addition, the amorphous silicon film 34a has an extremely low impurity concentration of amorphous silicon having an initial impurity concentration of less than 1.0 × 10 ¹⁷ cm ³ , or substantially non-doped amorphous silicon of less than 1.0 × 10 ¹⁴ cm ^3. Consists of. The amorphous silicon film 34a is formed in order to block contact between the extremely thin natural oxide film formed on the surfaces of the polycrystalline silicon films 14n and 14p and the WN _x film 24 deposited thereon in the next step. The amorphous silicon film 34a does not have to be in a completely amorphous state, and may be an aggregate of extremely small silicon crystal grains, for example.

Next, after cleaning the surface of the amorphous silicon film 34a using hydrofluoric acid, as shown in FIG. 44, the WN _X film 24 and the W film 25 are successively deposited on the amorphous silicon film 34a by sputtering. Subsequently, a silicon nitride film 8 is deposited on the W film 25 by the CVD method. The film thickness of the WN _x film 24 is about 5 nm to 10 nm. The film thickness of the W film 25 deposited on the WN _x film 24 is about 70 nm to 80 nm, and the film thickness of the silicon nitride film 8 is about 160 nm. A Mo film may be deposited on the WN _x film 24 instead of the W film 25.

In the present embodiment, when the WN _x film 24 is formed by sputtering, the nitrogen element composition at the completion of the device is at least 7% to 10%, preferably 13% or more, more preferably 18% or more. The WN _x film 24 is formed under various conditions. In order to form such a WN _x film 24, the film may be formed in an atmosphere in which the WN _x film 24 contains a high concentration of nitrogen. That is, sputtering may be performed by setting the atmosphere in the chamber to a gas atmosphere in which the flow rate ratio of nitrogen gas to argon gas is 1.0 or more. Specifically, for example, the film formation is performed under the conditions of a nitrogen gas flow rate = 50 sccm to 80 sccm, an argon gas flow rate = 20 sccm to 30 sccm, a vacuum in the chamber = 0.5 Pa, and a temperature = 200 ° C. to 500 ° C.

Further, it is desirable that the film thickness of the WN _x film 24 during film formation be in the range of 5 nm to 10 nm. By setting the thickness of the WN _X film 24 at the time of film formation to 5 nm or more, even if a part of the WN _X film 24 reacts with the lower silicon layer in the heat treatment process after the film formation, the remaining at the completion of the device Since the film thickness is at least 1 nm or more, the function as a barrier layer is ensured. On the other hand, if the thickness of the WN _X film 24 at the time of film formation exceeds 10 nm, the wiring resistance of the gate electrode is increased, there is a disadvantage for high-speed operation of the circuit.

Also, even when a film was formed in the atmosphere to contain a high concentration of nitrogen in the WN _X film 24, because the excess nitrogen in the heat treatment step after the film formation is disengaged from diffusing, WN _X at element completed The film 24 is mainly composed of W ₂ N, which is the most stoichiometrically stable. However, since a part of the WN _x film 24 reacts with the lower silicon layer in the course of the heat treatment, the WN _x film 24 at the completion of the element contains W ₂ N and other WN _x , and in some cases further contains WSiN. It becomes a mixed crystal.

Next, as shown in FIG. 45, the silicon nitride and the photoresist film 62 formed on the silicon nitride film 8 as a mask layer 8, W film 24, WN _X film 25, an amorphous silicon film 34a and the polycrystalline silicon film By sequentially dry-etching 14n and 14p, a gate electrode 7A (word line WL) is formed on the gate insulating film 6 of the memory array, and gate electrodes 7D and 7E are formed on the gate insulating film 6 of the logic portion.

  Thereafter, the memory cell selection MISFET Qt is formed in the memory array by the method described in the first embodiment, and the n-channel MISFET and the p-channel MISFET are formed in the logic portion. Also in this case, the re-oxidation treatment, the cleaning treatment, the deposition of the silicon nitride film and the like of the gate insulating film 6 are performed by the same method as in the first embodiment, so that the contamination of the substrate 1 by the oxide of W is at a very low level. Can be kept in.

Figure 46 is the gate electrode 7A, 7D, the relationship between the crystal structure of the nitrogen flow and WN _X film 24 for forming the WN _X film 24 constituting a part of 7E, and immediately after deposition of WN _X film 24 It is a graph which shows the result investigated by X-ray-diffraction measurement after heat-processing in 950 degreeC nitrogen gas for 1 minute. As shown, for the case of a 10sccm nitrogen flow for forming the WN _X film 24, nitrogen in the WN _X film 24 in the course of high-temperature heat treatment it becomes released by W film, WN _X film The function as the 24 barrier layer is lost.

FIG. 47 is a graph obtained by measuring the film stress when the WN _x film formed by changing the nitrogen gas flow rate while keeping the argon gas flow rate constant (40 sccm) is heat-treated at various temperatures. When the film is formed at a substrate temperature of 400 ° C., (b) shows the case where the film is formed at a substrate temperature of 200 ° C. As shown in the figure, it can be seen that when the flow rate of nitrogen when forming the WN _x film is small, nitrogen is released by the subsequent heat treatment and the film contracts, so that the film stress increases.

FIG. 48 shows the results of examining the relationship between the breakdown voltage of the gate electrode including the WN _x film formed by changing the flow rate ratio of nitrogen gas and argon gas, and the contact resistance at the interface of the WN _x film / polycrystalline silicon film. Yes. As shown in the figure, in the case of a WN _x film formed under a condition where the flow rate ratio of nitrogen gas is small, the breakdown voltage of the gate electrode is lowered and the contact resistance at the interface of the WN _x film / polycrystalline silicon film is increased.

As described above, according to the present embodiment in which film formation is performed in an atmosphere in which high concentration of nitrogen is contained in the WN _X film 24, N remains in the WN _X film even after the heat treatment step. The function of the WN _X film 24 as a barrier layer is not lost. Further, by interposing the amorphous silicon film 34a between the WN _X film 24 and the polycrystalline silicon films 14n and 14p, an extremely thin natural oxide film and the WN _X film 24 formed on the surfaces of the polycrystalline silicon films 14n and 14p. The formation of a high resistance layer due to contact with can be suppressed. The amorphous silicon film 34a that has undergone the heat treatment step becomes a polycrystalline film having an average crystal grain size smaller than that of the underlying polycrystalline silicon films 14n and 14p.

Through the process as described above, the contact resistance at the interface between the WN _x film 24 and the polysilicon films 14n and 14p constituting the gate electrodes 7A, 7D, and 7E is reduced from ⁵ kΩ / μm ² to 10 kΩ / μm ² before the countermeasure. It could be reduced to 1 kΩ / μm ² .

  Further, by performing re-oxidation treatment, cleaning treatment, deposition of a silicon nitride film and the like on the gate insulating film 6 by the same method as in the first embodiment, the contamination of the substrate 1 by W oxide is kept at an extremely low level. As a result, the refresh time of the DRAM could be remarkably improved.

(Embodiment 3)
In the second embodiment, WN _X film 24 and the polycrystalline silicon film 14n, by interposing the amorphous silicon film 34a between the 14p, and WN _X film 24 a polycrystalline silicon film 14n, a contact resistance between 14p reduced but, in the present embodiment, WN _X film 24 and the polycrystalline silicon film 14n, by interposing a thin film thickness of W film 62 between the 14p, WN _X film 24 and the polycrystalline silicon film 14n, The contact resistance with 14p is reduced.

  This process will be described. First, as shown in FIG. 49, an n-type polycrystalline silicon film 14n is formed on the gate insulating film 6 in the n-channel MISFET forming region, and the gate insulating film 6 in the p-channel MISFET forming region. A p-type polycrystalline silicon film 14p is formed thereon. The steps so far are the same as the steps shown in FIGS. 38 to 42 of the second embodiment.

  Next, after cleaning the surfaces of the polycrystalline silicon films 14n and 14p using hydrofluoric acid, a W film 65 is deposited on the polycrystalline silicon films 14n and 14p as shown in FIG. The W film 65 is deposited by sputtering, for example, and the film thickness is about 5 nm.

Next, as shown in FIG. 51, a WN _x film 24, a W film 25, and a silicon nitride film 8 are sequentially deposited on the W film 65 by the same method as in the second embodiment. WN _X film thickness of the film 24 is 10nm order of 5 nm, the thickness of the W film 25 is about 70Nm～80nm, the thickness of the silicon nitride film 8 of about 160 nm. A Mo film may be deposited on the WN _x film 24 instead of the W film 25. The WN _x film 24 is formed in an atmosphere containing high-concentration nitrogen as in the second embodiment, and the nitrogen element composition at the completion of the element is at least 7% to 10%, preferably 13% or more, more preferably 18% or more. Subsequent steps are the same as those in the second embodiment.

Thus, by interposing the W film 62 between the WN _X film 24 and the polycrystalline silicon films 14n and 14p, the W film 62 and the polycrystalline silicon films 14n and 14p react in the course of the subsequent heat treatment. A conductive layer mainly composed of W silicide (WSi _x ) is formed. As a result, the formation of a high resistance layer due to the contact between the natural oxide film generated on the surfaces of the polycrystalline silicon films 14n and 14p and the WN _x film 24 is suppressed, so that the same effect as in the second embodiment is obtained. be able to.

Through the process as described above, the contact resistance at the interface between the WN _x film 24 and the polysilicon films 14n and 14p constituting the gate electrodes 7A, 7D, and 7E is reduced from ⁵ kΩ / μm ² to 10 kΩ / μm ² before the countermeasure. It could be reduced to 1 kΩ / μm ² .

  Further, by performing re-oxidation treatment, cleaning treatment, deposition of a silicon nitride film and the like on the gate insulating film 6 by the same method as in the first embodiment, the contamination of the substrate 1 by W oxide is kept at an extremely low level. As a result, the refresh time of the DRAM could be remarkably improved.

In the present embodiment, the W film 62 is interposed between the WN _X film 24 and the polycrystalline silicon films 14n and 14p, and the W film 62 and the polycrystalline silicon films 14n and 14p react with each other in the course of the subsequent heat treatment. As a result, a conductive layer mainly composed of W silicide is formed. However, even if a thin W silicide film is formed on the polycrystalline silicon films 14n and 14p and the WN _x film 24 and the W film 25 are deposited on the thin W silicide film. Good. As a result, it is possible to prevent a problem that nitrogen in the WN _x film 24 diffuses to the interfaces with the polycrystalline silicon films 14n and 14p to form a high resistance silicon nitride layer. Further, when the W silicide layer is formed by reacting the W film 62 and the polycrystalline silicon films 14n and 14p in the course of the heat treatment, the reaction may occur locally and the gate breakdown voltage may be lowered. When a W silicide film is deposited, such a local reaction hardly occurs. The film thickness of the W silicide film may be about 5 nm to 20 nm. Further, _X of WSi _X is preferably about 2.0 to 2.7.

(Embodiment 4)
This embodiment is applied to a CMOS logic LSI having a circuit composed of an n-channel MISFET and a p-channel MISFET, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 52, a substrate 1 made of, for example, p-type single crystal silicon is prepared, and an element isolation trench 2, a p-type well 3, An n-type well 4 and a gate insulating film 6 are sequentially formed.

Next, as shown in FIG. 53, a low resistance n-type polycrystalline silicon film 14n doped with P (phosphorus) at a concentration of 1.0 × 10 ¹⁹ cm ³ or more is deposited on the gate insulating film 6; After cleaning the surface of the polycrystalline silicon film 14n using hydrofluoric acid, a WN _x film 24 having a film thickness of about 5 nm to 10 nm is deposited on the polycrystalline silicon film 14n by sputtering.

As in the second embodiment, the WN _x film 24 is formed in an atmosphere containing a high concentration of nitrogen, and the nitrogen element composition at the completion of the element is at least 7% to 10%, preferably 13%. Above, more preferably 18% or more. Further, the WN _x film 24 is deposited with a film thickness such that the remaining film thickness when the element is completed is at least 1 nm or more.

Further, as in the third embodiment, the WN _x film 24 and the polycrystal are formed for the purpose of suppressing the formation of the high resistance layer due to the contact between the natural oxide film generated on the surface of the polycrystal silicon film 14n and the WN _x film 24. A W film 62 may be formed between the silicon film 14n.

Next, as shown in FIG. 54, P (phosphorus) ions are implanted into the main surface of the substrate 1. This ion implantation is performed with such energy that P penetrates the WN _x film 24 and reaches a region of 10 nm or less from the surface of the polycrystalline silicon film 14n. For example, when the thickness of the WN _X film 24 is about 3 nm to 15 nm, the implantation energy of P is set to 2 keV to 10 keV.

This ion implantation is performed at a dose such that the P concentration in the surface region of the polycrystalline silicon film 14n is 5 × 10 ¹⁹ atoms / cm ³ or more. Further, after this ion implantation, lamp annealing may be performed for about 1 minute in a nitrogen atmosphere at about 950 ° C. to electrically activate the impurity (P) in the polycrystalline silicon film 14n. Note that the impurity (P) in the polycrystalline silicon film 14n is electrically activated in a later heat treatment step, and thus the heat treatment here may be omitted.

The ion implantation may be performed after the polycrystalline silicon film 14n is deposited and before the WN _x film 24 is deposited. When the W film 62 is formed between the WN _X film 24 and the polycrystalline silicon film 14n, this ion implantation is performed after the W film is formed, and then the WN _X film 24 is deposited on the W film. May be.

Next, as shown in FIG. 55, a W film 25 having a film thickness of about 70 nm is deposited on the WN _x film 24 by sputtering, and then a silicon nitride film having a film thickness of about 160 nm is deposited on the W film 25 by CVD. 8 is deposited. A Mo film may be deposited on the WN _x film 24 instead of the W film 25. After the W film 25 is deposited, another ion implantation is performed on the main surface of the substrate 1, and P is doped into the polycrystalline silicon film 14n through the W film 25 and the WN _x film 24, thereby forming the polycrystalline silicon film 14n. The surface region may be further reduced in resistance.

Next, as shown in FIG. 56, the silicon nitride and the photoresist film 63 formed on the silicon nitride film 8 as a mask layer 8, W film 24, WN _X film 25 and sequentially dry-etching the polycrystalline silicon film 14n As a result, an n-channel MISFET gate electrode 7F is formed on the p-type well 3, and a p-channel MISFET gate electrode 7G is formed on the n-type well 4.

  Thereafter, in order to keep the contamination of the substrate 1 by the oxide of W at a very low level, the re-oxidation process of the gate insulating film 6 shaved by the dry etching, the subsequent cleaning process, the deposition of the silicon nitride film, and the like are performed. The method is the same as in the first mode.

  In the present embodiment, the polycrystalline silicon film which is a part of each of the gate electrodes 7F and 7G is formed of n-type. However, in order to make both the n-channel MISFET and the p-channel MISFET both surface channel types, The polycrystalline silicon film that is a part of the gate electrode 7F of the channel type MISFET may be configured as an n-type, and the polycrystalline silicon film that is a part of the gate electrode 7G of the p-channel type MISFET may be configured as a p-type. In this case, as in the second embodiment, a non-doped amorphous silicon film is deposited on the gate insulating film 6, and then the amorphous silicon film in the n-channel MISFET formation region is formed by ion implantation using the photoresist film as a mask. Introducing P into B and introducing B into the amorphous silicon film in the p-channel MISFET formation region can prevent penetration of B due to the channeling phenomenon.

(Embodiment 5)
In the fourth embodiment, the resistance of the surface region of the polycrystalline silicon film 14n is reduced by impurity ion implantation. However, the resistance of the surface region of the polycrystalline silicon film 14n can be reduced by the following method. .

First, as shown in FIG. 57, for example, an element isolation trench 2, a p-type well 3, an n-type well 4 and a gate insulating film 6 are sequentially formed on the main surface of a substrate 1 made of p-type single crystal silicon. A low resistance n-type polycrystalline silicon film 14n doped with P (phosphorus) at a concentration of 1.0 × 10 ¹⁹ cm ³ or more is deposited on the gate insulating film 6. The steps up to here are the same as those in the fourth embodiment.

Next, as shown in FIG. 58, a low-resistance n-type polycrystalline silicon film 64 doped with P at a concentration of 5.0 × 10 ¹⁹ cm ³ or more is deposited on the polycrystalline silicon film 14n by the CVD method. Thereafter, the substrate 1 is heat-treated, and P in the n-type polycrystalline silicon film 64 is diffused from the surface of the polycrystalline silicon film 14n to a surface region of 10 nm or less, and the P concentration in this surface region is 5 × 10 ¹⁹ atoms / cm 3. ³ or more. After this thermal diffusion treatment, lamp annealing for about 1 minute may be performed in a nitrogen atmosphere at about 950 ° C. to electrically activate P in the polycrystalline silicon film 14n. Since P in the film 14n is electrically activated in a later heat treatment step, this heat treatment may be omitted.

  Next, as shown in FIG. 59, after removing the n-type polycrystalline silicon film 64 by dry etching, the surface of the polycrystalline silicon film 14n exposed on the surface of the substrate 1 is washed with hydrofluoric acid.

Next, as shown in FIG. 60, a WN _x film 24 having a thickness of about 5 nm to 10 nm is deposited on the polycrystalline silicon film 14n by sputtering. As in the fourth embodiment, the WN _x film 24 is formed in an atmosphere containing a high concentration of nitrogen, and the nitrogen element composition at the completion of the element is at least 7% to 10%, preferably 13%. Above, more preferably 18% or more. Further, the WN _x film 24 is deposited with a film thickness such that the remaining film thickness when the element is completed is at least 1 nm or more.

Further, as in the third embodiment, the WN _x film 24 and the polycrystal are formed for the purpose of suppressing the formation of the high resistance layer due to the contact between the natural oxide film generated on the surface of the polycrystal silicon film 14n and the WN _x film 24. A W film may be formed between the silicon film 14n.

Thereafter, as shown in FIG. 61, a W film 25 having a thickness of about 70 nm is deposited on the WN _X film 24 by sputtering, and then a silicon nitride film 8 having a thickness of about 160 nm is deposited on the W film 25 by CVD. To deposit.

Next, as shown in FIG. 62, the silicon nitride film 8, the W film 24, the WN _x film 25, and the polycrystalline silicon film 14n are sequentially dry etched using the photoresist film 63 formed on the silicon nitride film 8 as a mask. As a result, an n-channel MISFET gate electrode 7F is formed on the p-type well 3, and a p-channel MISFET gate electrode 7G is formed on the n-type well 4.

  Thereafter, in order to keep the contamination of the substrate 1 by the oxide of W at a very low level, the re-oxidation process of the gate insulating film 6 shaved by the dry etching, the subsequent cleaning process, the deposition of the silicon nitride film, and the like are performed. The method is the same as in the first mode.

  In the present embodiment, P in the polycrystalline silicon film 64 deposited on the polycrystalline silicon film 14n is thermally diffused to reduce the resistance of the surface region of the polycrystalline silicon film 14n. For example, the polycrystalline silicon film 14n P is introduced into the surface region by ion implantation, and then an insulating film such as a silicon oxide film is formed on the polycrystalline silicon film 14n, followed by heat treatment, and introduced into the surface region of the polycrystalline silicon film 14n. Alternatively, the surface region of the polycrystalline silicon film 14n may be reduced in resistance by removing the insulating film after segregating the P in the vicinity of the interface with the insulating film. The insulating film is composed of, for example, a silicon oxide film formed by thermally oxidizing the surface of the polycrystalline silicon film 14n, or a silicon oxide film deposited on the polycrystalline silicon film 14n by the CVD method, but is not limited thereto. It is not a thing.

(Embodiment 6)
The present embodiment is applied to a flash memory, and an example of a manufacturing method thereof will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 63, after the element isolation trench 2, the p-type well 3, and the gate insulating film 6 are formed on the main surface of the substrate 1 by the same method as in the first embodiment, FIGS. As shown, an n-type polycrystalline silicon film 66n having a film thickness of about 70 nm to 100 nm is deposited on the substrate 1 by a CVD method. The polycrystalline silicon film 66n is doped with an n-type impurity such as phosphorus (P) during the deposition process. Alternatively, an n-type impurity may be doped by ion implantation after depositing a non-doped polycrystalline silicon film. The polycrystalline silicon film 66n is used as a floating gate electrode of the MISFET constituting the memory cell.

  Next, as shown in FIGS. 66 and 67, the polycrystalline silicon film 66n is dry-etched using the photoresist film as a mask, thereby extending the upper portion of the active region L along the extending direction thereof. A polycrystalline silicon film 66n having a strip-like plane pattern is formed.

  Next, as shown in FIGS. 68 and 69, an ONO film 67 made of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the substrate 1 on which the polycrystalline silicon film 66n is formed. The ONO film 67 is used as a second gate insulating film of a MISFET constituting the memory cell. For example, a 5 nm-thickness silicon oxide film, a 7 nm-thickness silicon nitride film, and a 4 nm-thickness oxidation film are formed on the substrate 1 by the CVD method. The silicon film is formed by sequentially depositing.

Next, as shown in FIGS. 70 and 71, an n-type polycrystalline silicon film 14n doped with P (phosphorus), a WN _x film 24, a W film 25, and a silicon nitride film 8 are sequentially deposited on the ONO film 67. To do. The polycrystalline silicon film 14n, the W film 25, and the silicon nitride film 8 are deposited by the same method as in the first embodiment. The WN _x film 24 is deposited by the same method as in the second embodiment in order to reduce the contact resistance with the polycrystalline silicon film 14n. That is, the WN _x film 24 is formed under the condition that the nitrogen element composition at the time of device completion is at least 7% to 10% or more, preferably 13% or more, more preferably 18% or more. Further, in order to at least 1nm or more residual film thickness at the time of element completion, the thickness of the WN _X film 24 at the time of film formation, it is preferably in the range from 5nm to 10 nm. Further, in order to reduce the contact resistance between the WN _x film 24 and the polycrystalline silicon film 14n, the process described in the third, fourth or fifth embodiment may be employed.

  The polycrystalline silicon film 14n is used as a control gate electrode and a word line WL of a MISFET constituting a memory cell. The silicon nitride film 8 is used as an insulating film that protects the upper part of the control gate electrode. The polycrystalline silicon film 14n can be formed of a silicon film containing about 50% of Ge (germanium) at the maximum.

Next, as shown in FIG. 72, the silicon nitride and the photoresist film formed on the silicon nitride film 8 (not shown) as a mask film 8, W film 24, WN _X film 25, the polycrystalline silicon film 14n , are dry etched successively ONO film 67 and the polycrystalline silicon film 66n, a floating gate electrode 68 made of polycrystalline silicon 66n, W film 24, control of WN _X film 25 and the polycrystalline silicon film consisting 14n polymetal structure A gate electrode 69 (word line WL) is formed.

  Next, as shown in FIG. 73, an n-type semiconductor region 70 constituting the source and drain of the MISFET is formed. In the n-type semiconductor region 70, after ion-implanting n-type impurities (for example, arsenic (As)) into the p-type well 3, the substrate 1 is heat-treated at about 900 ° C. to diffuse the n-type impurities into the p-type well 3. By forming.

  In the steps so far, the gate insulating film 6 in the space region of the gate electrode (the floating gate electrode 68 and the control gate electrode 69) has been damaged in the gate electrode processing step and the impurity ion implantation step. This damage deteriorates the quality of the gate insulating film 6, such as a path in which electrons injected into the floating gate electrode 68 leak from the end of the floating gate electrode 68 to the substrate 1. There is.

Therefore, after the gate insulating film 6 is etched using hydrofluoric acid, a re-oxidation process for replenishing and regenerating the thinned gate insulating film 6 is performed. By performing this re-oxidation process in the same manner as in the first embodiment, oxidation of the W film 25 and the WN _x film 24 can be prevented, and oxide contamination on the surface of the substrate 1 can be kept at an extremely low level. As a result of this reoxidation treatment, as shown in FIG. 74, the space region of the gate electrode (floating gate electrode 68 and control gate electrode 69), that is, the surface of the n-type semiconductor region (source, drain) 70 and the sidewall of the floating gate electrode 68 A gate insulating film 6 is re-formed on the lower end portion.

  Next, after cleaning the surface of the substrate 1, as shown in FIG. 75, a silicon nitride film 11 is deposited on the substrate 1 by a low pressure CVD method. By performing the cleaning process and the deposition of the silicon nitride film 11 by the same method as in the first embodiment, the contamination of the substrate 1 by the oxide of W can be kept at a very low level.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, the case where the present invention is applied to a DRAM, a DRAM mixed logic LSI, a CMOS logic LSI, and a flash memory has been described. However, the present invention is not limited to these LSIs, and a polymetal (Polymetal) conductive film is used as a gate electrode. The present invention can be widely applied to LSIs having MISFETs on which are formed.

  In addition, the invention described in the present application is deeply connected to the polysilicon layer, so that it can be applied to a non-polysilicon metal gate electrode without a polysilicon layer unless the polysilicon layer is essential. Not too long.

  The present invention can be used for manufacturing an integrated circuit device having a polymetal gate, for example.

1 is an overall plan view of a semiconductor chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed. It is a principal part top view of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. 1 is a fragmentary enlarged plan view of a semiconductor substrate showing a manufacturing method of a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is a schematic view of a batch type vertical oxidation furnace used for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 15 is a schematic view showing a catalytic steam / hydrogen mixed gas generator connected to the batch type vertical oxidation furnace shown in FIG. 14. FIG. 16 is a piping system diagram of the steam / hydrogen mixed gas generating device shown in FIG. 15. It is a graph which shows the temperature dependence of the equilibrium vapor pressure ratio (P _H2O / P _H2 ) of the oxidation-reduction reaction using the steam / hydrogen mixed gas. It is explanatory drawing of the re-oxidation process sequence using the batch type vertical oxidation furnace shown in FIG. It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. (A) is the schematic of the single wafer type oxidation furnace used for manufacture of the semiconductor integrated circuit device which is one embodiment of this invention, (b) is sectional drawing along the BB 'line of (a). It is. It is a state figure showing the relation between the oxidation-reduction potential of tungsten-water system and pH. It is a graph which shows the result of having measured the removal effect by the water washing of the natural oxide film formed in the W film | membrane surface by a total reflection fluorescence X ray. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. The relationship between the nitrogen flow rate and the WN _X film crystal structure during the formation of the WN _X film constituting a part of the gate electrode is a graph showing the results of examining the X-ray diffraction measurement. (A), (b) keeps the flow rate of argon gas constant is a graph of film stress when heat-treating the WN _X film formed by changing the flow rate of nitrogen gas at various temperatures. By changing the flow ratio of nitrogen gas and argon gas is a graph showing the results of examining the breakdown voltage, and WN _X film / relationship of the contact resistance of the polycrystalline silicon film interface of the gate electrode including the formed WN _X film. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention.

Explanation of symbols

1 Semiconductor substrate (wafer)
DESCRIPTION OF SYMBOLS 1A Semiconductor chip 2 Element isolation groove 3 P-type well 4 N-type well 5 Silicon oxide film 6 Gate insulating film 7A-7G Gate electrode 8 Silicon nitride film 9 N-type semiconductor region (source, drain)
10 p ⁻ type semiconductor region 11 Silicon nitride film 11c Side wall spacer 12 n ⁺ type semiconductor region (source, drain)
13 p ⁺ type semiconductor region (source, drain)
14a Amorphous silicon film 14n, 14p Polycrystalline silicon film 15 Interlayer insulating film 16, 17 Contact hole 18 Plug 19 Silicon oxide film 20 Through hole 21, 22 Contact hole 23 Plug 24 WN _X film 25 W film 26 Photoresist film 27 Oxide (WO _X )
28, 29 Photoresist films 30 to 33 Wiring 34a Amorphous silicon film 40 Interlayer insulating film 41 Polycrystalline silicon film 42 Side wall spacer 43 Through hole 44 Plug 45 Silicon nitride film 46 Silicon oxide film 47 Groove 48 Lower electrode 49 Capacitive insulating film 50 Upper electrode 51 Silicon oxide film 60-63 Photoresist film 64 N-type polycrystalline silicon film 65 W film 66n Polycrystalline silicon film 67 ONO film 68 Floating gate electrode 69 Control gate electrode 70 N-type semiconductor region (source, drain)
100 single wafer oxidation furnace 101 chamber 103 soaking ring 104 susceptor 105 support arm 106 thermocouple 107 halogen lamp 108 gas introduction pipe 109 through-hole 110 partition 111 exhaust pipe 140 gas generator 141 reactor 142 coil 143 heater 144a, 144b, 144c Gas storage tank 145 Piping 146a, 146b, 146c Mass flow controllers 147a, 147b, 147c Open / close valve 148 Dilution line 150 Batch type vertical oxidation furnace 151 Chamber 152 Heater 153 Quartz boat 154 Gas introduction pipe 155 Exhaust pipe BL Bit line BP Bonding pad C Capacitance element for information storage L Active area MARY Memory array PC Peripheral circuit part Qn n channel type MISFET
Qp p-channel MISFET
Qt MISFET for memory cell selection
WL Word line

Claims (10)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) patterning a refractory metal film on the first main surface of the wafer;
(B) In a mixed gas atmosphere containing hydrogen and moisture, with respect to a portion containing silicon as a main component on the first main surface of the wafer without oxidizing the refractory metal film. Performing an oxidation treatment at a first temperature of 600 degrees or higher;
(C) After the step (b), it is neutral or weakly alkaline substantially free of hydrogen peroxide, and in the range of pH 6.5 to 12 in the redox potential and pH state diagram of the refractory metal-water system. Cleaning the first main surface of the wafer with water or a chemical solution in a reduction potential region; 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the following steps:
(D) After the step (c), a step of performing ion implantation treatment or heat treatment at a temperature of 600 degrees Celsius or higher on the first main surface of the wafer.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pH of the water or the chemical solution is 6.5 or more and less than 12.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the pH of the water or the chemical solution is 7 or more and less than 10.5.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the water or the chemical solution is used for the cleaning in a flowing state.   6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the temperature of the water or the chemical solution is less than 50 degrees Celsius or 70 degrees Celsius or more.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the temperature of the water or the chemical solution is less than 45 degrees Celsius or 75 degrees Celsius or more.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the temperature of the water or the chemical is approximately room temperature.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the cleaning is performed while applying ultrasonic vibration to the water or the chemical solution.   2. The semiconductor integrated circuit according to claim 1, wherein the water or the chemical solution does not contain 0.3% or more of the hydrogen peroxide by volume when the concentration of hydrogen peroxide having a concentration of 30% by weight is taken as 100%. Device manufacturing method.