JP4620654B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Manufacturing method of semiconductor integrated circuit device Download PDF

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JP4620654B2
JP4620654B2 JP2006347647A JP2006347647A JP4620654B2 JP 4620654 B2 JP4620654 B2 JP 4620654B2 JP 2006347647 A JP2006347647 A JP 2006347647A JP 2006347647 A JP2006347647 A JP 2006347647A JP 4620654 B2 JP4620654 B2 JP 4620654B2
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JP2007129251A (en
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吉田  誠
信義 夏秋
直樹 山本
勇 浅野
義和 田辺
政良 齊藤
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株式会社日立製作所
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  The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a gate processing process of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a polymetal gate.

  Devices such as DRAMs (Dynamic Random Access Memory) of 256 Mbit (Megabit) or later, etc., which comprise a circuit with a fine MOSFET having a gate length of 0.25 μm or less, include a metal layer in order to reduce the parasitic resistance of the gate electrode. Adoption of a gate processing process using a resistive conductive material is essential.

  What is regarded as a promising low-resistance gate electrode material is a so-called polymetal in which a refractory metal film is laminated on a polycrystalline silicon film. Polymetal can be used not only as a gate electrode material but also as a wiring material because its sheet resistance is as low as about 2Ω / □. As the refractory metal, W (tungsten), Mo (molybdenum), Ti (titanium), or the like, which shows good low resistance even at a low temperature process of 800 ° C. or less and has high electromigration resistance, is used. Note that if these refractory metal films are laminated directly on the polycrystalline silicon film, the adhesive strength between the two will decrease, or a high-resistance silicide layer will be formed at the interface between the two due to the high-temperature heat treatment process. The polymetal gate has a three-layer structure in which a barrier layer made of a metal nitride film such as TiN (titanium nitride) or WN (tungsten nitride) is interposed between a polycrystalline silicon film and a refractory metal film. The

  The outline of the conventional gate processing process is as follows. First, a semiconductor substrate is thermally oxidized to form a gate oxide film on the surface thereof. In general, the thermal oxide film is formed in a dry oxygen atmosphere, but in the case of forming a gate oxide film, a wet oxidation method is used because the defect density in the film can be reduced. In the wet oxidation method, a pyrogenic method is used in which hydrogen is burned in an oxygen atmosphere to generate water, and this water is supplied to the surface of the semiconductor wafer together with oxygen.

  However, the pyrogenic method ignites and burns hydrogen ejected from the nozzle attached to the tip of the quartz hydrogen gas inlet tube, so that the nozzle melts with the heat and particles are generated. Since there is a possibility of becoming a pollution source, a method of generating water by a catalytic system without combustion has also been proposed.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 5-152282) discloses a thermal oxidation apparatus having an inner surface of a hydrogen gas introduction pipe made of Ni (nickel) or a Ni-containing material and a means for heating the hydrogen gas introduction pipe. is doing. In this thermal oxidation apparatus, hydrogen is brought into contact with Ni (or Ni-containing material) in a hydrogen gas introduction pipe heated to 300 ° C. or more to generate hydrogen active species, and this hydrogen active species and oxygen (or a gas containing oxygen) To produce water. That is, since water is generated by a catalytic method without combustion, the tip of the hydrogen-introduced quartz tube is not melted to generate particles.

  Next, after depositing a gate electrode material on the gate oxide film formed by the wet oxidation method as described above, the gate electrode material is patterned by dry etching using a photoresist as a mask. Thereafter, the photoresist is removed by ashing (ashing), and an etching solution such as hydrofluoric acid is used to remove dry etching residue and ashing residue remaining on the substrate surface.

  When the above wet etching is performed, the gate oxide film in a region other than the lower part of the gate electrode is shaved, and at the same time, the gate oxide film at the side wall end of the gate electrode is isotropically etched to cause an undercut. Then, problems such as a decrease in the breakdown voltage of the gate electrode occur. Therefore, in order to improve the profile of the undercut gate electrode side wall end portion, a so-called light oxidation process is performed in which the substrate is once again thermally oxidized to form an oxide film on the surface thereof.

  However, the above-described refractory metals such as W and Mo are materials that are very easily oxidized in a high-temperature oxygen atmosphere. Therefore, when the above light oxidation treatment is applied to the gate electrode having a polymetal structure, the refractory metal film is oxidized. As a result, the resistance value increases or a part of the resistance value peels off from the substrate. Therefore, in the gate processing process using polymetal, it is necessary to take measures to prevent the refractory metal film from being oxidized during the light oxidation process.

  Patent Document 2 (Japanese Patent Laid-Open No. 59-132136) discloses that after forming a gate electrode having a polymetal structure including a W film or a Mo film on a Si (silicon) substrate, light oxidation is performed in a mixed atmosphere of water vapor and hydrogen. By doing so, a technique for selectively oxidizing only Si without oxidizing the W (Mo) film is disclosed. This is based on the fact that the water vapor / hydrogen partial pressure ratio at which the oxidation-reduction reaction is in equilibrium is different between W (Mo) and Si. This partial pressure ratio coexists even if W (Mo) is oxidized by water vapor. Although it is rapidly reduced by hydrogen, Si is selectively oxidized by setting it within a range in which Si remains oxidized. The mixed atmosphere of water vapor and hydrogen is generated by a bubbling method in which hydrogen gas is supplied into pure water contained in a container, and the water vapor / hydrogen partial pressure ratio is controlled by changing the temperature of pure water.

Patent Document 3 (Japanese Patent Laid-Open No. 3-119763) and Patent Document 4 (Japanese Patent Laid-Open No. 7-94716) describe a metal nitride layer such as TiN and a metal layer such as W on a Si substrate via a gate oxide film. A technique is disclosed in which light oxidation is performed in an atmosphere in which a reducing gas (hydrogen) and an oxidizing gas (water vapor) are diluted with nitrogen after forming a polymetal-structured gate electrode. According to these publications, only Si can be selectively oxidized without oxidizing the metal layer, and the denitrification reaction from the metal nitride layer is prevented by diluting the water vapor / hydrogen mixed gas with nitrogen. Therefore, it is said that oxidation of the metal nitride layer can be prevented at the same time.
JP-A-5-152282 JP 59-132136 A Japanese Patent Laid-Open No. 3-119963 JP-A-7-94716

  As described above, in the process of forming a gate electrode having a polymetal structure, light oxidation is performed in a steam / hydrogen mixed gas having a predetermined partial pressure ratio, thereby improving the breakdown voltage of the gate oxide film and preventing oxidation of the metal film. It becomes an effective means.

  However, the conventional bubbling method proposed as a method for generating a steam / hydrogen mixed gas supplies the hydrogen gas into the pure water pumped in the container to generate the steam / hydrogen mixed gas. There is a possibility that foreign matter mixed in water is sent to the oxidation furnace together with the water vapor / hydrogen mixed gas to contaminate the semiconductor wafer.

  In the bubbling method, the water vapor / hydrogen partial pressure ratio is controlled by changing the temperature of pure water. (1) The partial pressure ratio is likely to fluctuate, and it is difficult to accurately realize the optimum partial pressure ratio. 2) There is a problem that the control range of the water vapor concentration is as narrow as several percent to several tens of percent, and it is difficult to realize a water vapor concentration on the order of ppm.

  As will be described later, in the oxidation-reduction reaction of Si or metal using a steam / hydrogen mixed gas, the oxidation reaction proceeds more easily as the water vapor concentration is higher. Therefore, when Si is oxidized under a relatively high water vapor concentration, such as a water vapor / hydrogen mixed gas generated by a bubbling method, an oxide film grows in a very short time because the oxidation rate is high. However, a fine MOSFET with a gate length of 0.25 μm or less is required to form a gate oxide film with a very thin film thickness of 5 nm or less in order to maintain the electrical characteristics of the device. Accordingly, it is difficult to form such an extremely thin gate oxide film uniformly and with good controllability by using a vapor / hydrogen mixed gas generated by a bubbling method. Further, if the oxidation is performed at a low temperature (for example, 800 ° C. or lower) in order to reduce the growth rate of the oxide film, a high-quality gate oxide film cannot be obtained.

  The object of the present invention is to prevent the metal film from being oxidized during the light oxidation process after patterning the gate electrode in the gate processing process using polymetal, and to reproduce the oxide film formation at the side wall end of the gate electrode. It is an object of the present invention to provide a technique capable of controlling the uniformity and uniformity of the oxide film thickness.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A manufacturing method of a semiconductor integrated circuit device which is one invention of the present application,
(A) forming a polycrystalline silicon film on a gate insulating film including a silicon oxide film formed on the silicon surface of the wafer;
(B) forming a refractory metal film made of tungsten or molybdenum on the polycrystalline silicon film through a barrier layer made of tungsten nitride;
(C) forming a gate electrode by patterning the polycrystalline silicon film and the refractory metal film;
(D) After the step (c), the refractory metal film and the barrier are contained in a gas atmosphere containing hydrogen and water vapor generated from hydrogen and oxygen by catalytic action and substantially free of hydrogen radicals. A step of thermally oxidizing the polycrystalline silicon film without oxidizing the layer,
In the step (d), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
After the introduction of hydrogen into the gas generator is started, the introduction of oxygen into the gas generator is started.

The outline of the invention other than the above-described invention of the present application is as follows.
(1) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, after depositing a conductive film including at least a metal film on a gate oxide film formed on a main surface of a semiconductor substrate, the conductive film is patterned to form a MOSFET. A step of forming a gate electrode, and supplying hydrogen gas containing water vapor generated from hydrogen and oxygen by catalytic action to or near the main surface of the semiconductor substrate heated to a predetermined temperature, and the main surface of the semiconductor substrate Improving the profile of the side wall end of the gate electrode by selectively oxidizing the gate electrode.
(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, the conductive film includes at least a W film or a Ti film.
(3) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the water vapor / hydrogen partial pressure ratio of the hydrogen gas containing water vapor is set within a range in which the metal film is reduced and the main surface of the semiconductor substrate is oxidized. To do.
(4) The method for manufacturing a semiconductor integrated circuit device according to the present invention is such that the conductive film includes at least a Ti film, and the hydrogen gas includes a low concentration of water vapor that minimizes deterioration of the gate electrode due to oxidation of the Ti film. Is used to selectively oxidize the main surface of the semiconductor substrate.
(5) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the conductive film includes at least a W film, and uses hydrogen gas containing water vapor at a low concentration so that the oxidation rate and the oxide film thickness can be controlled. The main surface of the semiconductor substrate is selectively oxidized.
(6) In the method for manufacturing a semiconductor integrated circuit device of the present invention, after depositing a conductive film including at least a metal film on a gate oxide film having a thickness of 5 nm or less formed on the main surface of the semiconductor substrate, the conductive film A low concentration of water vapor that is generated from hydrogen and oxygen by catalysis and can control the reproducibility of oxide film formation and the uniformity of the oxide film thickness. A hydrogen gas containing hydrogen is supplied to or near the main surface of the semiconductor substrate heated to a predetermined temperature, and the main surface of the semiconductor substrate is selectively oxidized to obtain a profile of the side wall end of the gate electrode. Process to improve.
(7) The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps (a) to (d).
(A) a step of depositing a conductive film including at least a metal film on the gate oxide film after thermally oxidizing the semiconductor substrate to form a gate oxide film on a main surface thereof;
(B) forming the gate electrode of the MOSFET by patterning the conductive film by dry etching using a photoresist film as a mask;
(C) after removing the photoresist film, wet etching the main surface of the semiconductor substrate;
(D) The water vapor / hydrogen partial pressure ratio of hydrogen gas containing water vapor generated from hydrogen and oxygen by catalysis is set within a range in which the metal film is reduced and the main surface of the semiconductor substrate is oxidized. The hydrogen gas containing water vapor was damaged by the wet etching by supplying the hydrogen gas containing water vapor to the main surface of the semiconductor substrate heated to a predetermined temperature or in the vicinity thereof to selectively oxidize the main surface of the semiconductor substrate. Improving the profile of the side wall end of the gate electrode.
(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the conductive film is deposited on a polycrystalline silicon film, a metal nitride film deposited on the polycrystalline silicon film, and on the metal nitride film. It consists of a metal film.
(9) In the method of manufacturing a semiconductor integrated circuit device of the present invention, the metal nitride film is made of WN or TiN, and the metal film is made of W, Mo, or Ti.
(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the gate length of the gate electrode is 0.25 μm or less.
(11) In the method of manufacturing a semiconductor integrated circuit device of the present invention, the gate electrode is a gate electrode of a memory cell selection MISFET constituting a memory cell of a DRAM.
(12) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the heating temperature of the semiconductor substrate is 800 to 900 ° C.
(13) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the main surface of the semiconductor substrate is selectively oxidized by single wafer processing.
(14) In the method of manufacturing a semiconductor integrated circuit device of the present invention, selective oxidation of the main surface of the semiconductor substrate is performed by batch processing.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the gate processing process using polymetal, it is possible to prevent the metal film from being oxidized during the light oxidation process after gate patterning, and the reproducibility of the oxide film formation at the edge of the gate sidewall and the uniformity of the oxide film thickness Can be controlled well.

  As a result, a high-quality ultrathin gate oxide film with improved breakdown voltage, particularly with a film thickness of 5 nm or less, can be formed with a uniform film thickness and good reproducibility, so that the gate length is 0.25 μm or less. It is possible to improve the reliability and manufacturing yield of a device that forms a circuit with a simple MOSFET.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is an equivalent circuit diagram of the DRAM of the present embodiment. As shown in the figure, this DRAM memory array (MARY) has a plurality of word lines WL (WLn-1, WLn, WLn + 1...) And a plurality of bit lines BL arranged in a matrix, and intersections thereof. And a plurality of arranged memory cells (MC). One memory cell for storing 1-bit information is composed of one information storage capacitor element C and one memory cell selection MISFET Qs connected in series therewith. One of the source and drain of the MISFET Qs is electrically connected to the information storage capacitor element C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to the word driver WD, and one end of the bit line BL is connected to the sense amplifier SA.

  Hereinafter, a method of manufacturing the DRAM according to the present embodiment will be described with reference to FIGS. 2 to 8 and FIGS. 14 to 24 are cross-sectional views of a semiconductor substrate showing a part of a memory array (MARY) and a peripheral circuit (for example, sense amplifier SA), and FIGS. 9 and 10 are diagrams for a write oxidation process. FIG. 11 is a schematic view of a single-wafer oxidation furnace to be used, FIG. 11 is a schematic view of a catalytic steam / hydrogen mixed gas generator connected to a chamber of the single-wafer oxidation furnace, and FIG. 12 is a schematic view of a steam / hydrogen mixed gas. FIG. 13 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio of the oxidation-reduction reaction used, and FIG. 13 is a diagram showing a light oxidation process sequence using a single wafer oxidation furnace. In addition, numerical values, such as a film thickness shown in the following description, are illustrations, and are not for limiting the present invention.

  First, as shown in FIG. 2, a semiconductor substrate 1 made of single crystal silicon having a specific resistance of about 10 Ωcm is heat-treated to form a thin silicon oxide film 2 (pad oxide film) having a thickness of about 10 nm on its main surface. Next, after depositing a silicon nitride film 3 having a thickness of about 100 nm on the silicon oxide film 2 by a CVD (Chemical Vapor Deposition) method, the silicon nitride film 3 in the element isolation region is removed by etching using a photoresist film as a mask. . The silicon oxide film 2 is formed for the purpose of alleviating stress applied to the substrate when a silicon oxide film embedded in the element isolation trench is sintered (baked) in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface in the lower part (active region).

  Next, as shown in FIG. 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the silicon nitride film 3 as a mask, so that a trench having a depth of about 300 to 400 nm is formed in the semiconductor substrate 1 in the element isolation region. 4a is formed.

  Next, as shown in FIG. 4, in order to remove the damaged layer formed on the inner wall of the groove 4a by the etching, the semiconductor substrate 1 is heat-treated to form a silicon oxide film 5 having a thickness of about 10 nm on the inner wall of the groove 4a. After the formation, a silicon oxide film 6 is deposited on the semiconductor substrate 1 by a CVD method, and then the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 6 in order to improve the film quality of the silicon oxide film 6. To do. Thereafter, the element isolation trench 4 is formed by polishing the silicon oxide film 6 by chemical mechanical polishing (CMP) using the silicon nitride film 3 as a stopper and leaving it inside the trench 4a.

  Next, after removing the silicon nitride film 3 remaining on the semiconductor substrate 1 by wet etching using hot phosphoric acid, a region (memory array) for forming a memory cell on the semiconductor substrate 1 is formed as shown in FIG. B (boron) is ion-implanted into a region for forming a part of the peripheral circuit (n-channel type MISFETQn) to form the p-type well 7, and a region for forming another part of the peripheral circuit (p-channel type MISFETQp) N-type well 8 is formed by ion implantation of P (phosphorus).

  Next, as shown in FIG. 6, after removing the silicon oxide film 2 on each surface of the p-type well 7 and the n-type well 8 using an HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized. A clean gate oxide film 9 having a thickness of about 5 nm is formed on each surface of the p-type well 7 and the n-type well 8.

Although not particularly limited, after the gate oxide film 9 is formed, the semiconductor substrate 1 is heat-treated in an NO (nitrogen oxide) or N 2 O (nitrous oxide) atmosphere to thereby form the gate oxide film 9 and the semiconductor substrate 1. An oxynitriding treatment for segregating nitrogen may be performed at the interface between the two layers. When the gate oxide film 9 is thinned to about 5 nm, the distortion generated at the interface between the two due to the difference in thermal expansion coefficient with the semiconductor substrate 1 becomes obvious and induces the generation of hot carriers. Since nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion, the above oxynitriding treatment can improve the reliability of the ultrathin gate oxide film 9.

  Next, as shown in FIG. 7, a gate electrode 14A (word line WL) and gate electrodes 14B and 14C having a gate length of about 0.25 μm are formed on the gate oxide film 9. As the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film 10 having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) is deposited on the semiconductor substrate 1 by the CVD method. Next, a WN film 11 having a thickness of about 30 nm and a W film 12 having a thickness of about 100 nm are deposited on the upper portion by sputtering, and a silicon nitride film 13 having a thickness of about 150 nm is further deposited on the upper portion by CVD. Thereafter, these films are patterned by using a photoresist as a mask.

  When a part of the gate electrode 14A (word line WL) is made of a low-resistance metal (W), the sheet resistance can be reduced to about 2Ω / □, so that the word line delay can be reduced. In addition, since the word line delay can be reduced without lining the gate electrode 14 (word line WL) with Al wiring or the like, the number of wiring layers formed on the upper part of the memory cell can be reduced by one.

  Thereafter, the photoresist is removed by ashing (ashing), and further, dry etching residues and ashing residues remaining on the surface of the semiconductor substrate 1 are removed using an etchant such as hydrofluoric acid. When this wet etching is performed, as shown in FIG. 8, the gate electrode 14A (word line WL) and the gate oxide film 9 in a region other than the lower portions of the gate electrodes 14B and 14C (not shown) are simultaneously removed, and at the same time, the lower portion of the gate sidewall is removed. Since the gate oxide film 9 is also isotropically etched and undercut occurs, there arises a problem such that the breakdown voltage of the gate oxide film 9 is lowered as it is. Therefore, in order to regenerate the shaved gate oxide film 9, re-oxidation (light oxidation) treatment is performed by the following method.

  FIG. 9A is a schematic plan view showing an example of a specific configuration of the single wafer oxidation furnace used for the light oxidation treatment, and FIG. 9B is a BB ′ line in FIG. 9A. FIG.

  The single-wafer oxidation furnace 100 includes a chamber 101 composed of a multi-wall quartz tube, and heaters 102a and 102b for heating the semiconductor wafer 1A are installed at the upper and lower portions thereof. Housed in the chamber 101 is a disc-shaped heat equalizing ring 103 that uniformly distributes the heat supplied from the heaters 102a and 102b over the entire surface of the semiconductor wafer 1A, and holds the semiconductor wafer 1A horizontally on the upper portion thereof. A susceptor 104 is placed. The soaking ring 103 is made of a heat-resistant material such as quartz or SiC (silicon carbide), and is supported by a support arm 105 extending from the wall surface of the chamber 101. A thermocouple 106 that measures the temperature of the semiconductor wafer 1 </ b> A held by the susceptor 104 is installed near the soaking ring 103. For heating the semiconductor wafer 1A, for example, a heating method using a lamp 107 as shown in FIG. 10 may be adopted in addition to a heating method using the heaters 102a and 102b.

  One end of a gas introduction pipe 108 for introducing a steam / hydrogen mixed gas and a purge gas into the chamber 101 is connected to a part of the wall surface of the chamber 101. The other end of the gas introduction pipe 108 is connected to a catalyst-type gas generator described later. A partition 110 having a large number of through holes 109 is provided in the vicinity of the gas introduction pipe 108, and the gas introduced into the chamber 101 passes through the through holes 109 of the partition 110 and enters the chamber 101. Spread evenly. One end of an exhaust pipe 111 for discharging the gas introduced into the chamber 101 is connected to the other part of the wall surface of the chamber 101.

  FIG. 11 is a schematic view showing a catalytic steam / hydrogen mixed gas generator connected to the chamber 101 of the single wafer oxidation furnace 100. The gas generator 140 includes a reactor 141 made of a heat-resistant and corrosion-resistant alloy (for example, Ni alloy known as a trade name “Hastelloy”), and contains Pt (platinum), Ni ( A coil 142 made of a catalytic metal such as nickel) or Pd (palladium) and a heater 143 for heating the coil 142 are accommodated.

  A process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen or Ar (argon) are introduced into the reactor 141 from a gas storage tank 144a, 144b, 144c through a pipe 145. Between the gas storage tanks 144a, 144b, 144c and the pipe 145, mass flow controllers 146a, 146b, 146c for adjusting the amount of gas and open / close valves 147a, 147b, 147c for opening and closing the gas flow path are installed. The amount and component ratio of the gas introduced into the reactor 141 are precisely controlled thereby.

The process gas (hydrogen and oxygen) introduced into the reactor 141 is excited in contact with the coil 142 heated to about 350 to 450 ° C., and hydrogen radicals are generated from hydrogen molecules (H 2 → 2H *). ), Oxygen radicals are generated from oxygen molecules (O 2 → 2O *). Since these two radicals are chemically very active, they react quickly to produce water (2H * + O * → H 2 O). Therefore, by introducing a process gas containing hydrogen in excess of the molar ratio (hydrogen: oxygen = 2: 1) generated by water (steam) into the reactor 141, a steam / hydrogen mixed gas is generated. This mixed gas is introduced into the chamber 101 of the single wafer oxidation furnace 100 through the gas introduction pipe 108.

  The catalytic gas generator 140 as described above can control the amount of hydrogen and oxygen involved in the generation of water and the ratio thereof with high accuracy, so that the water vapor in the water vapor / hydrogen mixed gas introduced into the chamber 101 can be controlled. The concentration can be controlled over a wide range and with high accuracy from a very low concentration of the order of ppm to a high concentration of about several tens of percent. Further, when process gas is introduced into the reactor 141, water is instantly generated, so that a water vapor / hydrogen mixed gas having a desired water vapor concentration can be obtained in real time. This also minimizes contamination by foreign substances, so that a clean steam / hydrogen mixed gas can be introduced into the chamber 101. Note that the catalyst metal in the reactor 141 is not limited to the metals described above as long as hydrogen and oxygen can be radicalized. Further, the catalyst metal may be processed into a coil shape and used, for example, processed into a hollow tube or a fine fiber filter, and the process gas may be passed through the inside.

FIG. 12 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio (P H2O / P H2 ) of the oxidation-reduction reaction using a steam / hydrogen mixed gas, and the curves (a) to (e) in the figure are respectively The equilibrium vapor pressure ratios of W, Mo, Ta (tantalum), Si, and Ti are shown.

  As shown in the figure, the steam / hydrogen partial pressure ratio of the steam / hydrogen mixed gas introduced into the chamber 101 of the single-wafer oxidation furnace 100 is set within a range between the curves (a) and (d). As a result, only Si is selectively oxidized without oxidizing the W film 12 constituting the gate electrode 14A (word line WL) and part of the gate electrodes 14B and 14C and the WN film 11 serving as a barrier layer. Can do. As shown in the figure, the oxidation rate of the metals (W, Mo, Ta, Ti) and Si decreases as the water vapor concentration in the water vapor / hydrogen mixed gas decreases. Therefore, by reducing the water vapor concentration in the water vapor / hydrogen mixed gas, the oxidation rate and the oxide film thickness of Si can be easily controlled.

  Similarly, when a part of the gate electrode is composed of the Mo film, the Mo film is set by setting the water vapor / hydrogen partial pressure ratio within the range between the curves (b) and (d). Only Si can be selectively oxidized without oxidizing. In addition, when a part of the gate electrode is composed of a Ta film, the Ta film is formed by setting the water vapor / hydrogen partial pressure ratio within the range between the curves (c) and (d). Only Si can be selectively oxidized without oxidizing.

  On the other hand, as shown in the figure, Ti has a higher oxidation rate than Si in a water vapor / hydrogen mixed gas atmosphere, so when a part of the gate electrode is composed of a Ti film or the barrier layer is composed of a TiN film However, only Si cannot be selectively oxidized without oxidizing the Ti film or the TiN film. However, also in this case, by setting the water vapor in the water vapor / hydrogen mixed gas to a very low concentration, the oxidation rate and the oxide film thickness of the Ti film, TiN film and Si can be easily controlled. The oxidation of the film and the TiN film can be minimized, and the deterioration of the characteristics of the gate electrode can be suppressed within a range that does not cause a problem in practice. Specifically, the upper limit of the water vapor concentration is desirably about 1% or less, and a certain amount of water vapor is required to improve the profile of the side wall end of the gate electrode, so the lower limit is about 10 ppm to 100 ppm. Is desirable.

  Next, an example of a light oxidation process sequence using the single wafer oxidation furnace 100 will be described with reference to FIG.

  First, the chamber 101 of the single wafer oxidation furnace 100 is opened, and the semiconductor wafer 1A is loaded on the susceptor 104 while introducing purge gas (nitrogen) into the chamber 101. Thereafter, the chamber 101 is closed, and the purge gas is subsequently introduced to sufficiently exchange the gas in the chamber 101. The susceptor 104 is previously heated by the heaters 102a and 102b so that the semiconductor wafer 1A is heated quickly. The heating temperature of the semiconductor wafer 1A is in the range of 800 to 900 ° C., for example, 850 ° C. When the wafer temperature is 800 ° C. or lower, the quality of the silicon oxide film is deteriorated. On the other hand, when the temperature is 900 ° C. or higher, surface roughness of the wafer tends to occur.

  Next, hydrogen is introduced into the chamber 101 and nitrogen is discharged. If nitrogen remains in the chamber 101, an undesired nitriding reaction may occur. Therefore, it is desirable to exhaust the nitrogen completely.

  Next, oxygen and excess hydrogen are introduced into the reactor 141 of the gas generator 140, and water generated from the oxygen and hydrogen by the catalytic action is introduced into the chamber 101 together with excess hydrogen, so that the surface of the semiconductor wafer 1A is covered. Oxidizes for a predetermined time. As a result, the gate oxide film 9 that has been thinned by the wet etching is re-oxidized, and the profile of the side walls of the undercut gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is improved. .

  If the above light oxidation is performed for a long time, the oxide film thickness near the gate electrode end becomes thicker than necessary, an offset occurs at the gate electrode end, and the threshold voltage (Vth) of the MOSFET deviates from the design value. Or There is also a problem that the effective channel length is shorter than the processed value of the gate electrode. In particular, in a fine MOSFET having a gate length of about 0.25 μm, the allowable amount of thinning from the design value of the gate processing dimension is severely limited from the viewpoint of device design. This is because even if the thinning amount is slightly increased, the threshold voltage is rapidly decreased by the short channel effect. In the case of a gate electrode having a gate length of around 0.25 μm, the degree to which the side wall end portion of the polycrystalline silicon film constituting a part is oxidized by about 0.1 μm (about 0.2 μm at both ends) in the light oxidation step, This is considered to be a limit that does not cause a rapid decrease in the threshold voltage. Therefore, it is desirable that the upper limit of the oxide film thickness grown by light oxidation be about 50% of the gate oxide film thickness.

  Next, after introducing a purge gas (nitrogen) into the chamber 101 and discharging the steam / hydrogen mixed gas, the chamber 101 is opened, and the semiconductor wafer 1A is unloaded from the susceptor 104 while introducing the purge gas into the chamber 101. Thus, the light oxidation process ends.

Hereinafter, the DRAM process after the light oxidation process will be briefly described. First, as shown in FIG. 14, a p - type semiconductor region 16 is formed in the n-type well 8 on both sides of the gate electrode 14C by ion-implanting a p-type impurity such as B (boron) into the n-type well 8. Further, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 7 to form n -type semiconductor regions 17 in the p-type well 7 on both sides of the gate electrode 14B. An n-type semiconductor region 18 is formed in the well 7.

  Next, as shown in FIG. 15, after depositing a silicon nitride film 19 on the semiconductor substrate 1 by the CVD method, the memory array is covered with a photoresist film 20 as shown in FIG. Sidewall spacers 19a are formed on the side walls of the gate electrodes 14B and 14C by anisotropically etching 19. This etching minimizes the amount of overetching in order to minimize the amount of etching of the silicon oxide film 6 embedded in the element isolation trench 4 and the silicon nitride film 19 on the gate electrodes 14B and 14C. The etching is performed using an etching gas that can have a large selectivity with respect to the silicon oxide film 6.

Next, as shown in FIG. 17, an n type impurity, for example, As (arsenic) is ion-implanted into the p type well 7 of the peripheral circuit to form an n + type semiconductor region 21 (source, drain) of the n channel type MISFET Qn. Then, a p-type impurity, for example, B (boron) is ion-implanted into the n-type well 2 to form the p + -type semiconductor region 22 (source, drain) of the p-channel type MISFET Qp.

  Next, as shown in FIG. 18, a silicon oxide film 23 is deposited on the semiconductor substrate 1 by the CVD method, and the surface thereof is flattened by using a chemical mechanical polishing method, and then the photoresist film 24 is used as a mask. The silicon oxide film 23 above the n-type semiconductor region 18 (source, drain) of the memory cell selection MISFETQs is removed by dry etching. This etching is performed under the condition that the etching rate of the silicon oxide film 23 with respect to the silicon nitride films 13 and 19 is increased so that the silicon nitride film 19 on the n-type semiconductor region 18 is not removed.

  Next, as shown in FIG. 19, the silicon nitride film 19 and the gate oxide film 9 above the n-type semiconductor region 18 (source, drain) of the memory cell selection MISFET Qs are formed by dry etching using the photoresist film 24 as a mask. As a result, the contact hole 25 is formed above one of the source and drain (n-type semiconductor region 18), and the contact hole 26 is formed above the other (n-type semiconductor region 18). This etching uses an etching gas that minimizes the amount of overetching and minimizes the amount of overetching of the semiconductor substrate 1 and that allows a large selection ratio with respect to the semiconductor substrate 1 (silicon). This etching is performed under the condition that the silicon nitride film 19 is anisotropically etched so that the silicon nitride film 19 remains on the side wall of the gate electrode 14A (word line WL). In this way, the contact holes 25 and 26 are formed in self alignment with the gate electrode 14A (word line WL). In order to form the contact holes 25 and 26 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 19 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

  Next, as shown in FIG. 20, after plugs 27 are buried in the contact holes 25 and 26, a silicon oxide film 28 is deposited on the silicon oxide film 23 by the CVD method, and then the photoresist film 29 is masked. The silicon oxide film 28 above the contact hole 25 is removed by dry etching. In order to embed the plugs 27 in the contact holes 25 and 26, a polycrystalline silicon film doped with P (phosphorus) is deposited on the silicon oxide film 23 by the CVD method, and then the polycrystalline silicon film is subjected to chemical mechanical processing. The polycrystalline silicon film on the silicon oxide film 23 is removed by polishing using a polishing method. Part of P (phosphorus) in the polycrystalline silicon film diffuses from the bottom of the contact holes 25 and 26 into the n-type semiconductor region 18 (source and drain) in a later high-temperature process. Make resistance.

Next, as shown in FIG. 21, by removing the peripheral circuit type silicon oxide films 28 and 23 and the gate oxide film 9 by dry etching using the photoresist film 30 as a mask, the source of the n-channel type MISFET Qn, Contact holes 31 and 32 are formed above the drain (n + type semiconductor region 21), and contact holes 33 and 34 are formed above the source and drain (p + type semiconductor region 22) of the p-channel type MISFET Qp. This etching is performed under the condition that the etching rate of the silicon oxide film with respect to the silicon nitride film 13 and the side wall spacer 19a is increased, and the contact holes 31 and 32 are formed in self-alignment with the gate electrode 14B. , 34 are formed in a self-aligned manner with respect to the gate electrode 14C.

  Next, as shown in FIG. 22, the bit line BL and the first layer wirings 35 and 36 of the peripheral circuit are formed on the silicon oxide film 28. For the bit line BL and the first layer wirings 35 and 36, for example, a TiN film and a W film are deposited on the silicon oxide film 28 by sputtering, and then a silicon oxide film 37 is deposited on the W film by CVD. Then, these films are sequentially patterned by etching using a photoresist film as a mask.

  Next, as shown in FIG. 23, a silicon oxide film 38 is deposited by CVD on the bit line BL and the first layer wirings 35 and 36, and the upper part of the contact hole 26 by dry etching using a photoresist film as a mask. After removing the silicon oxide films 38 and 28 to form a through hole 39, a plug 40 is embedded in the through hole 39. The plug 40 is formed, for example, by depositing a W film on the silicon oxide film 38 by a sputtering method and then polishing the W film by a chemical mechanical polishing method to leave the inside of the through hole 39.

  Next, as shown in FIG. 24, an information storage capacitive element C having a laminated structure of a lower electrode 41, a capacitive insulating film 42, and an upper electrode 43 is formed above the through hole 39, thereby forming a memory cell. A DRAM memory cell composed of the selection MISFET Qs and the information storage capacitor C connected in series with the selection MISFET Qs is substantially completed. The lower electrode 41 of the information storage capacitive element C is formed, for example, by depositing a W film on the silicon oxide film 38 by CVD or sputtering, and patterning this W film by dry etching using a photoresist film as a mask. To do. The capacitor insulating film 42 and the upper electrode 43 are formed by depositing a tantalum oxide film on the upper part of the lower electrode 41 by CVD or sputtering, depositing a TiN film on the upper part by sputtering, and then etching using a photoresist film as a mask. These films are formed by patterning sequentially. Thereafter, about two layers of Al wiring are formed on the upper part of the information storage capacitive element C, but they are not shown.

  The above-described light oxidation treatment of the gate oxide film can be performed by attaching the above-described catalytic steam / hydrogen mixed gas generator 140 to a batch type vertical oxidation furnace 150 as shown in FIG. An example of a sequence of a light oxidation process using the batch type vertical oxidation furnace 150 is shown in FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the write oxidation processing of the MOSFETs constituting the DRAM memory cell and the peripheral circuit has been described. However, the present invention is not limited to this, and an extremely thin gate oxide film having a thickness of 5 nm or less is particularly limited. Is suitable for light oxidation treatment of various devices that constitute a circuit with fine MOSFETs that are required to be uniformly formed with good reproducibility.

  The present invention can be applied to a method of manufacturing a semiconductor integrated circuit device including a MOSFET having a polymetal gate.

1 is an equivalent circuit diagram of a DRAM according to an embodiment of the present invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. (A) is a schematic plan view of the single wafer type oxidation furnace used for a light oxidation process, (b) is sectional drawing along the B-B 'line of (a). (A) is a schematic plan view of the single wafer type oxidation furnace used for a light oxidation process, (b) is sectional drawing along the B-B 'line of (a). 1 is a schematic view of a catalytic steam / hydrogen mixed gas generator. It is a graph which shows the temperature dependence of the equilibrium vapor pressure ratio of the oxidation-reduction reaction using water vapor / hydrogen mixed gas. It is a figure which shows the sequence of the light oxidation process using a single wafer type oxidation furnace. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of DRAM which is one embodiment of this invention. It is the schematic of a batch type vertical oxidation furnace used for light oxidation treatment. It is a figure which shows the sequence of the light oxidation process using a batch type vertical oxidation furnace.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Semiconductor wafer 2 Silicon oxide film (pad oxide film)
3 Silicon nitride film 4 Element isolation trench 4a Groove 5 Silicon oxide film 6 Silicon oxide film 7 P-type well 8 N-type well 9 Gate oxide film 10 Polycrystalline silicon film 11 WN film 12 W film 13 Silicon nitride films 14A to 14C Gate electrodes 16 p type semiconductor region 17 n type semiconductor region 18 n type semiconductor region 19 silicon nitride film 19a sidewall spacer 20 photoresist film 21 p + type semiconductor region 22 n + type semiconductor region 23 silicon oxide film 24 photoresist film 25 Contact hole 26 Contact hole 27 Plug 28 Silicon oxide film 29 Photoresist film 30 Photoresist films 31 to 34 Contact holes 35 and 36 First layer wiring 37 Silicon oxide film 38 Silicon oxide film 39 Through hole 40 Plug 41 Lower electrode 42 Capacitance insulation On membrane 43 Electrode 100 Single wafer oxidation furnace 101 Chamber 102a, 102b Heater 103 Heat equalizing ring 104 Susceptor 105 Support arm 106 Thermocouple 107 Lamp 108 Gas introduction pipe 109 Through hole 110 Partition 111 Exhaust pipe 140 Gas generator 141 Reactor 142 Coil 143 Heater 144a to 144c Gas storage tank 145 Piping 146a to 146c Mass flow controllers 147a to 147c Open / close valve 150 Batch type vertical oxidation furnace BL Bit line C Information storage capacitor MARY Memory array Qn n-channel MOSFET
Qp p-channel MOSFET
Qs MISFET for memory cell selection
SA sense amplifier WD word driver WL word line

Claims (16)

  1. A method for manufacturing a semiconductor integrated circuit device, comprising:
    (A) forming a polycrystalline silicon film on a gate insulating film including a silicon oxide film formed on the silicon surface of the wafer;
    (B) forming a refractory metal film made of tungsten or molybdenum on the polycrystalline silicon film through a barrier layer made of tungsten nitride;
    (C) forming a gate electrode by patterning the polycrystalline silicon film and the refractory metal film;
    (D) After the step (c), in the gas atmosphere containing hydrogen and water vapor generated from hydrogen and oxygen by catalytic action and substantially free of hydrogen radicals, the refractory metal film and the barrier A step of thermally oxidizing the polycrystalline silicon film without oxidizing the layer,
    In the step (d), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
    A method of manufacturing a semiconductor integrated circuit device, comprising: starting introduction of oxygen into the gas generation device after starting introduction of hydrogen into the gas generation device.
  2.   The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas atmosphere does not contain nitrogen gas.
  3.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step (d), the wafer is heated in a temperature range of 800 to 900.degree.
  4. A method for manufacturing a semiconductor integrated circuit device, comprising:
    (A) forming a polycrystalline silicon film on a gate insulating film including a silicon oxide film having a thickness of 5 nm or less formed on the silicon surface of the main surface of the wafer;
    (B) forming a refractory metal film on the polycrystalline silicon film;
    (C) forming a gate electrode having a gate length of 0.25 μm or less by patterning the polycrystalline silicon film and the refractory metal film;
    (D) After the step (c), in the hydrogen gas atmosphere containing water vapor generated from hydrogen and oxygen by catalytic action, the polycrystalline silicon film is thermally oxidized without oxidizing the refractory metal film, The upper limit of the thickness of the oxide film grown by thermal oxidation is 50% of the thickness of the gate insulating film,
    In the step (d), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
    A method of manufacturing a semiconductor integrated circuit device, comprising: starting introduction of oxygen into the gas generation device after starting introduction of hydrogen into the gas generation device.
  5.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the hydrogen gas atmosphere does not contain nitrogen gas.
  6.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein in the step (d), the wafer is heated in a temperature range of 800.degree. C. to 900.degree.
  7. A method for manufacturing a semiconductor integrated circuit device, comprising:
    (A) forming a first polycrystalline silicon film on a gate insulating film including a silicon oxide film formed on the silicon surface of the main surface of the wafer;
    (B) forming a refractory metal film made of tungsten or molybdenum on the first polycrystalline silicon film through a barrier layer made of refractory metal nitride;
    (C) forming a gate electrode by patterning the first polycrystalline silicon film, the barrier layer, and the refractory metal film;
    (D) After the step (c), without oxidizing the refractory metal film in a hydrogen gas atmosphere containing water vapor generated from hydrogen and oxygen by catalytic action and substantially free of nitrogen gas, And thermally oxidizing the first polycrystalline silicon film,
    In step (d), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
    A method of manufacturing a semiconductor integrated circuit device, comprising: starting introduction of oxygen into the gas generation device after starting introduction of hydrogen into the gas generation device.
  8. A method for manufacturing a semiconductor integrated circuit device, comprising:
    (A) forming an element isolation groove on the silicon surface of the main surface of the wafer;
    (B) burying an insulating material in the element isolation trench;
    (C) After the step (b), a step of planarizing the main surface of the wafer by a chemical mechanical polishing method;
    (D) forming a polycrystalline silicon film on a gate insulating film mainly comprising a silicon oxide film having a thickness of 5 nm or less formed on the silicon surface of the wafer by thermal oxidation of the silicon surface;
    (E) forming a refractory metal film on the polycrystalline silicon film through a barrier layer;
    (F) patterning the polycrystalline silicon film and the refractory metal film to form a gate electrode having a gate length of 0.25 μm or less;
    (G) After the step (f), in a hydrogen gas atmosphere containing water vapor, the step of thermally oxidizing the polycrystalline silicon film without oxidizing the refractory metal film and the barrier layer. ,
    In the step ( g ), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
    A method of manufacturing a semiconductor integrated circuit device, comprising: starting introduction of oxygen into the gas generation device after starting introduction of hydrogen into the gas generation device.
  9.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the hydrogen gas atmosphere does not contain nitrogen gas.
  10.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein in the step (g), the wafer is heated in a temperature range of 800 to 900.degree.
  11. A method for manufacturing a semiconductor integrated circuit device, comprising:
    (A) forming a polycrystalline silicon film on the gate insulating film after forming a gate insulating film including a silicon oxide film and having a thickness of 5 nm or less on the silicon surface of the main surface of the wafer; ,
    (B) forming a refractory metal film made of tungsten on the polycrystalline silicon film through a barrier layer including a tungsten nitride film;
    (C) forming a gate electrode having a gate length of 0.25 μm or less by patterning the polycrystalline silicon film and the refractory metal film;
    (D) After the step (c), the refractory metal film and the barrier layer are oxidized without oxidizing the refractory metal film and the barrier layer in a gas atmosphere containing hydrogen and water vapor and substantially free of hydrogen radicals. A step of thermally oxidizing the crystalline silicon film,
    In the step (d), an oxidation furnace and a catalytic gas generator connected to the oxidation furnace are used, oxygen and hydrogen are introduced into the gas generator, and hydrogen and steam are introduced from the gas generator into the oxidation furnace. Is done,
    A method of manufacturing a semiconductor integrated circuit device, comprising: starting introduction of oxygen into the gas generation device after starting introduction of hydrogen into the gas generation device.
  12.   In the furnace where the polycrystalline silicon film is thermally oxidized without oxidizing the refractory metal film and the barrier layer, the furnace contains the hydrogen and the water vapor, and substantially does not contain hydrogen radicals. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of passing the gas atmosphere.
  13.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas atmosphere does not substantially contain hydrogen or oxygen radicals.
  14. In the furnace where the polycrystalline silicon film is thermally oxidized without oxidizing the refractory metal film and the barrier layer, the furnace contains the hydrogen and the water vapor, and substantially does not contain hydrogen radicals. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 11 , further comprising a step of passing the gas atmosphere.
  15. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 11 , wherein the gas atmosphere does not substantially contain hydrogen or oxygen radicals.
  16. The thickness of the oxide film and polycrystalline silicon film is grown by a step of thermal oxidation, according to claim 1, 7, 8 or 11 further characterized in that an upper limit of 50% more of the film thickness of the gate insulating film Of manufacturing a semiconductor integrated circuit device.
JP2006347647A 2006-12-25 2006-12-25 Manufacturing method of semiconductor integrated circuit device Expired - Lifetime JP4620654B2 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62198128A (en) * 1986-02-26 1987-09-01 Toshiba Corp Method and apparatus for forming silicon oxide film
JPH06115903A (en) * 1992-10-05 1994-04-26 Tadahiro Omi Water-generation method
JPH06333918A (en) * 1993-05-25 1994-12-02 Tadahiro Omi Formation of insulating oxide film and semiconductor device
JPH0964028A (en) * 1995-08-25 1997-03-07 Toshiba Corp Method and apparatus for manufacturing semiconductor device
WO1998039802A1 (en) * 1997-03-05 1998-09-11 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
JPH10335652A (en) * 1997-05-30 1998-12-18 Hitachi Ltd Manufacture of semiconductor integrated circuit device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62198128A (en) * 1986-02-26 1987-09-01 Toshiba Corp Method and apparatus for forming silicon oxide film
JPH06115903A (en) * 1992-10-05 1994-04-26 Tadahiro Omi Water-generation method
JPH06333918A (en) * 1993-05-25 1994-12-02 Tadahiro Omi Formation of insulating oxide film and semiconductor device
JPH0964028A (en) * 1995-08-25 1997-03-07 Toshiba Corp Method and apparatus for manufacturing semiconductor device
WO1998039802A1 (en) * 1997-03-05 1998-09-11 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
JPH10335652A (en) * 1997-05-30 1998-12-18 Hitachi Ltd Manufacture of semiconductor integrated circuit device

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