JP2000150803A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the temperature of the heat treatment required for the formation of a capacitor without degrading the characteristics of the capacitor in a method for manufacturing semiconductor device by which a semiconductor device provided with the capacitor is manufactured. SOLUTION: After the lower electrode 30 of a capacitor is formed, a nitride film is formed on the electrode 30 by the CVD method as the insulating film 32 of the capacitor. After the formation of the insulating film 32, the film 32 is oxidized in a wet state within the temperature range of 700-760 deg.C. Then the upper electrode 34 of the capacitor is formed on the insulating film 32. The process of forming the insulating film 32 includes a step of raising the temperature of a silicon wafer to the reactive temperature of the CVD method in an ammonia atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for miniaturizing a semiconductor device having a capacitor.

[0002]

2. Description of the Related Art FIG. 7 is a flowchart for explaining a conventional method for manufacturing a semiconductor device having a capacitor. In the conventional manufacturing method, first, on a silicon wafer,
A lower electrode film of the capacitor is formed (Step 1)
0). In this step, specifically, a process of depositing polysilicon containing phosphorus as an impurity on a silicon wafer by CVD is performed. Next, the lower electrode film is appropriately patterned by photolithography and dry etching to form a lower electrode of the capacitor (step 12).

A nitride film is formed on the lower electrode as a capacitor insulating film (step 14). In this step, specifically, dichlorosilane (SiH2Cl
Using 2) and ammonia (NH3) as raw materials, a process of depositing a nitride film on the upper portion of the lower electrode by CVD is performed. FIG. 8 shows a series of processes performed in the step of depositing an insulating film (nitride film). As shown in FIG. 8, in the insulating film deposition process, the evacuation of the reaction furnace, the process of raising the temperature of the silicon wafer, the process of forming a nitride film by CVD, and the purging process are continuously performed. In the conventional manufacturing method, the above-described evacuation, temperature raising, and purging are all performed in a nitrogen atmosphere.

When the formation of the insulating film is completed, next, wet oxidation is performed on the surface of the insulating film (step 16). The process (wet oxidation) in this step is performed for the purpose of repairing defects contained in the nitride film constituting the insulating film, improving the electrical characteristics of the capacitor, and increasing the reliability of the capacitor. In the conventional manufacturing method, the wet oxidation is performed by applying heat of about 800 ° C. to 900 ° C. to the silicon wafer in water vapor obtained by mixing hydrogen and oxygen.

In order to activate the impurities contained in the lower electrode, it is necessary to heat the silicon wafer. According to the conventional manufacturing method, the impurity of the lower electrode can be activated by the heat applied to the silicon wafer in the above-described wet oxidation process.

After the completion of the wet oxidation of the insulating film, an upper electrode film is formed on the insulating film (step 18). In the conventional manufacturing method, the upper electrode film is 5 ×
It is formed by depositing polysilicon containing phosphorus at a density of about 10 ²⁰ / cm ³ . After the upper electrode film is formed, the upper electrode film is appropriately patterned by photolithography and dry etching to form an upper electrode of the capacitor (Step 20).

Next, in order to sufficiently activate the impurities contained in the upper and lower electrodes, the silicon wafer is subjected to a heat treatment at a temperature in the range of 800 ° C. to 900 ° C. for about 30 minutes (step 22). ).

[0008]

A capacitor in a semiconductor device may be manufactured after a transistor is formed on a silicon wafer. Under such circumstances, when the above-described wet oxidation (step 16) and heat treatment (step 22) are performed in the process of manufacturing the capacitor, heat is applied to the vicinity of the transistor, and impurities implanted into each part of the transistor are removed. Spreading occurs. In particular, when a semiconductor device is miniaturized and a transistor is sufficiently miniaturized, the transistor may not be able to operate normally due to the diffusion.

In a semiconductor device such as a logic embedded memory, for example, in order to increase the operation speed,
Metal wiring (word line and
Bit line) may be provided. In this case, if a temperature exceeding the allowable temperature limit of the metal wiring is applied to the silicon wafer during the manufacturing process of the capacitor, a defect occurs in the metal wiring and the semiconductor device cannot operate.

For the reasons described above, in order to miniaturize a semiconductor device or operate it at a high speed, it is desirable that the temperature of the heat treatment performed in the manufacturing process of the capacitor be as low as possible. In this regard, the conventional method for manufacturing a semiconductor device still leaves room for improvement.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is intended to manufacture a semiconductor device capable of lowering the heat treatment temperature required for forming a capacitor without deteriorating the characteristics of the capacitor. The aim is to provide a method.

[0012]

According to the first aspect of the present invention,
A method of manufacturing a semiconductor device including a capacitor, comprising: forming a lower electrode of the capacitor; forming a nitride film by CVD as an insulating film of the capacitor on the lower electrode of the capacitor; After film formation, 70
A step of wet-oxidizing the insulating film within a temperature range of 0 ° C. to 760 ° C .; and a step of forming an upper electrode of a capacitor on the insulating film. The wafer is subjected to CV in an ammonia atmosphere.
D. A step of raising the temperature to the reaction temperature.

According to a second aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the first aspect, wherein the wet oxidation is performed by using steam having a flow ratio of hydrogen to oxygen in a range of 1.8: 1 to 1: 6. It is performed in an atmosphere.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a capacitor, comprising: forming a lower electrode of the capacitor;
A step of forming a nitride film by CVD as an insulating film of the capacitor; and 700 ° C. to 760 ° C. after forming the insulating film.
A step of performing annealing in an atmosphere containing an N2O gas within the temperature range described above, and a step of forming an upper electrode of a capacitor on the insulating film.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a capacitor, comprising: forming a lower electrode of the capacitor;
Forming an insulating film of a capacitor; and forming a film for forming an upper electrode of the capacitor on the insulating film by 8 ×
Depositing amorphous silicon having a phosphorus concentration of 10 ²⁰ atoms / cm ³ or more, and performing rapid thermal annealing at a temperature near 750 ° C. within 1 to 3 minutes after the deposition of the amorphous silicon; It is characterized by having.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to third aspects, the step of forming the upper electrode comprises forming an 8 ×
A step of depositing amorphous silicon having a phosphorus concentration of 10 ²⁰ / cm ³ or more, wherein rapid thermal annealing is performed at a temperature near 750 ° C. within a range of 1 to 3 minutes after the deposition of the amorphous silicon. It is characterized by the following.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals, and redundant description will be omitted.

Embodiment 1 FIG. 1 is a sectional view of a main part of a semiconductor device 10 manufactured by the manufacturing method according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 10 includes a silicon substrate 12. On the silicon substrate 12,
A plurality of isolation oxide films 14 for dividing the surface region into a plurality of regions and a plurality of diffusion layers 16 functioning as a source / drain of the transistor are provided.

On the silicon substrate 12, a gate oxide film 18, a word line 20, a data line 22, and the like are provided. Further, an interlayer insulating film 24
Is formed. The interlayer insulating film 24 is provided with a contact hole 26 opened in the diffusion layer 16 of the silicon substrate 12. Inside the contact hole 26, a contact 28 made of a conductive material such as doped polysilicon is provided.

The contact 2 is formed on the interlayer insulating film 24.
A lower electrode 30 electrically connected to the lower electrode 8 is formed.
The lower electrode 30 is made of doped polysilicon containing a predetermined concentration of phosphorus. The surface of the lower electrode 30 is covered with an insulating film 32. The insulating film 32 is composed of a silicon nitride film. An upper electrode 34 is formed on the insulating film 32. The lower electrode 30, the insulating film 32, and the upper electrode 34 constitute a capacitor inside the semiconductor device 10.

In the process of forming the lower electrode 30, the insulating film 32, and the upper electrode 34, that is, in the process of forming the capacitor, a process of heating the silicon wafer to a high temperature is performed as described later. When the silicon wafer is heated to a high temperature, impurities contained in the diffusion layer 16 and the channel region of the silicon substrate 12 diffuse to change the characteristics of the transistor. For this reason, it is desirable that the heat treatment applied to the silicon substrate during the manufacturing process of the capacitor be at a low temperature.
The manufacturing method of the present embodiment is characterized in that the temperature of the heat treatment in the manufacturing process of the capacitor can be reduced without deteriorating the characteristics of the capacitor.

Hereinafter, the contents of the manufacturing method of the present embodiment will be specifically described with reference to FIGS. FIG. 2 is a flowchart illustrating a main part of the method for manufacturing the semiconductor device 10 according to the present embodiment. In the manufacturing method of the present embodiment, a series of processes shown in FIG. 2 are executed to manufacture a capacitor.

In a series of processes shown in FIG. 2, first,
A lower electrode film of the capacitor is formed on the interlayer insulating film 24 (Step 10). In this step, specifically, a process of depositing polysilicon containing phosphorus as an impurity on a silicon wafer by CVD is performed. Next, the lower electrode film is appropriately patterned by photolithography and dry etching to form the lower electrode 30 of the capacitor (step 12).

A nitride film is formed on the lower electrode 30 as a capacitor insulating film 32 (step 36).
In this step, the insulating film 32 is formed by CVD using dichlorosilane (SiH2Cl2) and ammonia (NH3) as raw materials. FIG. 3 shows an insulating film 32.
A series of processes performed in a (nitride film) deposition process will be described.
As shown in FIG. 3, in the process of depositing the insulating film, the evacuation of the reactor, the process of raising the temperature of the silicon wafer, the process of forming a nitride film by CVD, and the purging process are continuously performed. The manufacturing method of the present embodiment includes, among those processes,
The silicon wafer is heated in an ammonia (NH3) atmosphere of about 0.4 Torr.

When the formation of the insulating film 32 is completed, the surface of the insulating film 32 is subjected to wet oxidation (step 3).
8). The process (wet oxidation) in this step is performed for the purpose of repairing defects contained in the nitride film constituting the insulating film, improving the electrical characteristics of the capacitor, and increasing the reliability of the capacitor. In the manufacturing method of the present embodiment, the wet oxidation is performed at 700 ° C. to 760 ° C.
The temperature is adjusted to a temperature range of about
This is performed by holding the silicon wafer in a furnace filled with steam obtained by mixing at a flow ratio of 8: 1 to 1: 6 for 60 minutes.

The above-mentioned wet oxidation temperature (700 ° C.
760 ° C.) is a temperature sufficiently lower than the temperature (820 ° C.) used in the conventional manufacturing method. Therefore,
According to the manufacturing method of the present embodiment, the heat load applied to the silicon wafer in the capacitor manufacturing process can be reduced as compared with the conventional manufacturing method. The above-described flow ratio of hydrogen to oxygen (1: 6) is a suitable ratio for appropriately oxidizing the surface of the insulating film 32. Therefore, according to the manufacturing method of the present embodiment, the insulating film 32 is oxidized to a suitable state, and a manufacturing process with excellent quality stability can be realized.

When the wet oxidation of the insulating film 32 is completed,
Next, an upper electrode film is formed on the insulating film 32 (Step 40). In the manufacturing method of the present embodiment, the upper electrode film is formed by depositing amorphous silicon containing phosphorus at a density of about 8 × 10 ²⁰ / cm ^{3 on} the insulating film 32 by CVD. In the manufacturing method of the present embodiment, the phosphorus concentration (8 ×
10 ²⁰ / cm ³ ) is a value sufficiently higher than the phosphorus concentration (5 × 10 ²⁰ / cm ³ ) applied to the upper electrode film by the conventional manufacturing method.

In manufacturing a semiconductor device industrially,
In some cases, it is required to simultaneously form an upper electrode film on more than 100 silicon wafers using a batch type CVD furnace. In such a case, if the upper electrode film 34 is formed by depositing doped polysilicon, it is difficult to obtain a phosphorus concentration as high as 8 × 10 ²⁰ / cm ³ . On the other hand, by depositing amorphous silicon as in the manufacturing method of the present embodiment, it is possible to obtain the above-mentioned high phosphorus concentration.

After the upper electrode film is formed, the upper electrode film is appropriately patterned by photolithography and dry etching to form an upper electrode 34 (step 20). Next, a heat treatment is performed on the silicon wafer in order to activate the impurities contained in the upper electrode 34 and the lower electrode 30. In the manufacturing method of the present embodiment,
As the heat treatment, a silicon wafer is subjected to RTA (Ra) for about 1 to 3 minutes at a temperature of about 750 ° C. in an N 2 atmosphere.
pid Thermal Anneal) is performed (step 42). The heat treatment conditions described above are conditions under which the heat load applied to the silicon wafer can be sufficiently suppressed as compared with the heat treatment conditions (800 ° C. to 900 ° C., 30 minutes) used in the conventional manufacturing method.

FIG. 4 shows the relationship between the semiconductor device manufacturing conditions and the TDDB life of the capacitor. Symbol (1) in FIG.
The point indicated by a symbol is the process of forming the insulating film 32 (step 3).
6) In the case where the process of raising the temperature of the silicon wafer to the CVD reaction temperature is performed in an N2 atmosphere and the wet oxidation of the insulating film 32 (step 38) is performed at a temperature of 820 ° C. (conventional conditions) Is shown). Points indicated by reference numeral (2) in FIG. 4 show the results when the temperature of the silicon wafer is raised in an N2 atmosphere and the wet oxidation is performed at a temperature of 760 ° C. Furthermore,
The point denoted by reference numeral (3) in FIG. 4 is a result when the temperature of the silicon wafer is raised in an NH3 atmosphere and the wet oxidation is performed at a temperature of 760 ° C. (the condition of the present embodiment). Is shown).

As shown by the results (1) and (2),
When the temperature rising atmosphere of the silicon wafer matches with N2,
As the temperature of the wet oxidation decreases from 820 ° C. to 760 ° C., the TDDB life is reduced to about 1/10. On the other hand, as shown in results (1) to (3), when the temperature rising atmosphere of the silicon wafer is changed from N2 to NH3, even if the temperature of wet oxidation is 760 ° C., the temperature becomes 820 ° C. It is possible to obtain a TDDB life equivalent to the case where the temperature is ° C.

As described above, if the temperature of the silicon wafer is raised in the NH3 atmosphere in the process of forming the insulating film 32, a sufficient TDDB life can be provided to the capacitor even when the temperature of wet oxidation is lowered. The TDDB life of the capacitor is as follows.
In the case of 3, it has been experimentally confirmed that a sufficient temperature can be ensured even when the temperature of wet oxidation is reduced to about 700 ° C.

As described above, in the manufacturing method of this embodiment,
In the process of forming the insulating film 32, the silicon wafer
While the temperature is raised in the atmosphere, wet oxidation of the insulating film 32 is performed in a temperature range of 700 ° C. to 760 ° C. Therefore, according to the manufacturing method of this embodiment, it is possible to manufacture a capacitor having a sufficient TDDB life while sufficiently lowering the temperature of wet oxidation. Therefore, according to the manufacturing method of the present embodiment, a capacitor having high reliability and durability can be formed while suppressing a thermal load on various elements mounted on the semiconductor device 10.

In the manufacturing method of this embodiment, the upper electrode 34 is an N-type semiconductor containing phosphorus as an impurity. Therefore, when the ground potential is led to the upper electrode 34, no depletion layer is generated near the boundary between the insulating film 32 and the upper electrode 34 regardless of the amount of activated impurities.
On the other hand, when a positive potential is introduced to the upper electrode 34, a depletion layer is generated near the boundary between the insulating film 32 and the upper electrode 34 if the amount of activated impurities is small. When such a depletion layer occurs between the insulating film 32 and the upper electrode 34, the utilization efficiency of the capacitor decreases. Therefore, in order to use the capacitor with high efficiency, it is necessary to make the upper electrode 34 contain a large amount of activated impurities.

FIG. 5 shows the relationship between the manufacturing conditions of the semiconductor device and the utilization efficiency of the capacitor. The relationship shown in FIG. 5 is obtained under the condition that a potential of +1 V is applied to the upper electrode 34, that is, under the condition where the utilization efficiency of the capacitor is mainly determined by the concentration of the active impurity in the upper electrode 34. It is. The point denoted by reference numeral (1) in FIG.
The heat treatment for activating the impurities inside the upper electrode 34 was performed at 800 ° C., FA (Furnace Anneal), and 30 minutes for the phosphorus concentration of 5 × 10 ²⁰ / cm ³ . The results in the case (results for the conventional conditions) are shown. In FIG. 5, the point indicated by reference numeral (2) is that the phosphorus concentration of the upper electrode 34 is 5 × 10 ²⁰ / cm ³ and the heat treatment is performed at 800 ° C., RTA, and 1 minute. Here is the result when executed by Further, the point indicated by reference numeral (3) in FIG. 5 indicates that the phosphorus concentration of the upper electrode 34 is 8 × 10 ²⁰ /.
cm ³ and heat treatment at 750 ° C., RTA, 3
The result (result for the condition of the present embodiment) when executed under the minute condition is shown.

As shown by the results (1) and (2),
When the phosphorus concentration of the upper electrode 34 is 5 × 10 ²⁰Pieces / cm^ThreeMatches with
If the heat treatment temperature is the same (800 ° C.)
Also changed the heat treatment method from FA 30 minutes to RTA 1 minute.
Approximately 10% reduction in capacitor utilization efficiency
I do. In contrast, results (1) and (3) show
As shown in FIG.²⁰Pieces / cm
^ThreeThen, the heat treatment method is changed from FA 30 minutes to RTA 3 minutes.
And heat treatment temperature from 800 ° C to 750 ° C
, The rate of decrease in the use efficiency of the capacitor is about 5%.
%.

FIG. 6 shows the relationship between the phosphorus concentration of the upper electrode 34 and the utilization efficiency of the capacitor. The relationship shown in FIG.
This relationship is obtained when heat treatment is performed at 750 ° C., RTA for 3 minutes after the formation of the upper electrode 34. still,
In FIG. 6, the utilization efficiency of the capacitor is represented based on the efficiency of the capacitor obtained by the conventional manufacturing method. As shown in FIG. 6, when the heat treatment for the upper electrode 34 is performed under the above conditions (the conditions of the present embodiment), the utilization efficiency of the capacitor is substantially proportional to the phosphorus concentration. According to the results shown in FIG. 6, the phosphorus concentration was 8 × 10 ²⁰ / cm
^{When the value is 3} or more, it can be seen that a capacitor having a utilization efficiency of 95% or more with respect to the capacitor obtained by the conventional manufacturing method is always obtained.

As described above, the phosphorus concentration of the upper electrode 34 is set to 8
When it is at least 10 ²⁰ / cm ^3, it is possible to obtain the same utilization efficiency as when conventional heat treatment conditions are used, even if the heat treatment conditions are lowered and the time is shortened. When the phosphorus concentration of the upper electrode 34 is 8 × 10 ²⁰ / cm ³ or more, a desired utilization efficiency (95% or more with respect to the conventional condition) can be obtained by performing RTA at 750 ° C. for 1 minute or more. Confirmed experimentally.

In the manufacturing method of the present embodiment, as described above,
In the step of depositing the upper electrode 34 (step 40), 8 × 10
A phosphorus concentration of ²⁰ / cm ³ is applied to the upper electrode 34, and a subsequent heat treatment (step 42) is performed at 750 ° C.
RTA, executed under conditions of 1 to 3 minutes. For this reason, according to the manufacturing method of the present embodiment, the temperature of the heat treatment is lowered,
In addition, it is possible to sufficiently secure the use efficiency of the capacitor while significantly shortening the heat treatment time. Therefore, according to the manufacturing method of the present embodiment, it is possible to form a capacitor having desired electric characteristics while suppressing a thermal load on various elements mounted on the semiconductor device 10.

In the above embodiment, the surface of the lower electrode 30 is formed flat, but the structure is not limited to this. That is, the lower electrode 30 may have, for example, a rough surface structure having irregularities on its surface.

In the above embodiment, after the formation of the insulating film 32, wet oxidation (step 38) using water vapor obtained by mixing hydrogen and oxygen is performed. May be performed in an atmosphere of N 2 O gas at a temperature of 700 to 760 ° C. for 60 minutes. It has been experimentally confirmed that the above-described annealing process can repair defects in the insulating film 32 and provide sufficient reliability to the capacitor, similarly to the case where the wet oxidation in step 38 is performed. . In this case, even if the atmosphere at the time of raising the temperature of the silicon wafer during the process of forming the insulating film 32 is N2, that is, sufficient reliability can be obtained even if the atmosphere is not NH3. Has been confirmed. For this reason, when performing the above-mentioned annealing process instead of the wet oxidation in step 38, the temperature raising step of the silicon wafer in the process of forming the insulating film 32 is performed in the same manner as the conventional manufacturing method.
It may be performed in two atmospheres.

In the above embodiment, the semiconductor device 10 includes the word line 20 and the data line 22. These are not limited to doped polysilicon, but may be tungsten, tungsten silicide, titanium nitride, or It may be made of a metal such as titanium. As described above, according to the manufacturing method of the present embodiment, the thermal load applied to the silicon wafer during the manufacturing process of the capacitor can be sufficiently suppressed. Therefore, according to the manufacturing method of the present embodiment, even if metal materials are used for the word lines 20 and the data lines 22, it is possible to form a capacitor without damaging them.

In the above embodiment, dichlorosilane (SiH 2 Cl 2) and ammonia (NH 3) are used as the raw material of the nitride film forming the insulating film 32, but the raw material of the nitride film is not limited to this. Not something. That is, the nitride film may be formed using, for example, tetrachlorosilane (SiCl4) and ammonia (NH3) as raw materials.

[0044]

Since the present invention is configured as described above, it has the following effects. Claim 1
According to the invention described above, the silicon wafer is heated to the CVD temperature in the ammonia atmosphere during the formation of the insulating film. In this case, the life of the capacitor can be sufficiently ensured even when the temperature of the wet oxidation is as low as about 700 ° C. to 760 ° C. Therefore, according to the manufacturing method of the present invention, it is possible to form a capacitor having a sufficient life while lowering the temperature of wet oxidation.

According to the second aspect of the present invention, the wet oxidation of the insulating film is performed in a steam atmosphere in which the flow ratio of hydrogen to oxygen is in the range of 1.8: 1 to 1: 6. When wet oxidation is performed in the above atmosphere, an oxide layer having an appropriate thickness can be formed on the surface of the insulating film. For this reason,
According to the present invention, a capacitor of stable quality can be manufactured with a high yield.

According to the third aspect of the present invention, after the formation of the insulating film, an annealing process at about 700 ° C. to 760 ° C. is performed in N 2 O gas. According to the above-described annealing treatment, the same effect as when wet oxidation is performed on the insulating film can be obtained. Therefore, according to the present invention, it is possible to form a capacitor having a sufficient life while suppressing heat applied to the silicon wafer during the manufacturing process of the capacitor.

According to the fourth aspect of the present invention, phosphorus ions are mixed into the upper electrode at a concentration exceeding 8 × 10 ²⁰ / cm ³ . In this case, desired electrical characteristics can be imparted to the upper electrode by performing RTA at a temperature of about 750 ° C. for about 1 to 3 minutes. Therefore, according to the present invention, it is possible to manufacture a capacitor having desired electric characteristics at a high yield while lowering the heat treatment temperature of the upper electrode.

According to the fifth aspect of the present invention, it is possible to manufacture a capacitor having stable characteristics while lowering both the temperature for processing the insulating film and the temperature for processing the upper electrode. . Therefore, according to the manufacturing method of the present invention, a capacitor having desired characteristics can be manufactured at a high yield without applying a large thermal load to other components mounted on the semiconductor device together with the capacitor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a main part of a semiconductor device manufactured by a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing method according to the first embodiment of the present invention;
FIG. 4 is a diagram for explaining the contents of a series of processes performed when forming an insulating film.

FIG. 4 shows a method of manufacturing a semiconductor device and TDD of a capacitor.
It is a figure showing the relationship with B life.

FIG. 5 is a diagram illustrating a relationship between a method of manufacturing a semiconductor device and utilization efficiency of a capacitor.

FIG. 6 is a diagram illustrating a relationship between a phosphorus concentration of an upper electrode and a utilization efficiency of a capacitor.

FIG. 7 is a flowchart for explaining a conventional method for manufacturing a semiconductor device.

FIG. 8 is a diagram for explaining the contents of a series of processes performed at the time of forming an insulating film in a conventional manufacturing method.

[Explanation of symbols]

Reference Signs List 10 semiconductor device, 20 word line, 22 data line, 30 lower electrode, 32 insulating film,
34 Upper electrode.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Inaba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Co., Ltd. (72) Inventor Kiyoshi Mori 2-3-2 Marunouchi, Chiyoda-ku, Tokyo 3 F term (reference) 5F038 AC05 AC09 AC16 DF05 EZ16 EZ17 EZ20 5F058 BA11 BC08 BF02 BF24 BF30 BF55 BF63 BH01 BH03 BJ01

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device having a capacitor, comprising: forming a lower electrode of the capacitor; and forming a nitride film by CVD as an insulating film of the capacitor on the lower electrode of the capacitor. A step of wet-oxidizing the insulating film within a temperature range of 700 ° C. to 760 ° C. after the formation of the insulating film; and a step of forming an upper electrode of a capacitor on the insulating film. A method of manufacturing a semiconductor device, wherein the step of forming a film includes a step of raising a temperature of a silicon wafer to a CVD reaction temperature in an ammonia atmosphere. 2. The method according to claim 1, wherein the wet oxidation is performed in a steam atmosphere having a flow ratio of hydrogen to oxygen in a range of 1.8: 1 to 1: 6. . 3. A method for manufacturing a semiconductor device having a capacitor, comprising: forming a lower electrode of the capacitor; and forming a nitride film by CVD as an insulating film of the capacitor on the lower electrode of the capacitor. A step of performing annealing in an atmosphere containing N 2 O gas within a temperature range of 700 ° C. to 760 ° C. after forming the insulating film; and a step of forming an upper electrode of the capacitor on the insulating film. A method for manufacturing a semiconductor device, comprising: 4. A method for manufacturing a semiconductor device having a capacitor, comprising: forming a lower electrode of the capacitor; forming an insulating film of the capacitor on the lower electrode of the capacitor; Depositing amorphous silicon having a phosphorus concentration of 8 × 10 ²⁰ / cm ³ or more as a film for forming an upper electrode of the capacitor on the upper part; Performing a rapid thermal anneal within a range of 3 to 3 minutes. 5. The step of forming the upper electrode includes a step of depositing amorphous silicon having a phosphorus concentration of 8 × 10 ²⁰ / cm ³ or more on the insulating film, and after depositing the amorphous silicon. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the rapid thermal annealing is performed at a temperature near 750 ° C. within a range of 1 to 3 minutes.