JPS6089943A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6089943A JPS6089943A JP19769183A JP19769183A JPS6089943A JP S6089943 A JPS6089943 A JP S6089943A JP 19769183 A JP19769183 A JP 19769183A JP 19769183 A JP19769183 A JP 19769183A JP S6089943 A JPS6089943 A JP S6089943A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten
- silicide
- wiring
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置の製造方法に係シ、詳しくはWも
しくはMO膜を電極や配線として用いる半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using a W or MO film as an electrode or wiring.
従来 81基板上に810g 、8isN4などの絶縁
膜を形成した後に、MOやWの配線ケ形成して、MOや
W配線とSi基板との電気的な絶縁をはかるという公知
の技術があるが、多層配線を行なう場合、配線に伴う表
面の凹凸で、MO,W配線が段差部で切断されたp2配
線間の接触があるといった問題があった。Conventionally, there is a known technique in which an insulating film such as 810g or 8isN4 is formed on an 81 substrate, and then MO or W wiring is formed to electrically insulate the MO or W wiring from the Si substrate. When performing multilayer wiring, there is a problem in that the surface unevenness accompanying the wiring causes contact between the p2 wirings where the MO and W wirings are cut at the stepped portions.
本発明の目的は、上記従来の問題を解決し、Mo−?W
腹膜下順次810g、シリサイドを形成してSi基板と
の電気絶縁を容易にすることのできる半導体装置の製造
方法を提供することである。An object of the present invention is to solve the above-mentioned conventional problems and to solve the problems of the Mo-? W
An object of the present invention is to provide a method for manufacturing a semiconductor device that can facilitate electrical insulation with a Si substrate by sequentially forming 810 g of silicide under the peritoneum.
上記目的を達成するため、本発明は、WやMOをSi上
に被着した後、H,+0を11)Pmから50%含む1
12中で500C〜1200Cで加熱する。このように
すると、まずW、MoがSiと反応してシリサイド(W
S l x 、 MoS + 2等)を形成し、次にH
2中の1120によってシリサイド表面にSighが形
成される。W、Moは上記気体(■12十Hz O)で
は酸化しないので、W1MO′/を酸化させることなし
に、上記シリサイドとSiO+の形成が行なわれる。In order to achieve the above object, the present invention provides 11) containing 50% of H, +0 from 11) Pm after depositing W or MO on Si.
Heat at 500C to 1200C in 12C. In this way, W and Mo first react with Si to create silicide (W
S l x , MoS + 2, etc.) and then H
Sigh is formed on the silicide surface by 1120 in 2. Since W and Mo are not oxidized by the above gas (120 Hz O), the above silicide and SiO+ are formed without oxidizing W1MO'/.
以下、実施例を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to Examples.
〔実施例1」
第1図(a)に示すように、Si結晶基板2上にW膜1
を厚さ35Qnm蒸着した試料を、H2Oを20チ含む
)I2中で1000C,120分間加熱□すると、第1
図(b)に示すように、W膜1(厚さ130nm)丁に
順次、5i02換3(厚さ2000m)、タングステン
シリサイド(WS i 2 )膜4(厚さ8501m)
が形成された。W膜1とシリサイド膜4の間の8i02
膜3の絶縁耐圧を測定すると2〜5 M V / on
であった。この値は通常の熱510z膜の耐圧(〜10
MY / clrr )に比べてやや低い値であるが
、十分に実用化に耐えるものである。また、5ro2膜
の厚さは、11!中のH2Oの量ならびに加熱&度、時
間を変えることで加減できる。[Example 1] As shown in FIG. 1(a), a W film 1 is formed on a Si crystal substrate 2.
When a sample deposited with a thickness of 35 Qnm was heated at 1000C for 120 minutes in I2 (containing 20 cm of H2O), the first
As shown in Figure (b), W film 1 (thickness: 130 nm), 5iO2 film 3 (thickness: 2000 m), and tungsten silicide (WS i 2 ) film 4 (thickness: 8501 m) are sequentially applied.
was formed. 8i02 between W film 1 and silicide film 4
Measuring the dielectric strength voltage of membrane 3 is 2 to 5 M V/on
Met. This value is the withstand pressure of a normal thermal 510z film (~10
Although this value is slightly lower than that of MY/clrr), it is sufficient for practical use. Also, the thickness of the 5RO2 film is 11! You can adjust the amount by changing the amount of H2O in it, the heating temperature, and the time.
〔実施例2〕
第2図(a)に示すように、Si結晶基板2上にW膜1
を厚さ350nm蒸着した後、その上に8102よって
lQQnm被着した後、通常のフオ) IJソゲラフイ
ーを用いて、適当な場所のS i O2膜をエツチング
して除去する。次にH20を10チ含むH2中で100
OC,60分間加熱すると、第2図(b)に示すように
、Wがむき出しの部分では、実施例1でみたようにW膜
下には順次8102膜3′(厚さ10100n、シリサ
イド膜4(厚さ700nm)が形成され、5i02膜3
で覆われた部分では、H2Oの拡散が抑えられるために
シリサイド膜4(厚さ800nm)のみが形成された。[Example 2] As shown in FIG. 2(a), a W film 1 is formed on a Si crystal substrate 2.
After depositing 1QQnm of 8102 on it to a thickness of 350 nm, the SiO2 film at appropriate locations is removed by etching using a conventional photolithography (IJ) polisher. Next, 100 in H2 containing 10 inches of H20
When heated OC for 60 minutes, as shown in FIG. 2(b), in the exposed part of W, an 8102 film 3' (thickness 10100 nm, silicide film 4 (thickness: 700 nm), 5i02 film 3
In the portion covered with , only the silicide film 4 (thickness: 800 nm) was formed because the diffusion of H2O was suppressed.
次に第2図(C)に示すように、CVD法によって、厚
さ1100nの5j02膜3“を被着した。本実施例は
、SiO□膜の拡散マスクを用いて、Wの埋め込み配線
を形成する技術を与えるものである。W配線は、埋め込
み型に形成されるため、配線に伴う表面の凹凸は生じな
い。Next, as shown in FIG. 2(C), a 5j02 film 3'' with a thickness of 1100 nm was deposited by the CVD method.In this example, a W buried wiring was formed using a SiO□ film diffusion mask. Since the W wiring is formed in a buried manner, surface irregularities associated with the wiring do not occur.
本発明によれは、Si基板上にW、MO膜を蒸着した後
、アニール工程でW、MOの膜下に5in2を形成する
ことができる。実施例で見た様に、H2Oの拡散マスク
としてSing 、PSG 、Si2N4 などを用い
れば、選択的に上記の反応を起こすことができるので埋
め込み配線等に利用でき、多層配線、三次元デバイス用
の配線に応用できる。製造工程も通常の電気炉を用いて
行なえるため、その生産性・経済性は極めて高い。According to the present invention, after a W and MO film is deposited on a Si substrate, a 5in2 film can be formed under the W and MO film in an annealing process. As seen in the example, if Sing, PSG, Si2N4, etc. are used as a H2O diffusion mask, the above reaction can be selectively caused, so it can be used for embedded wiring, etc., and it can be used for multilayer wiring and three-dimensional devices. Can be applied to wiring. The manufacturing process can also be carried out using a normal electric furnace, so its productivity and economic efficiency are extremely high.
第1図、第2図はそれぞれ本発明の異なる実施例を示す
工程図である。
1・・・タングステン膜、2・・・シリコン単結晶、3
゜3 / 、 3//・・・酸化シリコン膜、4・・・
タングステン秀1図
N2図
一’;)’;)1−FIGS. 1 and 2 are process diagrams showing different embodiments of the present invention. 1... Tungsten film, 2... Silicon single crystal, 3
゜3/, 3//...silicon oxide film, 4...
Tungsten Xiu 1 Figure N2 Figure 1';)';)1-
Claims (1)
Mo)金属膜を形成する工程と、11□0をippmか
ら50%含むH2中テ500〜1200Cの温度で加熱
して上記タングステンあるいはモリブデン金属膜下に二
酸化シリコン(SiOx)膜とシリサイド膜を順次形成
する工程を含むことを特徴とする半導体装置の製造方法
。Tungsten (W) or molybdenum (
Mo) Step of forming a metal film, and successively forming a silicon dioxide (SiOx) film and a silicide film under the tungsten or molybdenum metal film by heating at a temperature of 500 to 1200 C in H2 containing 50% of 11□0 from ippm. 1. A method of manufacturing a semiconductor device, the method comprising the step of forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19769183A JPS6089943A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19769183A JPS6089943A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6089943A true JPS6089943A (en) | 1985-05-20 |
Family
ID=16378744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19769183A Pending JPS6089943A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6089943A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323115B1 (en) | 1998-05-20 | 2001-11-27 | Hitachi, Ltd. | Method of forming semiconductor integrated circuit device with dual gate CMOS structure |
US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
-
1983
- 1983-10-24 JP JP19769183A patent/JPS6089943A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323115B1 (en) | 1998-05-20 | 2001-11-27 | Hitachi, Ltd. | Method of forming semiconductor integrated circuit device with dual gate CMOS structure |
US6784038B2 (en) | 1998-05-20 | 2004-08-31 | Renesas Technology Corp. | Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device |
US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
US7144766B2 (en) | 2001-03-12 | 2006-12-05 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
US7300833B2 (en) | 2001-03-12 | 2007-11-27 | Renesas Technology Corp. | Process for producing semiconductor integrated circuit device |
US7375013B2 (en) | 2001-03-12 | 2008-05-20 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
US7632744B2 (en) | 2001-03-12 | 2009-12-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
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