JPS60134445A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60134445A JPS60134445A JP24270283A JP24270283A JPS60134445A JP S60134445 A JPS60134445 A JP S60134445A JP 24270283 A JP24270283 A JP 24270283A JP 24270283 A JP24270283 A JP 24270283A JP S60134445 A JPS60134445 A JP S60134445A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- polycrystalline
- cvd method
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は導電層間を絶縁する眉間絶縁膜を有する半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device having a glabella insulating film that insulates between conductive layers.
第1図に半導体装置の具体例としてNIViO8FET
を示す。半導体基板1にソース、rレインとしての不純
物拡散層2.3を形成しこれら不純物拡散層2.3の間
にゲート酸化膜4と多結晶シリコン電極5とを形成する
。その上に層間絶縁膜6を形成し、さら忙アルミニウム
配線層7を形成する。Figure 1 shows NIViO8FET as a specific example of a semiconductor device.
shows. Impurity diffusion layers 2.3 as a source and r-rain are formed on a semiconductor substrate 1, and a gate oxide film 4 and a polycrystalline silicon electrode 5 are formed between these impurity diffusion layers 2.3. An interlayer insulating film 6 is formed thereon, and a thin aluminum wiring layer 7 is formed thereon.
8は素子分離酸化膜である。8 is an element isolation oxide film.
この層間絶縁膜6を形成するのに従来通常の常圧CVD
法忙よりS iozを堆積させていた。しかしながらこ
のような従来の製造方法では、第2図に示すようにCV
D膜のガノ々レジが悪く空洞を生じたり(A)、下地段
差部で薄くなりすぎ(B)、電気的特性が悪いという問
題があった。また通常のCVD法では製造装置内の壁等
に堆積した酸化膜の固まりが半導体基板上に付着して、
CVD膜にヒロック(hillock ) が発生しや
すいという問題があった。このヒロックは製造装置の使
用回数に比例して増加し、アルミニウム配線が断線した
りパターン形状が異常となる問題があった。To form this interlayer insulating film 6, conventional normal pressure CVD is used.
I was accumulating more Sioz than I was before. However, in such a conventional manufacturing method, as shown in FIG.
There were problems such as poor registration of the D film and the formation of cavities (A), excessive thinning at the step portion of the base (B), and poor electrical characteristics. In addition, in the normal CVD method, clumps of oxide film deposited on the walls of the manufacturing equipment adhere to the semiconductor substrate.
There is a problem in that hillocks are likely to occur in the CVD film. These hillocks increase in proportion to the number of times the manufacturing equipment is used, causing problems such as disconnection of the aluminum wiring and abnormal pattern shapes.
本発明は上記畠情を考慮してなされたもので、膜厚が均
一で欠陥の少ない層間絶縁膜を形成することができる半
導体装置の製造方法を提供することを目的とする。The present invention has been made in consideration of the above situation, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can form an interlayer insulating film having a uniform thickness and fewer defects.
この目的を達成するために本発明による半導体装置の製
造方法は、導電層上にLP CVD法により多結晶シリ
コン膜を堆積し、その後この多結晶シリコン膜を熱酸化
することにより、導電層間を絶縁する層間絶縁膜を形成
することを特徴とする。またこの製造方法において4.
′、、多結晶シリコン膜を熱酸化する前に不純物を添加
することが望ましい。In order to achieve this object, the method for manufacturing a semiconductor device according to the present invention deposits a polycrystalline silicon film on a conductive layer by LP CVD method, and then thermally oxidizes the polycrystalline silicon film to insulate the conductive layers. It is characterized by forming an interlayer insulating film. In addition, in this manufacturing method, 4.
', It is desirable to add impurities before thermally oxidizing the polycrystalline silicon film.
呆発明の一実施例による半導体装置の製造方法を輯3図
を用いて説明する。半導体基板1に不純物拡散層2.3
、ゲート酸化膜4、多結晶シリコン電極5を形成する(
第3図(a))。次にLPCVD法(Lovr Pre
ssure Chemical Vapor Depo
sl tion )により多結晶シリコン層6を約50
0X〜aooo! 堆積させる(第3図(b))。ここ
でCVD法によらずLPCVD法によるのは、堆積され
る膜設として均一なものが得られるからである。また酸
化シリコンでなく多結晶シリコンを堆積させるのは、酸
化シリコンを直接堆積させると電気的絶縁性に問題があ
るからである。A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. Impurity diffusion layer 2.3 on semiconductor substrate 1
, gate oxide film 4, and polycrystalline silicon electrode 5 are formed (
Figure 3(a)). Next, LPCVD method (Lovr Pre
ssure Chemical Vapor Depo
polycrystalline silicon layer 6 by approximately 50%
0X~aoooo! (Fig. 3(b)). The reason why the LPCVD method is used instead of the CVD method is that a uniform deposited film can be obtained. Further, the reason why polycrystalline silicon is deposited instead of silicon oxide is that there is a problem in electrical insulation if silicon oxide is directly deposited.
この多結晶シリコン層6をすぐ酸化して層間絶縁膜6と
してもよいが、その前に不純物、例えばリン(P)を拡
散またはイオン注入して多結晶シリコン層6に不純物を
添加する(第3図(C))。その後熱酸化すると熱酸化
速度が速くなり、より低波(約700’C,−900℃
)で熱酸化が可能である。不純物を添加しない場合の熱
酸化は約900°C〜1100°Cでおこなわれる。熱
酸化により多結晶シリコン層6は酸化シリコン層すなわ
ち層間絶縁膜6となる(第3図(d) )、その後アル
ミニウム配線層7を形成し半導体装置の製造を終了する
(第3図(e))。This polycrystalline silicon layer 6 may be immediately oxidized to form the interlayer insulating film 6, but before that, an impurity such as phosphorus (P) is diffused or ion-implanted to add an impurity to the polycrystalline silicon layer 6 (third step Figure (C)). After that, when thermal oxidation is carried out, the thermal oxidation rate becomes faster and lower waves (approximately 700'C, -900°C
) thermal oxidation is possible. Thermal oxidation without the addition of impurities is carried out at approximately 900°C to 1100°C. By thermal oxidation, the polycrystalline silicon layer 6 becomes a silicon oxide layer, that is, an interlayer insulating film 6 (FIG. 3(d)), and then an aluminum wiring layer 7 is formed to complete the manufacturing of the semiconductor device (FIG. 3(e)). ).
本発明による製造方法は実施例のものの他にも層間絶縁
膜を有するすべての半導体装置に適用可能であり、メモ
リマイクロプロセッサ等、はとんどの半導体装置に適用
できる。The manufacturing method according to the present invention can be applied not only to the embodiments but also to all semiconductor devices having an interlayer insulating film, and can be applied to most semiconductor devices such as memory microprocessors.
以上の通り本発明によれば、膜厚が均一で欠陥の少ない
層間絶縁膜を形成することができ、半導体装置の製造の
歩留り向上、および製造された半導体装置の信頼性向上
が図れる。As described above, according to the present invention, it is possible to form an interlayer insulating film having a uniform thickness and fewer defects, thereby improving the yield of manufacturing semiconductor devices and improving the reliability of the manufactured semiconductor devices.
第1図は層間絶縁膜を有する半導体装置の一具体例の断
面図、第2図は従来の製造方法により形成された半導体
装置の一具体例の断面図、第3図(a)、(b)、(e
)、(d)、(e)は本発明の一実施例による半導体装
置の製造方法の工程図である。
1・・・半導体基板、2.3・・・不純物拡散層、4・
・・ゲート酸化膜、5・・・多結晶シリコン電極、6・
・・層間絶縁膜、7・・・アルミニウム配線層。
出願人代理人 猪 股 清FIG. 1 is a cross-sectional view of a specific example of a semiconductor device having an interlayer insulating film, FIG. 2 is a cross-sectional view of a specific example of a semiconductor device formed by a conventional manufacturing method, and FIGS. ), (e
), (d), and (e) are process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate, 2.3... Impurity diffusion layer, 4.
...Gate oxide film, 5...Polycrystalline silicon electrode, 6.
...Interlayer insulating film, 7... Aluminum wiring layer. Applicant's agent Kiyoshi Inomata
Claims (1)
を堆積し、その後この多結晶シリコン膜を熱酸化するこ
とにより、導電層間を絶縁する眉間絶縁膜を形成するこ
とを特徴とする半導体装置の製造方法。 2、特許請求の範囲第1項記載の方法において、多結晶
シリコン膜を熱酸化する前に不純物を添加することを特
徴とする半導体装置の製造方法。[Claims] 1. A polycrystalline silicon film is deposited on a conductive layer by the LP CVD method, and then this polycrystalline silicon film is thermally oxidized to form a glabella insulating film that insulates between the conductive layers. A method for manufacturing a featured semiconductor device. 2. A method for manufacturing a semiconductor device according to claim 1, characterized in that impurities are added to the polycrystalline silicon film before thermally oxidizing it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24270283A JPS60134445A (en) | 1983-12-22 | 1983-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24270283A JPS60134445A (en) | 1983-12-22 | 1983-12-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60134445A true JPS60134445A (en) | 1985-07-17 |
Family
ID=17092973
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24270283A Pending JPS60134445A (en) | 1983-12-22 | 1983-12-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60134445A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03183137A (en) * | 1989-09-08 | 1991-08-09 | Hyundai Electron Ind Co Ltd | Manufacture of semiconductor device by utilizing self-alignment contact method |
US10816254B2 (en) | 2014-07-22 | 2020-10-27 | Peter TROISSINGER | Device for producing snow |
-
1983
- 1983-12-22 JP JP24270283A patent/JPS60134445A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03183137A (en) * | 1989-09-08 | 1991-08-09 | Hyundai Electron Ind Co Ltd | Manufacture of semiconductor device by utilizing self-alignment contact method |
US10816254B2 (en) | 2014-07-22 | 2020-10-27 | Peter TROISSINGER | Device for producing snow |
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