JP3277043B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a silicon oxidation step after forming a gate electrode is improved.

[0002]

2. Description of the Related Art At present, polycrystalline silicon is widely used as a material for electrodes and wirings of semiconductor devices. However, with high integration and high speed of semiconductor devices, delay in signal transmission due to resistance of electrodes and wiring has become a serious problem. In particular, MOs with large capacity and high integration
In the field of SLSI, the polycrystalline silicon used for the gate electrode is shared with the first layer wiring, and the resistance of the polycrystalline silicon here is an obstacle to the high-speed operation of the semiconductor device.

For these reasons, silicide of high melting point metal having thermal stability and low electric resistance is being used as an electrode wiring material instead of polycrystalline silicon.
Recently, attempts have been made to use a high melting point metal such as W or Mo as a gate electrode. Refractory metals such as W and Mo have an electrical resistivity two orders of magnitude lower than that of polycrystalline silicon, and are １ ／ to の of the resistivity of silicide.
And is promising as a low-resistance electrode wiring material.

As a semiconductor device using the above-mentioned refractory metal (for example, W) as a constituent material of a gate electrode, a semiconductor device having a structure shown in FIG. 7A is conventionally known. That is, reference numeral 1 in the drawing denotes a p-type silicon substrate, on which a field insulating film 2 for electrically isolating element regions is formed. On the surface of the p-type silicon substrate 1 separated by the field insulating film 2, n ⁺ -type diffusion layers 3a and 3b serving as a source and a drain electrically separated from each other are formed.

On the surface of the substrate 1 including the channel region between the diffusion layers 3a and 3b, a polycrystalline silicon layer 5, a metal nitride layer (for example, Ti
A gate electrode 8 including an N layer 6 and a tungsten (W) layer 7 is provided. The metal nitride layer 6 forming the gate electrode 8 improves the adhesion between the tungsten layer 7 and the polycrystalline silicon layer 5 and reacts with the tungsten layer 7 and the polycrystalline silicon layer 5 to form a resistivity. Acts as a reaction barrier for preventing the rise of one digit.

In the conventional process of forming a gate electrode made of polycrystalline silicon, 5 to 50
In order to recover the gate breakdown voltage deterioration caused by the defect of the gate oxide film as thin as nm and the edge shape of the gate electrode,
A heat treatment is performed in an oxidizing atmosphere (for example, dry oxygen) to perform a process of newly growing a silicon oxide layer on the exposed surface of the polycrystalline silicon layer and the substrate in the source and drain regions. This step is called a post-gate oxidation step.

However, since high melting point metals such as W and Mo generally do not have resistance to heat treatment in an oxidizing atmosphere, the gate electrode structure shown in FIG. There was a problem that it could not be applied.

As a method for solving the above problem, a heat treatment is performed in an atmosphere containing a reducing gas (for example, hydrogen) and an oxidizing gas (for example, water vapor) and containing nitrogen as a diluent gas, so that the gate electrode is formed. There is well known a silicon selective oxidation technique capable of forming a silicon oxide film without causing oxidation of the constituent metal layer and metal nitride layer, thereby improving the gate breakdown voltage (Japanese Patent Laid-Open No. Hei 3-
119763).

In this case, when H ₂ is used as the reducing gas, water vapor (H ₂ O) is used as the oxidizing gas, and N ₂ is used as the gas containing nitrogen, the mixing ratio is as follows. It is said that setting is desirable. That is, H
₂ , assuming that the partial pressures of H ₂ O and N ₂ are P _H2 , P _H2O and P _N2 , P _N2 / P _H2O is 0.5-1.0 × 10 ⁹ and log P _N2 is -22-14. I do. Further, as a more preferable condition, the temperature is preferably set to 800 to 900 ° C., and at this time, PH ₂ / PH _{2 O} is adjusted to 1.0 × 10 ^{3 to} 1.0 × 1.
To 0 ^4, and in which the logP _N2 to -2 to 2. By performing the heat treatment under such an atmosphere condition, only the silicon can be oxidized without oxidizing the metal forming the gate electrode.

However, recent vigorous research has revealed that this type of method has the following problems. First, under the above selective oxidation conditions, P _H2O
, The oxidation rate of silicon is very low, and it is necessary to heat at a high temperature for a long time in order to obtain a silicon oxide film necessary for improving the breakdown voltage of the gate electrode, which increases the thermal load. In addition, the above selective oxidation conditions are those during annealing after temperature stabilization, and do not satisfy the selective conditions at the time of raising and lowering the temperature of the substrate, which clearly oxidizes the metal layer and the metal nitride layer at the gate electrode. Became.

As an example, in the gate electrode structure of tungsten layer 7 / TiN layer 6 / polycrystalline silicon layer 5 as shown in FIG. 7A , the gas partial pressure is set to H ₂ : H ₂ O: N ₂ =
The heating was performed at 900 ° C. for 120 minutes at a temperature rising / falling rate of ± 45 ° C./min while keeping 0.164: 1 × 10 ⁻⁴ : 0.836. Figure temporal change of H _{2 O} partial pressure and the substrate temperature at this
FIG . However, according to such heat treatment, FIG.
As shown in (b) , not only the polycrystalline silicon layer 5 and the side wall and the surface of the silicon substrate 1 but also the T
It was confirmed that the iN layer 6 was oxidized and a TiO ₂ film 9 of about 10 nm was formed. Further, in the gate electrode thus formed, it is difficult to form a side wall film on the side wall of the gate electrode, the reaction barrier property of the TiN layer itself deteriorates, There has been a problem that the function as a mask is impaired.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to perform post-gate oxidation while suppressing oxidation of a metal layer constituting a gate electrode. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing a thermal load by shortening a heat treatment time and improving a gate breakdown voltage.

[0013]

According to the present invention, there is provided a step of forming a gate electrode having a laminated structure including a metal nitride layer and a metal layer on a silicon substrate via a gate insulating film; A step of oxidizing the surface of the silicon substrate by heat treatment in an atmosphere containing an oxidizing gas and nitrogen, and a step of raising and lowering the temperature of the silicon substrate in the atmosphere before and after the step of heat treatment; In the step of raising and lowering the temperature, the thickness of the metal oxide layer formed by oxidizing the metal nitride layer and the metal layer is 20% or less of the thickness of the metal oxide layer and the metal layer.
As described above, a method for manufacturing a semiconductor device, which is performed at a rate of 50 ° C./min or more, is provided.

In the method of the present invention, the gate electrode may have a stacked structure of a polycrystalline silicon layer, a metal nitride layer, and a metal layer. As the metal layer, tungsten,
Molybdenum, platinum, palladium, rhodium, ruthenium, nickel, cobalt, tantalum , titanium and the like can be used. The metal nitride layer forms a barrier layer between the metal layer and the polycrystalline silicon layer, and uses a nitride such as titanium, zirconium, hafnium, tungsten, vanadium, niobium, tantalum, chromium, or rhenium. Can be done.

Further, in the heat treatment step in the method of the present invention, the rate of temperature rise and the rate of temperature decrease are such that the thickness of the metal oxide layer formed by oxidation of the metal nitride layer and the metal layer is smaller than the thickness of the metal layer. The speed is 20% or less. By performing the heating at such a temperature increasing rate and a temperature decreasing rate, it is possible to oxidize silicon and to perform a heat treatment for suppressing the oxidation of the metal nitride layer and the metal layer.

Further, the present invention provides a step of forming an electrode having a laminated structure including a metal nitride layer and a metal layer on a silicon substrate via a gate insulating film, and forming the electrode in an atmosphere containing hydrogen, water vapor and nitrogen. A step of oxidizing the surface of the silicon substrate by performing a heat treatment, and a step of raising and lowering the temperature of the silicon substrate before and after the step of heat treatment, prior to or during the step of raising and lowering the temperature ,
Gibbs free energy in the oxidation reaction of silicon
Change ΔG ₁ ° (T), the oxidation reaction of the metal of the metal layer
Change in free energy of Gibbs ΔG ₂ ° (T)
Gibbs free energy in oxidation reactions of metals and metal nitrides
The change in energy ΔG ₃ ° (T) is calculated by the following equations (1) to (3).
A method for manufacturing a semiconductor device is provided , wherein a partial pressure of a gas contained in the atmosphere is controlled so as to satisfy the above condition . ΔG ₁ ° (T) ≧ −4.575 × T × 2 log (P _H2 / P _H2O ) (1) ΔG ₂ ° (T) ≦ −4.575 × T × 2 log (P _H2 / P _H2O ). 2) ΔG ₃ ° (T) ≦ −4.575 × T × {1/2 [logP _N2 + 2log (P _H2 / P _H2O )] } (3)

For example, when the temperature rises and falls, the gas partial pressure ratio is
By changing the temperature so as to be included in the selective oxidation conditions corresponding to the changing temperature, it is possible to suppress the oxidation of the metal nitride layer and the metal layer at the time of raising and lowering the temperature.

[0018]

[0019]

In the method of the present invention, the heat treatment step for post-gate oxidation is performed under conditions controlled so as to oxidize silicon and to suppress oxidation of the metal nitride layer and the metal layer. That is, the heat treatment is performed in an atmosphere containing a reducing gas, an oxidizing gas, and nitrogen, and the rate of temperature increase and the rate of temperature decrease are appropriately controlled. Thereby the metal
The thickness of the metal oxide layer formed by oxidation of the nitride layer and the metal layer can be set to 20% or less of the thickness of the metal nitride layer and the metal layer.

The relationship between the heating rate and the cooling rate and the thickness of the metal oxide layer will be described below. First, time t ₀
The film thickness Δt _OXさ れ_る at which the metal nitride layer and the metal layer are oxidized when the temperature is raised from T ₀ to T ₁ between t ₁ and t ₁ is expressed by the following equation (1). Note that the temperature T = At +
B (A and B are constants, A represents a rate gradient of temperature rise and temperature decrease), and an oxidation rate R = Cexp (−Ea / k
^{_{T) (C = C'P H2O n}} , n is represented by about 1).

[0021]

(Equation 1)

The thickness Δt _OX ↓ at which the metal nitride layer and the metal layer are oxidized when the temperature is lowered can be calculated in the same manner.
Accordingly, the total thickness of the film thickness Delta] t _OX ↓ metal nitride layer and a metal layer is oxidized when the metal nitride layer and a metal layer is lowered and ↑ thickness Delta] t _OX is oxidized when heating Delta] t _OX Then, it is necessary to satisfy the following equation.

Δt _OX = Δt _OX ↑ + Δt _OX ↓ ≦ 0.2t (t: metal nitride layer and metal film thickness) This equation was actually calculated, and the relationship between PH _{2 O} and the temperature rise / fall rate was obtained. The result shown in FIG. 9 was obtained. In this figure, it can be seen that it is better to raise and lower the temperature in the curve formed by smoothly connecting the four points (indicated by white circles) and in the region on the higher heating rate side.

Under normal atmospheric pressure conditions, the metal nitride layer is more easily oxidized than the metal layer, so it is only necessary to consider only the thickness of the metal nitride layer. As described above, by suppressing the oxidation of the metal nitride layer and the metal layer, a low-resistance gate electrode can be obtained, and the shortening of the heat treatment time leads to a reduction in thermal load and an improvement in throughput. A semiconductor device having good gate insulation resistance can be manufactured.

The following can be said with respect to the partial pressures of hydrogen and water vapor in which only Si is oxidized and W and TiN are not oxidized. That is, first, the oxidation reaction of Si, W and TiN
It is shown by the following reaction formula.

The following can be said with respect to the partial pressures of hydrogen and water vapor in which only Si is oxidized and W and TiN are not oxidized. That is, first, the oxidation reaction of Si, W and TiN
It is shown by the following reaction formula. _{Si + 2H 2 O = SiO 2} + 2H 2 ... (1) ΔG 1 ° (T) W + 2H 2 O = WO 2 + 2H 2 ... (2) ΔG 2 ° (T) TiN + 2H 2 O = TiO 2 + 2H 2 + 1 / 2N 2 ... (2) ΔG ₃ ° (T) ΔG ₁ ° (T), ΔG ₂ ° (T), ΔG ₃ °
(T) is the free energy of Gibbs in each reaction equation.
It is a change .

The condition of the partial pressure of hydrogen and water vapor to oxidize only Si and not W and Ti is expressed by the following equation. ΔG ₁ ° (T) ≧ −4.575 × T × 2 log (P _H2 / P _H2O ) (1) ΔG ₂ ° (T) ≦ −4.575 × T × 2 log (P _H2 / P _H2O ). 2) ΔG ₃ ° (T) ≦ −4.575 × T × {1/2 [log P _N2 +2 log (PH ₂ / P _H2O )]} (3) For example, ΔG _n ° (T) Is ΔG _n °
To change the (T') (T>T') , the range of the partial pressure of each gas is changed as shown in FIG. 10. By changing the partial pressure so that the experimental conditions fall within the changing range, it is possible to oxidize only Si without oxidizing W and Ti. That is, the straight line 1 in FIG.
2, 3, 1 ', 2', and 3 'represent the equality of the above inequality, respectively, and the region surrounded by the straight lines 1, 2, and 3 oxidizes only Si without oxidizing W and Ti. Range. The same can be said for the temperature rise.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A to 1E are cross-sectional views showing steps of forming a gate electrode according to a first embodiment of the present invention. First, as shown in FIG. 1A, for example, after a field oxide film 12 is formed on the surface of a p-type silicon substrate 11 by selective oxidation, a thermal oxidation process is applied to the silicon substrate 11 separated by the field oxide film 12. 5 thickness on the surface
A 30 nm silicon oxide film 13 was formed.

Next, as shown in FIG. 1B, after a polycrystalline silicon layer 14 having a thickness of 50 nm doped with impurities is deposited on the silicon oxide film 13, the substrate 11 is
At a temperature of K, sputtering is performed in a mixed gas of N ₂ and Ar with Ti as a target, so that a 50 nm-thick TiN film is formed on the polycrystalline silicon layer 14.
Layer 15 was deposited. Subsequently, H ₂ was added to the mixture by a CVD method using a mixed gas of hydrogen (H ₂ ), monosilane (SiH ₄ ), and tungsten hexafluoride (WF ₆ ).
A partial pressure of Torr and SiH ₄ of 0.013 Torr and a partial pressure of WF ₆ of 0.065 Torr were maintained, and a W layer 16 having a thickness of about 150 nm was deposited on the TiN layer 15 at a substrate temperature of 420 ° C.

Subsequently, the W layer 16, the TiN layer 15, and the polycrystalline silicon layer 14 are sequentially and selectively etched using ordinary photolithography and reactive ion etching (RIE), as shown in FIG. Thus, the gate electrode 18 was formed.

Next, in a mixed gas atmosphere (total pressure 1 atm) containing hydrogen (H ₂ ) and water vapor (H ₂ O) and using nitrogen (N ₂ ) as a carrier gas, the oxidation rate of silicon is increased. The water vapor partial pressure was increased to a condition where WO ₂ was reduced and TiN was oxidized. The gas partial pressure under this condition is H
₂ : H ₂ O: N ₂ = 0.164: 1 × 10 ⁻³ : 0.83
5 Under these partial pressure conditions, a heating rate of 100 ° C./min.
After heating to 00 ° C and heating for 30 minutes, -70 ° C /
The temperature was lowered at a rate of one minute. FIG. 2 shows the time change of the substrate temperature at this time. The H ₂ O partial pressure was kept constant.

According to the oxidation treatment under the above conditions, as shown in FIG. 1D, not only is the side wall of the polycrystalline silicon layer 14 and the surface of the silicon substrate 11 oxidized,
The exposed side walls of the iN layer 15 are also oxidized, and the TiO ₂ film 17 is exposed.
Was formed, and it was confirmed that the thickness was as thin as about 5 nm. This indicates that the above-described oxidation treatment method can reduce the process time from 160 minutes to 46 minutes as compared with the conventional method, and is effective in suppressing the TiN layer oxidation.

It has also been found that the W surface oxidized by the resist peeling asher is reduced and becomes a good W surface. Further, it was confirmed that the oxide film in the edge region of the gate electrode 18 was thickened by about 5 nm by this method.

Subsequently, n-type impurities, for example, arsenic are ion-implanted and activated using the field oxide film 12 and the gate electrode 18 as a mask, thereby activating the surface region of the silicon substrate 11 as shown in FIG. Then, n ⁺ -type diffusion layers 19a and 19b serving as a source and a drain were formed.

According to this embodiment, in the oxidation process, the oxidation of the sidewalls of the W layer and the TiN layer in the gate structure can be minimized, the process time can be shortened, and furthermore, a good gate can be obtained. It has been confirmed that a MOS type semiconductor device having electrode insulation resistance can be manufactured.

Further, in this embodiment, in the gate electrode structure, P _H2O was lowered to the limit condition of TiN oxidation (gas partial pressure was H ₂ : H ₂ O: N ₂ = 0.164: 1 × 10 ^-4 :
0.836), heating rate 150 ° C./min, cooling rate −90
By performing the heat treatment at a high temperature rising / falling rate of 120 ° C./minute for 120 minutes, it is possible to further suppress the oxidation of the sidewall of the TiN layer. According to this method, the thickness of the oxide on the sidewall of the TiN layer can be reduced to 1 nm or less. The rate of temperature rise and fall of the substrate is not limited to the above value, and the object of the present invention can be achieved as long as the oxidation of the exposed surface of the metal layer forming the electrode is suppressed to at least 20% of the film thickness. You.

Next, a manufacturing process of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. First, the W layer 16, the TiN layer 15, and the polycrystalline silicon layer 14 are sequentially and selectively etched by using normal photolithography and reactive ion etching (RIE) to form a gate electrode shown in FIG. 1
8 was formed.

Next, hydrogen (H ₂ ) and steam (H ₂ O)
In a mixed gas atmosphere (total pressure of 1 atm) using nitrogen (N ₂ ) as a carrier gas, the partial pressure ratio of each gas is set in advance so as to satisfy the TiO ₂ reduction conditions at the time of temperature rise. did. The partial pressure ratio is H ₂ : H ₂ O: N ₂
= 1: 10 ^-8 : 10. By the way, this condition is WO
It is also the reduction condition of ₂ . H ₂ The TiO ₂ in a reducing atmosphere up to 900 ° C. while maintaining a heating rate of 0.99 ° C. / min, a TiN oxide boundary conditions simultaneously gas partial pressure ratio when the temperature becomes constant: H ₂ O: N ₂ = 0.164: 1 × 1
0 ^-4: 0.836 to a varied, it was heated for 120 minutes. Next, the gas partial pressure ratio was changed from the original H ₂ : H ₂ O: N ₂ = 1:
After changing to 10 ⁻⁸ : 10, the temperature was lowered at −90 ° C./min. FIG. 4 shows the change over time in the H ₂ O partial pressure and the substrate temperature at this time.

According to such a heat treatment step, FIG.
As shown in FIG. 3B, only the side wall of the polycrystalline silicon layer 14 and the surface of the silicon substrate 11 are oxidized and exposed to TiN.
No oxide film was formed on the side walls of the layer 15 and the W layer. The oxide film in the edge region of the gate electrode 18 is
It was confirmed that the thickness was increased by about 5 nm.

Subsequently, n-type impurities, for example, arsenic are ion-implanted and activated using the field oxide film 12 and the gate electrode 18 as a mask, thereby activating the surface region of the silicon substrate 11 as shown in FIG. Then, n ⁺ -type diffusion layers 19a and 19b serving as a source and a drain were formed.

According to the second embodiment described above, the oxidation of the side walls of the gate electrode structure other than silicon in the metal electrode structure can be suppressed by the heat treatment step, and the semiconductor device having good gate electrode insulation resistance can be obtained. Can be manufactured.

Further, H ₂ / H at the time of temperature rise and fall shown in this embodiment
_{The 2} O / N ₂ partial pressure can be changed within the range of the following conditions. That is, at the time of temperature rise and fall between the room temperature and the processing temperature, P _H2 / P _{H2O and} logP _N2 are controlled in accordance with the changing temperature so that the conditions for selective oxidation of silicon are constantly satisfied so that the metal layer and the metal are It is also possible to suppress oxidation of the nitride layer.

Next, a manufacturing process of a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. First, the W layer 16, the TiN layer 15, and the polycrystalline silicon layer 14 are sequentially and selectively etched using ordinary photolithography and reactive ion etching (RIE) to form a gate electrode 18 shown in FIG.
Is formed, field oxide film 12 and gate electrode 1 are formed.
N-type impurity 8 as a mask, arsenic is ion-implanted, as shown in FIG. 5 (b), n ⁺ diffusion layers 19a, 19
b is formed.

Next, hydrogen (H ₂ ) and steam (H ₂ O)
In a mixed gas atmosphere using nitrogen (N ₂ ) as a carrier gas (total pressure: 1 atm), the partial pressure ratio of each gas was changed so as to satisfy the conditions for reducing TiO ₂ when the temperature was raised. The partial pressure ratio is H ₂ : H ₂ O: N ₂ = 1: 10.
^-8 : 10. In such a reducing atmosphere of TiO ₂ , the temperature is raised to 1000 ° C. while keeping the temperature rising rate at 150 ° C./min, and at the same time the temperature becomes constant and the gas partial pressure ratio is H ₂ : H.
_The temperature was changed to ₂ O: N ₂ = 0.164: 1 × 10 ⁻⁴ : 0.836, and heating was performed for 1 minute. Next, the gas partial pressure ratio is set to H
After changing to ₂ : H ₂ O: N ₂ = 1: 10 ^-8 : 10,
The temperature was lowered at -90 ° C / min. At this time, it was confirmed that the oxide film in the gate electrode edge region was thickened by about 5 nm.

According to such a heat treatment step, FIG.
As shown in FIG. 3C, the side wall of the polysilicon layer 14 and the silicon substrate 11 are oxidized without oxidation of the W layer 16 / TiN layer 15.
Of the n ⁺ -type diffusion layer 19 serving as a source and a drain for heat treatment at a high temperature and for a short time.
The activation of the ion-implanted impurities can be performed without excessively expanding a and 19b.

According to the third embodiment described above, since the diffusion layer is activated simultaneously with the selective oxidation of silicon, a semiconductor device having good gate electrode insulation resistance can be manufactured without increasing the number of steps. It is possible.

Next, the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention will be described. First, W layer / TiN
The gate electrode 18 is formed by sequentially and selectively etching the layer / polycrystalline silicon layer using normal photolithography and reactive ion etching (RIE).
Next, the gas atmosphere at the time of temperature rise was a mixed gas of steam (H ₂ O) and nitrogen (N ₂ ) (total pressure 1 atm), and the partial pressure ratio of each gas was H ₂ O: N ₂ = 0.01: Set to 10. In such an oxidizing atmosphere, the temperature is raised to 900 ° C. while maintaining the temperature rising rate at 150 ° C./min, and heat treatment is performed at a constant temperature for 10 minutes. As a result, the surface of the W layer / TiN layer / polycrystalline silicon layer was oxidized, and the gate oxide film became thick.

Next, after changing the gas to H ₂ : N ₂ = 1: 10 (total pressure 1 atm), the gas was further reduced to 1 in this reducing atmosphere.
After performing the heat treatment for 0 minutes, the temperature was lowered at a temperature reduction rate of -90 ° C / min. By changing from the oxidizing atmosphere to the reducing atmosphere, the oxide film on the surface of the W layer / TiN layer is completely reduced, but the oxide film on the side surface of the polycrystalline silicon layer and the gate oxide film remain without being reduced. It was possible.

As described above, by alternately performing the oxidation and the reduction, the same effect as the selective oxidation of silicon can be obtained. FIG. 6 shows the amount of oxidation on the surface of the W layer and the amount of W after reduction of WO _X.
Shows the flatness of the surface. If the oxidation amount is 20% or less with respect to the thickness of the W film, the unevenness after reduction can be suppressed to 10 nm or less.

According to the fourth embodiment described above, the oxidation rate can be increased by increasing the partial pressure of water, and the amount of oxidation can be suppressed to a certain limit to reduce the oxidation rate after reduction. Since the flatness of the gate surface is maintained, a process time can be reduced, and a semiconductor device having good gate electrode insulation resistance can be manufactured.

Although the various embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, but uses Pt, Pd, Rh, Ru, Ni, or the like as a metal layer, and uses a metal nitride. ZrN as a layer, HfN, is also applicable to metal laminate structures using, for example, WN _x. The gate electrode is not limited to a laminated structure of a silicon layer, a metal nitride layer, and a metal layer, but is a metal gate in which a metal nitride layer and a metal layer are laminated in this order on a gate insulating film. It may have a structure. In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0052]

As described above in detail, according to the present invention, by controlling the temperature rise and fall rates of the heat treatment of a gate electrode having a multilayer structure, the metal nitride layer and the metal layer constituting the gate electrode can be controlled. Post-gate oxidation can be performed without causing oxidation. Thus, the heat treatment time can be reduced, the thermal load can be reduced, and a semiconductor device with an improved gate breakdown voltage can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a temporal change of a substrate temperature and a partial pressure of water vapor in a heat treatment step in the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a characteristic diagram showing a temporal change of a substrate temperature and a partial pressure of water vapor in a heat treatment step in a second embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 shows W in a heat treatment step according to a fourth embodiment of the present invention.
FIG. 4 is a characteristic diagram showing the oxidation amount of the layer surface and the flatness of the W surface after WO _x reduction.

FIG. 7 is a characteristic diagram showing a relationship between a partial pressure of steam and a temperature rise / fall rate.

FIG. 8 is a characteristic diagram showing the relationship between the partial pressure of gas and the presence or absence of oxidation.

FIG. 9 is a sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 10 is a characteristic diagram showing a temporal change of a substrate temperature and a partial pressure of water vapor in a heat treatment step in a conventional semiconductor device manufacturing process.

[Explanation of symbols]

1 ... p-type silicon substrate 2 ... field insulating film 3a, 3b ... n ⁺ -type diffusion layer 4 ... gate oxide film 5 ... polycrystalline silicon 6 ... metal nitride layer 7 ... W layer 8 ... gate electrode 9 ... TiO ₂ film 11 ... p-type silicon substrate 12 ... field oxide film 13 ... silicon oxide film 14 ... polycrystalline silicon layer 15 ... TiN layer 16 ... W layer 17 ... TiO ₂ film 18 ... gate electrodes 19a, 19b ... n ⁺ type diffusion layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-299273 (JP, A) JP-A-59-132136 (JP, A) JP-A-3-119763 (JP, A) JP-A-2- 32537 (JP, A) JP-A-5-102076 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 29/78

Claims (2)

(57) [Claims] A step of forming a gate electrode having a laminated structure including a metal nitride layer and a metal layer on a silicon substrate via a gate insulating film, and an atmosphere containing a reducing gas, an oxidizing gas and nitrogen. A step of oxidizing the surface of the silicon substrate by performing a heat treatment in the step; and a step of raising and lowering the temperature of the silicon substrate in the atmosphere before and after the step of performing the heat treatment. 50 ° C./min or more such that the thickness of the metal oxide layer formed by oxidizing the metal nitride layer and the metal layer is 20% or less of the thickness of the metal oxide layer and the metal layer, respectively. A method of manufacturing a semiconductor device, wherein the method is performed at a high speed. 2. A step of forming an electrode having a laminated structure including a metal nitride layer and a metal layer on a silicon substrate via a gate insulating film, and performing a heat treatment in an atmosphere containing hydrogen, water vapor and nitrogen. And a step of raising and lowering the temperature of the silicon substrate before and after the step of heat treatment, and oxidizing silicon before or during the step of raising and lowering the temperature. Change in Gibbs free energy in the reaction ΔG ₁ °
(T), change in Gibbs free energy in the oxidation reaction of the metal of the metal layer ΔG ₂ ° (T), and change in Gibbs free energy in the oxidation reaction of the metal nitride Δ
G ₃ ° (T) The method for forming a semiconductor device characterized by so as to satisfy the following formulas (1) to (3), controlling the partial pressure of the gas contained in said atmosphere. ΔG ₁ ° (T) ≧ −4.575 × T × 2 log (P _H2 / P _H2O ) (1) ΔG ₂ ° (T) ≦ −4.575 × T × 2 log (P _H2 / P _H2O ). 2) ΔG ₃ ° (T) ≦ −4.575 × T × {1/2 [logP _N2 + 2log (P _H2 / P _H2O )]} (3)