JPS6072229A - Electrode and wiring structure of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the generation of channeling when electrodes and wirings consisting of high-melting-point metals are arranged in a semiconductor device and impurity layers are formed by self-aligning by ion implantation using said electrodes and wirings as a mask by providing an oxide film consisting of the same metal on the metal surface before the ion implantation. CONSTITUTION:A thick SiO2 film 2 for element isolation is formed on a circumferential portion of a p type Si substrate 1 and a thin gate SiO2 film 3 is arranged on the substrate surface surrounded with said SiO2 film 2 and further the whole surface is coated with a film 4 of a high-melting-point metal such as Mo. Next, a mask 5 of a photoresist film is arranged on the substrate followed by etching using CF4 gas including O2 of 20% of leave the film 4 only in the center of surface. After that, the mask 5 is removed and a heat treatment is performed with 400 deg.C in O2 atmosphere to produce an oxide film 6 on a surface of the exposed film 4. Then this film is used as a mask to implant As ions and an implantation region 7 is formed. Thus, the ions enter deeply because atomic configurations of the metallic oxide and the metal are different and channeling is diminished.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having electrodes and wiring made of a high-melting point metal. The present invention relates to an electrode and wiring structure suitable for a semiconductor device characterized in that the present invention is provided with an electrode and a wiring structure.

MO in which the source and drain are completely formed in a self-aligned manner by implanting arsenic ions using the molybdenum gate electrode as a mask.
It has been reported that in S transistors, molybdenum does not act as a mask for ion implantation, and arsenic can penetrate to the silicon substrate below the gate electrode (Murao et al., Proceedings of the 19th Symposium on Semiconductor Integrated Circuit Technology, p. 96) ,
1980).

In order to prevent this negative effect, the same report describes a method in which ions are implanted after coating the molybdenum surface m1 with a silicon nitride film. In this method, it is necessary to process a stacked film of a molybdenum film and a silicon nitride film as a gate electrode and wiring. Dry etching using plasma etching is used for this process, but in this case, since the etching speeds of molybdenum and silicon nitride films are different,
There was a drawback that microfabrication of microns to 2 microns or the like became difficult.

The purpose of the present invention is to penetrate the implanted element under the electrode and wiring when performing ion implantation as a high melting point gold bullion electrode and wiring mask. It is an object of the present invention to provide an electrode and wiring structure that prevents penetration and solves the difficulty of microfabrication, which is a drawback of conventional penetration prevention measures.

According to LSS theory, for molybdenum and tungsten,
When arsenic ions are fully implanted with an energy of 50 to 100 KeV, the projected range is 1° to 2 Qnm, and the dispersion is about IQnm. Therefore about 3 Q Q nm
A film of molybdenum with a thickness of 100 to 100 mL should perfectly serve as a mask for ion implantation. For this reason, it is explained that the penetration of the arsenic ion implantation described above is due to the channeling effect. The LSS theory assumes that the metal into which ions are implanted is an amorphous body. However, molybdenum and tungsten formed by vapor deposition or sputtering are columnar crystals that extend perpendicularly to the substrate surface, and the crystal grain size is lO~lQQnm (
110). When ions are incident on such a metal film from a vertical direction, the ions approach the atomic array at a small angle, so they enter the film without colliding with the metal atoms due to the effects of repulsive force between them and the metal atoms. Therefore, in the case of such channeling, the energy loss due to collision is small, and the implanted ions penetrate deeply.

In order to prevent such channeling, it is conceivable to form an amorphous film or a thin film with a lattice arrangement different from that of the metal on the metal surface.

The above-mentioned silicon nitride film has been considered as this method, but as already mentioned, it has the drawback that microfabrication is difficult.

The present invention aims to prevent channeling without this drawback. Generally, oxides of high melting point metals differ from the crystalline system of the metal. For example, molybdenum and tungsten are cubic and have a body-centered cubic structure, but their oxides are orthorhombic and have a rutile structure. therefore,
If ion implantation is performed after oxidizing the high melting point metal surface,
Channeling can be suppressed because the atomic arrangement of metal oxide and metal is different. This oxidation of the metal surface can be carried out after the metal has been processed into electrodes and wiring, thereby eliminating the difficulty in microfabrication that was a problem with the silicon nitride coating method described above. Note that when high-melting point metals are oxidized, high-temperature oxidation causes sublimation and pulverization, so it is necessary to oxidize at a low temperature that does not cause these problems.

An embodiment of the present invention will be described below with reference to FIG.

This example is a fine gate electrode MOS transistor.

1OΩ·cm, P (100) The silicon substrate 1e is locally oxidized to form a silicon oxide film 2 for element isolation of 70 Qnm. Subsequently, after forming a gate oxide film 3 of 2 onm, the MOS transistor is formed. In order to adjust the threshold voltage of the transistor, boron was implanted at 60 KeV to a size of 7 x 10" (cII-2). Next, sputtering was performed.

A molybdenum film 4 is formed to a thickness of nm. Subsequently, the photoresist 5 is processed into a desired shape by plasma etching using CF4+20% O2 gas as an entire mask of molybdenum. Next, after removing the resist, 400t? , the molybdenum surface is oxidized to about 5 Qnm in an oxygen atmosphere. Then, arsenic was added to 80KeVT I X 1016Crn-”
Perform ion implantation 7. Next, 500 nm of 1 Q mol cinsilicate glass is deposited 8 by the ThCVD method. After opening the contact hole 9 with butic acid-based enching liquid, 100 (
After heat treatment in a nitrogen atmosphere for 1 to 20 minutes, the molybdenum oxide exposed in the contact hole is removed by the plasma etching method described above to form a silicon-containing sialuminium electrode IO. Subsequently, after performing hydrogen heat treatment at % 450 Cy for 60 minutes, a passivation film was formed. A fine gate electrode MOs transistor is completed.

Arsenic ions penetrated the plate and did not exhibit normal MO8+- transistor characteristics.

MOs with a gate length of 1.4 μm formed according to this example.
The 4-transistor exhibited a threshold voltage of 0.24±0.07V at a power supply voltage of 5V and a substrate bias of -3V. Furthermore, with respect to the designed gate length of 1.4 μm, the processing dimension of molybdenum was 1.4 μm with a standard deviation of 0.2 μm.

[Brief Description of the Drawings] Figure 1 shows the flow of the MOS transistor manufacturing process and cross-sectional views obtained in each process. l... Silicon substrate, 2... Silicon oxide film for separating confectionery, 3... Gate oxide film, 4... Molybdenum,
5...Resist, 6...Molybdenum oxide film, 7...
・Arsenic ion implantation layer, 8... cinsilicate glass, 9...
- Contact hole, 10...1% silicon-containing oxidized aluminum electrode 11...passivation film. Agent: Patent Attorney Fuhai Wagyo) Hesuφ

Claims (1)

[Claims] 1. In a semiconductor device having electrodes and wiring made of a high melting point metal and having an ion implantation step after forming the metal thin film, an oxide film made of the same metal is formed on the surface of the metal before ion implantation. An electrode/wiring structure for a semiconductor device, characterized in that: