JPH0527272B2 - - Google Patents

Info

Publication number
JPH0527272B2
JPH0527272B2 JP4029884A JP4029884A JPH0527272B2 JP H0527272 B2 JPH0527272 B2 JP H0527272B2 JP 4029884 A JP4029884 A JP 4029884A JP 4029884 A JP4029884 A JP 4029884A JP H0527272 B2 JPH0527272 B2 JP H0527272B2
Authority
JP
Japan
Prior art keywords
oxide film
oxygen
gate oxide
metal
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4029884A
Other languages
Japanese (ja)
Other versions
JPS60186064A (en
Inventor
Hidenao Tanaka
Kinya Kato
Tsutomu Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP4029884A priority Critical patent/JPS60186064A/en
Publication of JPS60186064A publication Critical patent/JPS60186064A/en
Publication of JPH0527272B2 publication Critical patent/JPH0527272B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、シリコン基板上のMOSFETの製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a MOSFET on a silicon substrate.

(従来技術) シリコン基板上のMOSFETは集積回路に広く
用いられており、さらに集積密度を大きくするた
め、素子寸法の微細化がはらられている。これに
伴いMOSFETのゲート酸化膜も20nm程度の薄
い膜も用いられるようになつた。ところが従来の
MOSFETの製造方法では、ゲート酸化膜をシリ
コン基板の素子領域に熱酸化により形成した後
に、ゲート電極、ソース、ドレイン領域の形成な
ど各種の処理工程を経るため次に示す問題があ
り、素子寸法を微細化しゲート酸化膜を薄くする
と歩留りの良い素子形成が困難であるという欠点
があつた。すなわち、(イ)ゲート酸化膜形成後、ゲ
ート電極材の堆積を行うまでの間の汚染により、
ゲート酸化膜の絶縁耐圧が劣化する。(ロ)ゲート酸
化膜形成後に、イオン衝撃を利用した工程、たと
えばプラズマCVD法、スパツタ法による膜堆積、
反応性イオンエツチング法によるパタン加工、あ
るいは不純物イオン打込み等を用いると、帯電に
よりゲート酸化膜が絶縁破壊を起こす。(ハ)ゲート
酸化膜形成後に、ゲート電極材のアニールや、不
純物イオンの活性化のため高温の熱処理を行なう
と、ゲート電極材の拡散が起り、ゲート酸化膜の
侵食破壊を起こす。
(Prior Art) MOSFETs on silicon substrates are widely used in integrated circuits, and in order to further increase the integration density, efforts are being made to miniaturize the element dimensions. Along with this, gate oxide films for MOSFETs have started to be thinner, about 20 nm thick. However, the conventional
The MOSFET manufacturing method involves forming a gate oxide film on the element area of a silicon substrate by thermal oxidation, and then going through various processing steps such as forming the gate electrode, source, and drain regions, which poses the following problems. A drawback of miniaturization and thinning of the gate oxide film is that it is difficult to form devices with good yield. In other words, (a) contamination after the gate oxide film is formed and before the gate electrode material is deposited;
The dielectric strength of the gate oxide film deteriorates. (b) After forming the gate oxide film, a process using ion bombardment, such as plasma CVD method or sputtering method, is used to deposit the film.
When patterning by reactive ion etching or impurity ion implantation is used, dielectric breakdown of the gate oxide film occurs due to charging. (c) After the gate oxide film is formed, if high-temperature heat treatment is performed to anneal the gate electrode material or activate impurity ions, diffusion of the gate electrode material occurs, causing erosion and destruction of the gate oxide film.

これらは素子微細化にともない、ゲート酸化膜
がますます薄くなること、素子製造がイオン利用
技術にますます頼らざるを得ないことにより、素
子製造上大きな問題点として顕在化されつつあ
る。
These are becoming apparent as major problems in device manufacturing, as gate oxide films become thinner and thinner with device miniaturization, and device manufacturing has to rely more and more on ion-utilizing technology.

(発明の目的) 本発明はこれらの欠点を除去するために提案さ
れたもので、ゲート電極の形成後にゲート電極と
シリコン基板の界面での反応によつてゲート酸化
膜を形成することを特徴とし、その目的は素子製
造中に薄いゲート酸化膜の絶縁破壊を生ずること
なく歩留り良くMOSFETを形成することにあ
る。
(Objective of the Invention) The present invention has been proposed to eliminate these drawbacks, and is characterized by forming a gate oxide film by a reaction at the interface between the gate electrode and the silicon substrate after forming the gate electrode. The purpose is to form MOSFETs with high yield without causing dielectric breakdown of the thin gate oxide film during device manufacturing.

(発明の構成) 上記の目的を達成するため、本発明はシリコン
基板上にMOSFETを製造する工程において、素
子領域となるべきシリコン露出領域を覆つて酸素
を含有する金属層を堆積する工程と、該金属層を
エツチングしゲート電極を形成する工程と、還元
性ガス種を透過し、かつ該金属から発生する酸素
の透過を抑制する層間絶縁膜を堆積する工程と、
該還元性ガス種を含む雰囲気中の熱処理により、
前記シリコン基板と前記ゲート電極の界面にゲー
ト酸化膜を生成する工程とを順に含むことを特徴
とするMOSFETの製造方法を発明の要旨とする
ものである。
(Structure of the Invention) In order to achieve the above object, the present invention includes a step of depositing a metal layer containing oxygen to cover an exposed silicon region that is to become an element region in a step of manufacturing a MOSFET on a silicon substrate. a step of etching the metal layer to form a gate electrode; a step of depositing an interlayer insulating film that transmits reducing gas species and suppresses permeation of oxygen generated from the metal;
By heat treatment in an atmosphere containing the reducing gas species,
The gist of the invention is a method for manufacturing a MOSFET, which includes the steps of sequentially forming a gate oxide film at the interface between the silicon substrate and the gate electrode.

次に本発明の実施例を説明する。なお実施例は
一つの例示であつて、本発明の精神を逸脱しない
範囲で、種々の変更あるいは改良を行いうること
は云うまでもない。
Next, examples of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

本発明はシリコンと酸素を含む金属との界面に
おいて、熱処理により該界面にシリコン酸化膜が
形成される反応を利用する。この反応を利用すれ
ば、シリコン酸化膜からなるゲート酸化膜の形成
をゲート電極形成後に実施できるので、ゲート酸
化膜の表面汚染やゲート電極形成時の破壊を回避
することができる。さらにゲート電極材のアニー
ル等のために、従来はゲート酸化膜形成後に行な
つていた高温の熱処理を、ゲート酸化膜形成と同
時に行なうことができ、酸化膜形成後の熱処理に
よるゲート酸化膜の破壊を回避できる。
The present invention utilizes a reaction in which a silicon oxide film is formed at the interface between silicon and a metal containing oxygen through heat treatment. By utilizing this reaction, a gate oxide film made of a silicon oxide film can be formed after the gate electrode is formed, so that surface contamination of the gate oxide film and destruction during formation of the gate electrode can be avoided. Furthermore, high-temperature heat treatment for annealing the gate electrode material, which was conventionally performed after forming the gate oxide film, can be performed simultaneously with the formation of the gate oxide film. can be avoided.

本発明で用いるシリコン酸化膜の形成反応は以
下の原理に基づく。一般にシリコンと酸素の親和
力は金属と酸素の親和力より大きいため、シリコ
ンに酸素を含む金属が接しているとすれば、常温
で変化は見られないが、高温に曝すとシリコンの
酸化が生じる。高温では、金属自体の再結晶や、
金属中の酸素の拡散係数の増大により、酸素がシ
リコンに結びつく確率が増加するが、効率よくシ
リコン酸化膜を形成するためには、次の2条件が
必要である。すなわち、還元性雰囲気中での熱処
理を行ない、金属中の酸素の遊離を促進すると共
に、金属上に酸素を透過しない膜を設け、外部へ
の酸素の放出を抑制することである。
The formation reaction of the silicon oxide film used in the present invention is based on the following principle. In general, the affinity between silicon and oxygen is greater than the affinity between metal and oxygen, so if silicon is in contact with a metal containing oxygen, no change will be observed at room temperature, but when exposed to high temperatures, oxidation of the silicon will occur. At high temperatures, the metal itself recrystallizes,
An increase in the diffusion coefficient of oxygen in metal increases the probability that oxygen will bond to silicon, but the following two conditions are required to form a silicon oxide film efficiently. That is, heat treatment is performed in a reducing atmosphere to promote the release of oxygen in the metal, and a film that does not allow oxygen to pass is provided on the metal to suppress the release of oxygen to the outside.

以上の原理から本発明の製造方法では、次の要
件を満足する必要がある。まず金属の種類である
が、酸化膜形成熱処理の温度(800〜1100℃)に
おいて、金属酸化物とシリコンの反応における自
由エネルギーの変化が負であることが、上記反応
を起させる基本要件である。さらに酸素を含有し
得て、なおかつ高温で安定な金属を選ぶ必要があ
る。これらの要件を満足する金属としては、モリ
ブデン、タングステン、クロム、バナジウム、ニ
オブ、タンタルが挙げられる。中でもモリブデ
ン、タングステンは酸素を含有しても比抵抗が小
であり、耐熱性に優れているため、本発明の製造
方法に適している。
Based on the above principle, the manufacturing method of the present invention needs to satisfy the following requirements. First, regarding the type of metal, the basic requirement for the above reaction to occur is that the change in free energy in the reaction between the metal oxide and silicon is negative at the temperature of the oxide film forming heat treatment (800 to 1100 degrees Celsius). . Furthermore, it is necessary to select a metal that can contain oxygen and is stable at high temperatures. Metals that meet these requirements include molybdenum, tungsten, chromium, vanadium, niobium, and tantalum. Among them, molybdenum and tungsten have low resistivity even when they contain oxygen and have excellent heat resistance, so they are suitable for the manufacturing method of the present invention.

一方、前述のようにシリコン酸化膜形成には金
属中の酸素が使われるため、シリコン酸化膜形成
の再現性を良くするためには熱処理条件などと共
に金属中の酸素量の制御が重要な要件となる。金
属中に酸素を含有させる方法としては、微量酸素
中での蒸着法、化学的気相成長法、あるいは酸素
を含有するガス雰囲気中でのスパツタ法を用いる
ことが可能である。特にスパツタ法を用いると、
ガス分圧調整により金属中の酸素量を広く変化さ
せることができ、しこも再現性よく制御しうるこ
とを見出した。たとえば金属の種類にも依存する
が、スパツタ時の酸素分圧により、金属中の酸素
量を40at.%まで制御でき、シリコン酸化膜形成
に十分な酸素量を含有させることができた。
On the other hand, as mentioned above, oxygen in the metal is used to form a silicon oxide film, so controlling the amount of oxygen in the metal as well as heat treatment conditions is an important requirement to improve the reproducibility of silicon oxide film formation. Become. As a method for incorporating oxygen into the metal, it is possible to use a vapor deposition method in a trace amount of oxygen, a chemical vapor deposition method, or a sputtering method in an oxygen-containing gas atmosphere. Especially when using the spatuta method,
We have found that the amount of oxygen in the metal can be varied over a wide range by adjusting the gas partial pressure, and that the formation of particles can be controlled with good reproducibility. For example, although it depends on the type of metal, the amount of oxygen in the metal can be controlled to 40 at.% by adjusting the oxygen partial pressure during sputtering, making it possible to contain enough oxygen to form a silicon oxide film.

シリコン酸化膜形成のための熱処理時の雰囲気
としては、金属中の酸素の遊離を促進するため、
金属に対して還元性のガス種を含むことが必要で
あり、物質中の透過性が優れた水素を含む還元性
雰囲気が適しているが、原理的にこれに限定され
るものではない。
The atmosphere during heat treatment to form a silicon oxide film is as follows:
It is necessary to contain a gas species that is reducing to the metal, and a reducing atmosphere containing hydrogen with excellent permeability in the substance is suitable, but is not limited thereto in principle.

さらに、熱処理時に金属から遊離した酸素をシ
リコンの界面での反応に有効に用いるためには、
酸素の金属表面から外部への放出を抑制すること
が重要である。このため、前述の還元性のガス種
は透過するが、酸素の放出は抑制できる膜を金属
上に堆積することが必要である。この膜の材質と
しては、半導体素子の層間絶縁膜として良く用い
られ、水素は良く透過するのに比べ酸素は透過し
にくい二酸化シリコン膜が適しているが、上記の
条件を満足していれば、これに限定されるもので
はない。
Furthermore, in order to effectively use the oxygen liberated from the metal during heat treatment for the reaction at the silicon interface,
It is important to suppress the release of oxygen from the metal surface to the outside. For this reason, it is necessary to deposit a film on the metal that allows the above-mentioned reducing gas species to permeate but suppresses the release of oxygen. A suitable material for this film is silicon dioxide, which is often used as an interlayer insulating film in semiconductor devices and which is permeable to hydrogen but is less permeable to oxygen.If the above conditions are met, It is not limited to this.

なお水素を含む還元性雰囲気中の熱処理を用い
ると、シリコン酸化膜厚は、金属中の酸素量、熱
処理温度、熱処理雰囲気中の水素含有量、熱処理
時間により制御でき、6nm〜50nm程度の膜厚は
容易に再現性良く形成できる。また、絶縁耐圧は
11MV/cm程度の良好な値となり、さらにシリコ
ンとシリコン酸化膜界面の表面準位は通常の熱酸
化で形成したものと同等であり、MOSFETのゲ
ート酸化膜として十分な特性を有する。
Note that when heat treatment is used in a reducing atmosphere containing hydrogen, the silicon oxide film thickness can be controlled by the amount of oxygen in the metal, heat treatment temperature, hydrogen content in the heat treatment atmosphere, and heat treatment time, and a film thickness of about 6 nm to 50 nm can be achieved. can be easily formed with good reproducibility. Also, the insulation voltage is
It has a good value of about 11 MV/cm, and the surface state at the interface between silicon and silicon oxide film is equivalent to that formed by normal thermal oxidation, and has sufficient characteristics as a gate oxide film for a MOSFET.

以下、本発明を実施例について説明する。 Hereinafter, the present invention will be explained with reference to examples.

実施例 1 第1図A〜Gは本発明による第1の実施例であ
るpチヤンネルMOSFETの製造方法を工程順に
示す。
Embodiment 1 FIGS. 1A to 1G show a method for manufacturing a p-channel MOSFET according to a first embodiment of the present invention in the order of steps.

比抵抗3〜5Ωcmの(100)面n型シリコン基
板1の表面に水蒸気酸化法によりフイールド酸化
膜2を形成し、フオトエツチング工程により開口
して素子領域3を形成した。(A) 従来のMOSFETの製造方法では、次にゲート
酸化膜の形成を行なうのが通例であるが、本方法
ではゲート酸化膜形成を行なわず、素子領域3の
シリコン露出領域に直接ゲート電極となるべき酸
素を含むモリブデン4を約300nm堆積した。酸
素を含むモリブデンはアルゴンに酸素を約10%、
分圧で約0.13Pa混合したガス中での反応性スパツ
タ法により堆積した。モリブデン中には、約
30at.%の酸素が含まれるが、比抵抗は約3×
10-5Ωcmとなり電極配線として使用可能であつ
た。(B) 次いでフオト工程によりゲート電極部をレジス
ト5で覆い、他の部分をCCl2F2と酸素を混合し
たガスによる反応性イオンエツチングで除去し、
ゲート電極6の形状加工を行なつた。(C) 次いでこのレジスト5とゲート電極6およびフ
イールド酸化膜2をマスクとして用い、B+イオ
ンを40KeVで5×1015個/cm2打込み、ソース、ド
レイン領域7,8を形成した。(D) 次いで、レジスト5を酸素プラズマ中で灰化し
て除去した後、ゲート酸化膜形成の熱処理時に水
素を透過し、かつ酸素のゲート電極金属表面から
の放出を抑制する膜として、二酸化シリコン膜9
をスパツタ法により約800nm堆積した。なお、
この二酸化シリコン膜9は層間絶縁膜としても機
能させた。(E) 次いで水素を50%含む窒素中で900℃60分の熱
処理を行ない、ゲート電極6とシリコン基板1の
界面に約50nmのゲート酸化膜10を形成した。
また、この熱処理により、ソース、ドレイン領域
7,8に打込んだ不純物の活性化を行ない、シー
ト抵抗を約50Ω/□にできた。(F) 次いでフオトエツチング工程により、コンタク
トホール11,12,13をあけ、さらにアルミ
ニウム合金(シリコン3at.%含有)層をスパツタ
法により堆積した後に、フオトエツチング工程に
よりアルミニウム合金配線14,15,16を形
成してMOSFETを製造した。(G) 本実施例により製造したpチヤネルMOSFET
は従来法で製造したMOSFETと同等の特性を示
し、しきい値電圧は約−1.9Vであつた。また測
定以前の素子製造工程でゲート酸化膜が破壊され
ていた素子数を単位面積当りのゲート酸化膜の欠
陥に換算すると、約50個/cm2となり、工程中の絶
縁破壊の少ないMOSFETの形成が可能であつ
た。
A field oxide film 2 was formed on the surface of a (100) plane n-type silicon substrate 1 having a resistivity of 3 to 5 Ωcm by a steam oxidation method, and an opening was formed by a photoetching process to form an element region 3. (A) In conventional MOSFET manufacturing methods, a gate oxide film is usually formed next, but in this method, a gate oxide film is not formed and a gate electrode is directly formed on the exposed silicon region of the device region 3. About 300 nm of molybdenum 4 containing oxygen was deposited. Molybdenum containing oxygen is about 10% oxygen in argon,
It was deposited by the reactive sputtering method in a mixed gas with a partial pressure of about 0.13 Pa. Molybdenum contains about
Contains 30at.% oxygen, but the specific resistance is approximately 3×
It was 10 -5 Ωcm and could be used as electrode wiring. (B) Next, the gate electrode part is covered with resist 5 by a photo process, and the other part is removed by reactive ion etching using a gas mixed with CCl 2 F 2 and oxygen.
The shape of the gate electrode 6 was processed. (C) Next, using this resist 5, gate electrode 6, and field oxide film 2 as a mask, B + ions were implanted at 5×10 15 /cm 2 at 40 KeV to form source and drain regions 7 and 8. (D) Next, after the resist 5 is ashed and removed in oxygen plasma, a silicon dioxide film is formed as a film that transmits hydrogen and suppresses the release of oxygen from the gate electrode metal surface during the heat treatment for forming the gate oxide film. 9
was deposited to a thickness of approximately 800 nm using the sputtering method. In addition,
This silicon dioxide film 9 also functioned as an interlayer insulating film. (E) Next, heat treatment was performed at 900° C. for 60 minutes in nitrogen containing 50% hydrogen to form a gate oxide film 10 with a thickness of about 50 nm at the interface between the gate electrode 6 and the silicon substrate 1.
Further, by this heat treatment, the impurities implanted into the source and drain regions 7 and 8 were activated, and the sheet resistance was made approximately 50Ω/□. (F) Next, contact holes 11, 12, 13 are formed by a photo-etching process, and an aluminum alloy (containing 3 at.% silicon) layer is deposited by sputtering, and then aluminum alloy wirings 14, 15, 16 are formed by a photo-etching process. A MOSFET was manufactured by forming the following. (G) p-channel MOSFET manufactured according to this example
exhibited characteristics equivalent to those of MOSFETs manufactured by conventional methods, and the threshold voltage was approximately -1.9V. Furthermore, if we convert the number of devices whose gate oxide film was destroyed in the device manufacturing process prior to measurement into defects in the gate oxide film per unit area, it will be approximately 50 defects/cm 2 , making it possible to create MOSFETs with less dielectric breakdown during the process. was possible.

実施例 2 実施例1において比抵抗3〜5Ωのn型基板の
代りに比抵抗3〜5Ω(100)面p型基板を用い、
ソース、ドレイン領域形成のためB+イオンの代
りにAS +イオンを130KeVで5×1015個/cm2打込
むことにより、しきい値電圧約0.15Vのnチヤネ
ルMOSFETを形成できた。このMOSFETの特
性は、従来法で製造したMOSFETと同等であ
り、ゲート酸化膜の絶縁破壊の数は実施例1と同
様に少なく、歩留りの良いMOSFETの形成が可
能であつた。
Example 2 In Example 1, a p-type substrate with a specific resistance of 3 to 5 Ω (100) was used instead of the n-type substrate with a specific resistance of 3 to 5 Ω,
By implanting 5×10 15 /cm 2 of A S + ions at 130 KeV instead of B + ions to form the source and drain regions, an n-channel MOSFET with a threshold voltage of about 0.15 V was formed. The characteristics of this MOSFET were equivalent to those of the MOSFET manufactured by the conventional method, and the number of dielectric breakdowns of the gate oxide film was as small as in Example 1, making it possible to form a MOSFET with a high yield.

実施例 3 実施例1において酸素を含むモリブデンの代り
に酸素を含むタングステンを用い、水素を10%含
む窒素雰囲気中1000℃60分の熱処理を行なうこと
により、ゲート酸化膜厚が実施例1と同じ約50n
mのpチヤネルMOSFETが形成でき、しきい値
電圧は約−1.5Vであつた。この場合にはゲート
電極をタングステンにしたことにより、電極の比
抵抗は約6×10-5Ωcmとなつた。ゲート酸化膜の
絶縁破壊の数は、やはり実施例1と同様に少な
く、歩留りの良いMOSFETの形成が可能であつ
た。
Example 3 The gate oxide film thickness was the same as in Example 1 by using tungsten containing oxygen instead of molybdenum containing oxygen in Example 1 and performing heat treatment at 1000°C for 60 minutes in a nitrogen atmosphere containing 10% hydrogen. Approximately 50n
m p-channel MOSFETs were formed, and the threshold voltage was approximately -1.5V. In this case, by using tungsten as the gate electrode, the specific resistance of the electrode was approximately 6×10 -5 Ωcm. The number of dielectric breakdowns in the gate oxide film was also small as in Example 1, and it was possible to form a MOSFET with a high yield.

(発明の効果) 以上説明したように本発明によれば、ゲート酸
化膜形成前にゲート電極の形成を終了しているた
め、ゲート酸化膜表面が大気に曝されず汚染によ
る絶縁耐圧の劣化が防止できると共に、ゲート電
極形成などの工程での帯電によるゲート酸化膜の
絶縁破壊を生ずることがなく、さらにゲート電極
材のアニールやソース、ドレイン領域の不純物活
性化などのため、従来はゲート酸化膜形成後に行
なつていた高温の熱処理を、ゲート酸化膜形成と
同時にでき、ゲート電極材の侵食によるゲート酸
化膜の破壊を回避できるので、薄いゲート酸化膜
のMOSFETを歩留り良く形成できる利点があ
る。
(Effects of the Invention) As explained above, according to the present invention, since the formation of the gate electrode is completed before the formation of the gate oxide film, the surface of the gate oxide film is not exposed to the atmosphere, thereby preventing deterioration of dielectric strength due to contamination. In addition, it does not cause dielectric breakdown of the gate oxide film due to charging during processes such as gate electrode formation, and it also prevents dielectric breakdown of the gate oxide film due to charging during processes such as gate electrode formation. The high-temperature heat treatment that was previously performed after formation can be performed at the same time as gate oxide film formation, and destruction of the gate oxide film due to erosion of the gate electrode material can be avoided, so there is an advantage that MOSFETs with thin gate oxide films can be formed with high yield.

さらに同一熱処理によりゲート酸化膜の形成及
びソース、ドレイン領域の活性化を同時に行いう
るのでFETの製造能率を高めうる利点をも有す
る。
Furthermore, since the formation of the gate oxide film and the activation of the source and drain regions can be performed simultaneously by the same heat treatment, it also has the advantage of increasing the manufacturing efficiency of FETs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のMOSFETの製造方法を工程
順に示したものである。 1……シリコン基板、2……フイールド酸化
膜、3……素子領域、4……酸素を含むモリブデ
ン、5……レジスト、6……ゲート電極、7,8
……ソース、ドレイン領域、9……二酸化シリコ
ン膜、10……ゲート酸化膜、11,12,13
……コンタクトホール、14,15,16……ア
ルミニウム合金配線。
FIG. 1 shows the method for manufacturing a MOSFET according to the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Field oxide film, 3...Element region, 4...Molybdenum containing oxygen, 5...Resist, 6...Gate electrode, 7, 8
... Source, drain region, 9 ... Silicon dioxide film, 10 ... Gate oxide film, 11, 12, 13
... Contact hole, 14, 15, 16 ... Aluminum alloy wiring.

Claims (1)

【特許請求の範囲】 1 シリコン基板上にMOSFETを製造する工程
において、素子領域となるべきシリコン露出領域
を覆つて酸素を含有する金属層を堆積する工程
と、該金属層をエツチングしゲート電極を形成す
る工程と、還元性ガス種を透過し、かつ該金属か
ら発生する酸素の透過を抑制する層間絶縁膜を堆
積する工程と、該還元性ガス種を含む雰囲気中の
熱処理により、前記シリコン基板と前記ゲート電
極の界面にゲート酸化膜を生成する工程とを順に
含むことを特徴とするMOSFETの製造方法。 2 金属層として、モリブデン、タングステン、
クロム、バナジウム、ニオブ、タンタルのいずれ
かあるいはこれらの合金を用いることを特徴とす
る特許請求の範囲第1項記載のMOSFETの製造
方法。 3 酸素を含有する金属層の堆積方法として、酸
素を含有するガス雰囲気中でスパツタ法により形
成することを特徴とする特許請求の範囲第1項記
載のMOSFETの製造方法。
[Claims] 1. In the process of manufacturing a MOSFET on a silicon substrate, a process of depositing a metal layer containing oxygen to cover an exposed silicon region that is to become an element region, and etching the metal layer to form a gate electrode. the silicon substrate by a step of forming an interlayer insulating film that transmits a reducing gas species and suppresses the transmission of oxygen generated from the metal, and a heat treatment in an atmosphere containing the reducing gas species. and forming a gate oxide film at the interface of the gate electrode. 2 As a metal layer, molybdenum, tungsten,
2. The method for manufacturing a MOSFET according to claim 1, wherein any one of chromium, vanadium, niobium, tantalum, or an alloy thereof is used. 3. The method of manufacturing a MOSFET according to claim 1, wherein the metal layer containing oxygen is deposited by sputtering in an oxygen-containing gas atmosphere.
JP4029884A 1984-03-05 1984-03-05 Manufacture of mosfet Granted JPS60186064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4029884A JPS60186064A (en) 1984-03-05 1984-03-05 Manufacture of mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4029884A JPS60186064A (en) 1984-03-05 1984-03-05 Manufacture of mosfet

Publications (2)

Publication Number Publication Date
JPS60186064A JPS60186064A (en) 1985-09-21
JPH0527272B2 true JPH0527272B2 (en) 1993-04-20

Family

ID=12576702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4029884A Granted JPS60186064A (en) 1984-03-05 1984-03-05 Manufacture of mosfet

Country Status (1)

Country Link
JP (1) JPS60186064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0754723A (en) * 1993-08-19 1995-02-28 Komatsu Zenoah Co Engine case

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0754723A (en) * 1993-08-19 1995-02-28 Komatsu Zenoah Co Engine case

Also Published As

Publication number Publication date
JPS60186064A (en) 1985-09-21

Similar Documents

Publication Publication Date Title
JP2937817B2 (en) Method of forming oxide film on semiconductor substrate surface and method of manufacturing MOS semiconductor device
JPS6072272A (en) Manufacture of semiconductor device
KR20030044800A (en) Semiconductor device having a low-resistance gate electrode
JPS609160A (en) Semiconductor device and manufacture thereof
JPH0527272B2 (en)
JPS59200418A (en) Manufacture of semiconductor device
JP2997554B2 (en) Method for manufacturing semiconductor device
JPS6261345A (en) Manufacture of semiconductor device
JP2918914B2 (en) Semiconductor device and manufacturing method thereof
JPS5966165A (en) Electrode wiring and manufacture thereof
JPH11186548A (en) Semiconductor device and manufacture thereof
JP3067433B2 (en) Method for manufacturing semiconductor device
JPH0227769A (en) Semiconductor device
JPS58155767A (en) Manufacture of metal oxide semiconductor type semiconductor device
JP3238804B2 (en) Method for manufacturing semiconductor device
JPH02103930A (en) Manufacture of semiconductor device
JPH04158516A (en) Manufacture of semiconductor device
JPH07147403A (en) Semiconductor device and manufacture thereof
JPH04155967A (en) Manufacture of semiconductor device
JPS61288427A (en) Manufacture of semiconductor device
JPS59161072A (en) Semiconductor device
JPS6057974A (en) Manufacture of semiconductor device
JPS6167270A (en) Semiconductor device
KR100356817B1 (en) Method of forming contacts in semiconductor devices
JP2668380B2 (en) Method for manufacturing semiconductor device