JPH0671076B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0671076B2 JPH0671076B2 JP59270885A JP27088584A JPH0671076B2 JP H0671076 B2 JPH0671076 B2 JP H0671076B2 JP 59270885 A JP59270885 A JP 59270885A JP 27088584 A JP27088584 A JP 27088584A JP H0671076 B2 JPH0671076 B2 JP H0671076B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- semiconductor device
- oxide
- free energy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に関し、詳しくは、絶縁膜の変質と
電極・配線の剥離の防止に有効な、高融点金属膜からな
る電極・配線を備えた半導体装置に関する。Description: FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more specifically, to an electrode / wiring made of a refractory metal film, which is effective for preventing deterioration of an insulating film and peeling of the electrode / wiring. Semiconductor device.
従来、MOS素子の電極・配線には多結晶シリコンが用い
られてきた。しかし、素子の高集積化と高速化のために
は、多結晶シリコンより抵抗抗の材料が必要である。従
つて、電極・配線の材料として純金属が使えれば理想的
であるが、これには次のような問題がある。即ち、製造
工程中に金属が、絶縁膜であるSiO2（二酸化シリコン）
膜からはがれてしまつたり、高温熱処理中に金属とSiO2
が反応して、絶縁耐圧不良等の素子特性の劣化を引起こ
す心配がある。等の問題がある。特に、高融点金属膜と
SiO2膜との接着性が不充分であるという問題はデバイス
の信頼性に大きく影響するので解決が強く望まれてい
た。Conventionally, polycrystalline silicon has been used for the electrodes and wirings of MOS elements. However, for higher integration and higher speed of the device, a material having resistance higher than that of polycrystalline silicon is required. Therefore, it would be ideal if pure metal could be used as the material for the electrodes and wiring, but this has the following problems. That is, during the manufacturing process, the metal is SiO 2 (silicon dioxide), which is an insulating film.
It peels off from the film, and metal and SiO 2
May react with each other to cause deterioration of element characteristics such as insulation breakdown voltage failure. There is a problem such as. In particular, with refractory metal films
Since the problem of insufficient adhesion with the SiO 2 film has a great influence on the reliability of the device, it has been strongly desired to solve the problem.
本発明の目的は、絶縁膜特にSiO2膜上に形成する電極・
配線として高融点金属膜を用いる半導体装置において、
絶縁膜の変質を防止でき、かつ、高融点金属膜と絶縁膜
との接着性を良くすることのできる半導体装置を提供す
ることにある。An object of the present invention is to form an electrode, which is formed on an insulating film, particularly a SiO 2 film.
In a semiconductor device using a refractory metal film as wiring,
It is an object of the present invention to provide a semiconductor device capable of preventing the deterioration of the insulating film and improving the adhesiveness between the refractory metal film and the insulating film.
半導体素子を製造するに際しては、絶縁膜と電極・配線
膜が接触した状態で、約1000℃の高温で加熱される。電
極・配線に高融点金属を使う場合、金属の酸化物の生成
自由エネルギーがSiO2のそれより負で絶対値が大きい
（即ち、生成自由エネルギーがSiO2のそれより低い）と
きには、金属とSiO2とは反応してしまう。一方、金属の
酸化物の生成自由エネルギーがSiO2のそれより負で絶対
値が小さい場合には、金属とSiO2とは反応しにくいはず
である。（生成自由エネルギーが正のときは、不安定な
ので、問題外である。）ところが、約1000℃の高温で
は、SiO2そのものの安定性も問題になる。即ち、金属と
SiO2とが反応しにくくても、金属に含まれる酸素が少な
くなると、SiO2の解離が認められる場合がある。従つ
て、金属膜とSiO2膜間に酸化物層を設けることが上記Si
O2の解離を防止するのに有効である。しかし、多くの場
合、酸化物は化学量論組成にはならないので、そのとき
酸素が不足していると、この酸化物としての生成自由エ
ネルギーがSiO2のそれより低いものを使うと、SiO2が還
元される場合があるので危険である。このような理由か
ら、本発明では、第１図に示すように、絶縁膜（SiO
2膜）３と高融点金属膜（ゲート電極）１との間に、生
成自由エネルギーの絶対値がSiO2のそれより小さい酸化
物に、生成自由エネルギーの絶対値がSiO2のそれと同じ
か大きい酸化物を１〜50％混合させた界面層２を設ける
構成とする。When manufacturing a semiconductor element, the insulating film and the electrode / wiring film are in contact with each other and heated at a high temperature of about 1000 ° C. When refractory metal is used for electrodes / wiring, if the free energy of formation of metal oxide is negative and the absolute value is larger than that of SiO 2 (that is, the free energy of formation is lower than that of SiO 2 ), metal and SiO It reacts with 2 . On the other hand, when the free energy of formation of the metal oxide is negative and smaller in absolute value than that of SiO 2 , the metal and SiO 2 should not react easily. (If the free energy of formation is positive, it is unstable because it is unstable.) However, at a high temperature of about 1000 ° C, the stability of SiO 2 itself becomes a problem. That is, with metal
Even when the SiO 2 is less likely to react, the oxygen contained in the metal decreases, there is a case where the dissociation of SiO 2 is observed. Therefore, it is necessary to form an oxide layer between the metal film and the SiO 2 film.
It is effective in preventing the dissociation of O 2 . However, in many cases, since not a oxide stoichiometry, when the time the oxygen is insufficient, the free energy as the oxide using lower than that of SiO 2, SiO 2 May be returned, which is dangerous. For this reason, in the present invention, as shown in FIG.
Between the 2 films) 3 and 1 refractory metal film (gate electrode), the absolute value of the free energy of formation in less oxide than that of SiO 2, the absolute value of the free energy is greater or equal to that of SiO 2 The structure is such that the interface layer 2 containing 1 to 50% of oxide is provided.
以下、図面により本発明の実施例を説明する。第１図は
実施例の断面図で、１は高融点金属膜のゲート電極、２
は界面層、３はSiO2膜、４はSi単結晶基板を示す。タン
グステン（Ｗ）をゲート電極１としたMOS半導体素子
を、２種類の被着法と２種類の界面層について形成し
た。上記膜の形成には、CVD（Chemical Vapor Depositi
on）法とスパッタ法を用いた。CVD法ではふつ化タング
ステン（WF6）を原料ガスに用い、Si添加のためにはSiH
4を混合した。界面層の酸化物形成には、蒸着初期にCVD
雰囲気中に存在するO2や水（H2O）を利用した。スパツ
タ法ではＷとSiのターゲツトを用い、初期にO2を微量導
入して同時スパツタすることにより酸化物層を形成し
た。上記の、２種類の被着法と、２種類の界面層との組
合せから成る４種類の試料I,II,III,IVについて、ゲー
ト電極１とSiO2膜３との接着性の良否、SiO2膜３の変質
の有無を調べた結果を第２図に示す。なお、界面層（酸
化物層）２の厚さは、いずれも5nmである。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the embodiment, 1 is a gate electrode of a refractory metal film, 2
Indicates an interface layer, 3 indicates a SiO 2 film, and 4 indicates a Si single crystal substrate. MOS semiconductor elements using tungsten (W) as the gate electrode 1 were formed for two types of deposition methods and two types of interface layers. CVD (Chemical Vapor Depositi
on) method and sputtering method were used. In the CVD method, tungsten fluoride (WF 6 ) is used as the source gas, and SiH is added to add Si.
4 were mixed. To form the oxide in the interface layer, use CVD
O 2 and water (H 2 O) existing in the atmosphere were used. In the sputtering method, a target of W and Si was used, and a small amount of O 2 was initially introduced and simultaneous sputtering was performed to form an oxide layer. Regarding the four types of samples I, II, III, and IV, which consist of a combination of the above-mentioned two types of deposition methods and two types of interface layers, whether the adhesion between the gate electrode 1 and the SiO 2 film 3 is good or not, SiO FIG. 2 shows the results of examining the presence or absence of alteration of the 2 film 3. The thickness of each of the interface layers (oxide layers) 2 is 5 nm.
第２図に見られるように、CVD法を用いたとき、界面層
がWO3だけの場合、高融点金属膜（ゲート電極１）とSiO
2膜３との接着性が悪かつたが、界面層を、10％のSiO2
を含むWO3とした試料IIでは、約1000℃の加熱により良
好な接着性が得られた。スパツタ法によつて得られた試
料III,IVは、第２図に示す通り、WO3中のSiO2の有無に
かかわらず接着性は良かつたが、SiO2をWO3中に含む試
料IVの方が、試料IIIより接着性が良かつた。結局、は
がれが認められた試料Ｉを除いては、ドライエツチング
により電極を形成して、第１図に示すようなMOS素子を
形成することができた。測定したフラツトバンド電圧、
SiO2膜３の絶縁耐圧等の特性に問題はなかつた。As shown in FIG. 2, when the CVD method is used and the interface layer is only WO 3 , the refractory metal film (gate electrode 1) and SiO 2 are formed.
2 Adhesion to the film 3 was poor, but the interface layer was 10% SiO 2
Sample II containing WO 3 containing was obtained good adhesion by heating at about 1000 ° C. Sputter method Sample III obtained Te cowpea in, IV, as shown in FIG. 2, adhesive or without SiO 2 in WO 3 is had and good, sample IV containing SiO 2 in the WO 3 The adhesiveness of the sample was better than that of the sample III. Eventually, except for the sample I in which peeling was observed, the electrodes were formed by dry etching, and the MOS element as shown in FIG. 1 could be formed. The measured flat band voltage,
There was no problem in the characteristics of the SiO 2 film 3 such as withstand voltage.
界面層２へのSiO2添加の効果は、その量が１％以上で認
められた。しかし、50％以上にすると、絶縁耐圧の低下
が認められる場合があつた。なお、第２図に示した例で
は界面層に添加するSi酸化物はSiO2を用いたが、これは
SiO2でなくてもよく、SiOｘとして、ｘ１であれば接
着性向上の効果が認められ、下層のSiO2膜３が劣化する
ことはなかつた。また、界面層２の厚さとしては、単分
子層以上、50nm以下の厚さで接着性向上の効果が認めら
れた。さらに、界面層２のＷ酸化物の組成もWO3に限定
されず、WOｙのｙ＝２〜３の範囲で前記効果が認められ
た。Effect of SiO 2 added to the interfacial layer 2, the amount was observed in 1% or more. However, if it is 50% or more, a decrease in dielectric strength may be observed. In the example shown in FIG. 2 , SiO 2 was used as the Si oxide added to the interface layer.
It does not have to be SiO 2 , and if x 1 is SiO x , the effect of improving the adhesiveness is recognized, and the lower SiO 2 film 3 is not deteriorated. Further, as the thickness of the interface layer 2, the effect of improving the adhesiveness was recognized when the thickness was not less than the monomolecular layer and not more than 50 nm. Further, the composition of the W oxide of the interface layer 2 is not limited to WO 3 , and the above effects were observed in the range of y = 2 to 3 of WO y .
以上は高融点金属としてＷを用いた場合について説明し
たが、高融点金属としてMo（モリブデン）を用い、界面
層にMoOｙ＋SiOｘを用いた場合にも同様の効果が得られ
た。この場合、 SiOｘの代わりにTiOｘを用いても効果を生じ得るが、Ti
O2の生成自由エネルギーが SiO2のそれより負で大きい値をとることから、ｘ２に
しないと、下層のSiO2膜の変質が認められた。なお、Ｃ
（炭素）を含む化合物をWOｙやMoOｙに添加しても、接
着性向上の効果が認められた。Although the case where W is used as the refractory metal has been described above, the same effect is obtained when Mo (molybdenum) is used as the refractory metal and MoO y + SiO x is used for the interface layer. In this case, the effect can be produced by using TiO x instead of SiO x.
Free energy of the O 2 from taking a large value in the negative than that of SiO 2, unless the x2, alteration of the underlying SiO 2 film was observed. Note that C
Even if a compound containing (carbon) was added to WO y or MoO y , the effect of improving the adhesiveness was recognized.
本発明によれば、高融点金属で形成される電極・配線膜
と下層のSiO2膜との間に界面層を介在させることで、下
層のSiO2膜の変質を防止しながら、電極・配線膜とSiO2
膜との接着性の良好なMOS型半導体装置とすることがで
き、SiO2膜が薄い、非常に多くのMOS素子からなる、超
高集積回路の歩留りの向上と高信頼化に効果がある。ま
た、将来、電極・配線の形成に用いる蒸着装置が改良さ
れて装置内雰囲気の酸化性不純物が減少すると共に、電
極・配線の金属は純粋になり、下層のSiO2膜が不安定に
なる可能性は大きくなるので、本発明の有用性は増す。According to the present invention, by interposing an interface layer between the electrode / wiring film formed of a refractory metal and the lower SiO 2 film, the electrode / wiring can be prevented while preventing deterioration of the lower SiO 2 film. Membrane and SiO 2
A MOS type semiconductor device having good adhesiveness to a film can be provided, and it is effective in improving the yield and increasing the reliability of an ultra-high-integrated circuit having a large number of MOS elements with a thin SiO 2 film. Also, in the future, the vapor deposition equipment used to form electrodes and wiring will be improved to reduce oxidizing impurities in the atmosphere inside the equipment, and the metal of the electrodes and wiring will become pure, making the underlying SiO 2 film unstable. The usefulness of the present invention is increased because the property is increased.
【図面の簡単な説明】 第１図は本発明の実施例説明用の断面図、第２図は実施
例の４種類の試料Ｉ〜IVの仕様の特性比較を示す図であ
る。 １……ゲート電極（高融点金属膜）、２……界面層、３
……SiO2膜、４……Si単結晶基板。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view for explaining an embodiment of the present invention, and FIG. 2 is a diagram showing a characteristic comparison of specifications of four kinds of samples I to IV of the embodiment. 1 ... Gate electrode (refractory metal film), 2 ... Interface layer, 3
…… SiO 2 film, 4 …… Si single crystal substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山本 直樹 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭57−159042（ＪＰ，Ａ) 特開 昭59−132163（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoki Yamamoto 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) References JP 57-159042 (JP, A) JP 59 -132163 (JP, A)
Claims (5)
に積層して形成された絶縁膜、生成自由エネルギの絶対
値が二酸化シリコンの生成自由エネルギの絶対値以上で
ある酸化物を１〜50％含み、かつ、生成自由エネルギの
絶対値が二酸化シリコンの生成自由エネルギの絶対値よ
り小さい酸化物膜および所定の形状を有する高融点金属
膜を具備し、上記絶縁膜は、上記酸化物膜を介して上記
高融点金属膜に接することによつて安定性の低下が防止
される膜であることを特徴とする半導体装置。1. A semiconductor substrate, an insulating film laminated on the main surface of the semiconductor substrate, and an oxide having an absolute value of free energy of formation equal to or greater than an absolute value of free energy of formation of silicon dioxide. An oxide film containing 50% of the absolute value of free energy of formation is smaller than the absolute value of free energy of formation of silicon dioxide, and a refractory metal film having a predetermined shape, wherein the insulating film is the oxide film. A semiconductor device, which is a film in which deterioration of stability is prevented by being in contact with the refractory metal film through the film.
る特許請求の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein the insulating film is a SiO 2 film.
下であることを特徴とする特許請求の範囲第１項若しく
は第２項記載の半導体装置。3. The semiconductor device according to claim 1 or 2, wherein the oxide film has a film thickness of not less than a monomolecular layer and not more than 50 nm.
はモリブデン膜であることを特徴とする特許請求の範囲
第１項から第３項のいずれか一に記載の半導体装置。4. The semiconductor device according to any one of claims 1 to 3, wherein the refractory metal film is a tungsten film or a molybdenum film.
１）若しくはTiOｘ（ただし、ｘ≧２）を含むWOｙ（た
だし、２≦ｙ≦３）若しくはMoOｙ（ただし、２≦ｙ≦
３）の膜であることを特許請求の範囲第１項から第４項
のいずれか一に記載の半導体装置。5. The oxide film is formed of SiO x (where x ≧
1) or WO y containing TiO x (where x ≧ 2) (where 2 ≦ y ≦ 3) or MoO y (where 2 ≦ y ≦)
The semiconductor device according to any one of claims 1 to 4, which is the film of 3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59270885A JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59270885A JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61150236A JPS61150236A (en) | 1986-07-08 |
| JPH0671076B2 true JPH0671076B2 (en) | 1994-09-07 |
Family
ID=17492317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59270885A Expired - Lifetime JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671076B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330468A (en) | 1998-05-20 | 1999-11-30 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
| KR100650467B1 (en) | 2001-03-12 | 2006-11-28 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor integrated circuit device and process for producing the same |
| JP2005101141A (en) | 2003-09-24 | 2005-04-14 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57159042A (en) * | 1981-03-26 | 1982-10-01 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
-
1984
- 1984-12-24 JP JP59270885A patent/JPH0671076B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61150236A (en) | 1986-07-08 |
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