JPS6478362A - One connection preparation of several data processors for central clock control multi-line system - Google Patents

One connection preparation of several data processors for central clock control multi-line system

Info

Publication number
JPS6478362A
JPS6478362A JP63209310A JP20931088A JPS6478362A JP S6478362 A JPS6478362 A JP S6478362A JP 63209310 A JP63209310 A JP 63209310A JP 20931088 A JP20931088 A JP 20931088A JP S6478362 A JPS6478362 A JP S6478362A
Authority
JP
Japan
Prior art keywords
time
transferred
information value
value signal
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63209310A
Other languages
English (en)
Other versions
JPH0472262B2 (ja
Inventor
Aizenatsuku Yooahimu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wincor Nixdorf International GmbH
Nixdorf Computer AG
Original Assignee
Wincor Nixdorf International GmbH
Nixdorf Computer AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wincor Nixdorf International GmbH, Nixdorf Computer AG filed Critical Wincor Nixdorf International GmbH
Publication of JPS6478362A publication Critical patent/JPS6478362A/ja
Publication of JPH0472262B2 publication Critical patent/JPH0472262B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
JP63209310A 1982-09-27 1988-08-23 One connection preparation of several data processors for central clock control multi-line system Granted JPS6478362A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3235739A DE3235739C2 (de) 1982-09-27 1982-09-27 Verfahren zur Vorbereitung der Anschaltung einer von mehreren datenverarbeitenden Einrichtungen an eine zentral taktgesteuerte Mehrfach-Leitungsanordnung

Publications (2)

Publication Number Publication Date
JPS6478362A true JPS6478362A (en) 1989-03-23
JPH0472262B2 JPH0472262B2 (ja) 1992-11-17

Family

ID=6174275

Family Applications (2)

Application Number Title Priority Date Filing Date
JP58176553A Pending JPS5977566A (ja) 1982-09-27 1983-09-26 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法
JP63209310A Granted JPS6478362A (en) 1982-09-27 1988-08-23 One connection preparation of several data processors for central clock control multi-line system

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP58176553A Pending JPS5977566A (ja) 1982-09-27 1983-09-26 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法

Country Status (3)

Country Link
EP (1) EP0104638B1 (ja)
JP (2) JPS5977566A (ja)
DE (2) DE3235739C2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03266011A (ja) * 1990-03-16 1991-11-27 Hitachi Ltd フォールト・トレラント・システム及びその冗長系間の同期方法並びに多重化クロツク発振器

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3235739C2 (de) * 1982-09-27 1984-07-12 Nixdorf Computer Ag, 4790 Paderborn Verfahren zur Vorbereitung der Anschaltung einer von mehreren datenverarbeitenden Einrichtungen an eine zentral taktgesteuerte Mehrfach-Leitungsanordnung
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
BR9201605A (pt) * 1992-04-24 1993-10-26 Joao Marcelo Correa Sistema multiprocessado com comunicacoes em multicanais
DE19632832A1 (de) * 1996-08-14 1998-02-19 Siemens Nixdorf Inf Syst Verfahren zum Betreiben einer Mehrprozessor-Datenverarbeitungsanlage und nach diesem Verfahren arbeitenden Mehrprozessor-Datenverarbeitungsanlage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595131A (en) * 1979-01-10 1980-07-19 Hitachi Ltd Information bus controller
JPS5679353A (en) * 1979-11-30 1981-06-29 Hitachi Ltd Memory bus data transfer method of multiprocessor
JPS5977566A (ja) * 1982-09-27 1984-05-04 ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4290102A (en) * 1977-10-25 1981-09-15 Digital Equipment Corporation Data processing system with read operation splitting
NL8100930A (nl) * 1981-02-26 1982-09-16 Philips Nv Datacommunicatiesysteem.
FR2519165B1 (fr) * 1981-12-30 1987-01-16 Finger Ulrich Procede d'echange de donnees entre des modules de traitement et une memoire commune dans un systeme de traitement de donnees et dispositif pour la mise en oeuvre de ce procede

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595131A (en) * 1979-01-10 1980-07-19 Hitachi Ltd Information bus controller
JPS5679353A (en) * 1979-11-30 1981-06-29 Hitachi Ltd Memory bus data transfer method of multiprocessor
JPS5977566A (ja) * 1982-09-27 1984-05-04 ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03266011A (ja) * 1990-03-16 1991-11-27 Hitachi Ltd フォールト・トレラント・システム及びその冗長系間の同期方法並びに多重化クロツク発振器

Also Published As

Publication number Publication date
EP0104638A3 (en) 1985-05-08
EP0104638B1 (de) 1987-06-10
DE3235739A1 (de) 1984-03-29
JPS5977566A (ja) 1984-05-04
EP0104638A2 (de) 1984-04-04
JPH0472262B2 (ja) 1992-11-17
DE3372027D1 (en) 1987-07-16
DE3235739C2 (de) 1984-07-12

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