BR9201605A - Sistema multiprocessado com comunicacoes em multicanais - Google Patents

Sistema multiprocessado com comunicacoes em multicanais

Info

Publication number
BR9201605A
BR9201605A BR9201605A BR9201605A BR9201605A BR 9201605 A BR9201605 A BR 9201605A BR 9201605 A BR9201605 A BR 9201605A BR 9201605 A BR9201605 A BR 9201605A BR 9201605 A BR9201605 A BR 9201605A
Authority
BR
Brazil
Prior art keywords
multiprocessed
channel communications
communications
channel
multiprocessed system
Prior art date
Application number
BR9201605A
Other languages
English (en)
Inventor
Joao Marcelo Correa
Ricardo Broering Philippi May
Original Assignee
Joao Marcelo Correa
Ricardo Broering Philippi May
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Joao Marcelo Correa, Ricardo Broering Philippi May filed Critical Joao Marcelo Correa
Priority to BR9201605A priority Critical patent/BR9201605A/pt
Priority to PCT/BR1993/000015 priority patent/WO1993022727A1/en
Publication of BR9201605A publication Critical patent/BR9201605A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
BR9201605A 1992-04-24 1992-04-24 Sistema multiprocessado com comunicacoes em multicanais BR9201605A (pt)

Priority Applications (2)

Application Number Priority Date Filing Date Title
BR9201605A BR9201605A (pt) 1992-04-24 1992-04-24 Sistema multiprocessado com comunicacoes em multicanais
PCT/BR1993/000015 WO1993022727A1 (en) 1992-04-24 1993-04-23 Multiprocessing system with multiple-channel communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BR9201605A BR9201605A (pt) 1992-04-24 1992-04-24 Sistema multiprocessado com comunicacoes em multicanais

Publications (1)

Publication Number Publication Date
BR9201605A true BR9201605A (pt) 1993-10-26

Family

ID=4054139

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9201605A BR9201605A (pt) 1992-04-24 1992-04-24 Sistema multiprocessado com comunicacoes em multicanais

Country Status (2)

Country Link
BR (1) BR9201605A (pt)
WO (1) WO1993022727A1 (pt)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060535A3 (en) * 1981-03-12 1985-03-06 Recognition Equipment Incorporated Multiprocessor network
US4494192A (en) * 1982-07-21 1985-01-15 Sperry Corporation High speed bus architecture
DE3235739C2 (de) * 1982-09-27 1984-07-12 Nixdorf Computer Ag, 4790 Paderborn Verfahren zur Vorbereitung der Anschaltung einer von mehreren datenverarbeitenden Einrichtungen an eine zentral taktgesteuerte Mehrfach-Leitungsanordnung
EP0444711A3 (en) * 1990-03-02 1994-07-20 Fujitsu Ltd Bus control system in a multi-processor system

Also Published As

Publication number Publication date
WO1993022727A1 (en) 1993-11-11

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Legal Events

Date Code Title Description
FD5 Application fees: dismissal - article 86 of industrial property law