JPS645341B2 - - Google Patents

Info

Publication number
JPS645341B2
JPS645341B2 JP2148583A JP2148583A JPS645341B2 JP S645341 B2 JPS645341 B2 JP S645341B2 JP 2148583 A JP2148583 A JP 2148583A JP 2148583 A JP2148583 A JP 2148583A JP S645341 B2 JPS645341 B2 JP S645341B2
Authority
JP
Japan
Prior art keywords
memory
processor
parent
address
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2148583A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59148966A (ja
Inventor
Tetsuo Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2148583A priority Critical patent/JPS59148966A/ja
Publication of JPS59148966A publication Critical patent/JPS59148966A/ja
Publication of JPS645341B2 publication Critical patent/JPS645341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP2148583A 1983-02-14 1983-02-14 データ処理システム Granted JPS59148966A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2148583A JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2148583A JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Publications (2)

Publication Number Publication Date
JPS59148966A JPS59148966A (ja) 1984-08-25
JPS645341B2 true JPS645341B2 (es) 1989-01-30

Family

ID=12056273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2148583A Granted JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Country Status (1)

Country Link
JP (1) JPS59148966A (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259345A (ja) * 1985-05-13 1986-11-17 Panafacom Ltd 障害監視回路制御方式
JPS62127963A (ja) * 1985-11-29 1987-06-10 Fujitsu Ltd マルチプロセサシステム
JPS62174843A (ja) * 1986-01-29 1987-07-31 Hitachi Ltd メモリ優先切替方式
JP2610971B2 (ja) * 1988-11-29 1997-05-14 日本電気株式会社 中央処理装置間ダイレクトメモリアクセス方式
JPH05282198A (ja) * 1991-03-12 1993-10-29 Oki Electric Ind Co Ltd Dma転送方式

Also Published As

Publication number Publication date
JPS59148966A (ja) 1984-08-25

Similar Documents

Publication Publication Date Title
JPS60157646A (ja) メモリバンク切換装置
JPS645341B2 (es)
JPS60189561A (ja) メモリアクセス制御方式
JPH04288643A (ja) マルチプロセッサシステムのメモリマッピング方式
JPS6324348A (ja) メモリ共有方式
JP2581484B2 (ja) データ処理システム
JPS59128619A (ja) マイクロコンピユ−タ装置
JPS60245060A (ja) マイクロコンピユ−タ装置
JPS5821734B2 (ja) ダイレクトメモリアクセス制御方式
JPH0417466B2 (es)
JP3049710B2 (ja) 不揮発性半導体記憶装置
JPS62174843A (ja) メモリ優先切替方式
JPS6242308B2 (es)
JPH03191487A (ja) シングルチップマイクロコンピュータ
JPH01204118A (ja) 情報処理装置
JP2001155006A (ja) バス制御回路及び該バス制御回路を用いたマイコンシステム
JPS5921062B2 (ja) メモリ競合制御方式
JPS6040115B2 (ja) バブルメモリのバンクスイツチ方式
JPS63204342A (ja) メモリ装置
JPS62174844A (ja) メモリ優先切替方式
JP2003271573A (ja) マルチプロセッサ、マルチプロセッサコア及びその制御方法
JPH02257241A (ja) メモリアクセス競合改善方式
JPH01241643A (ja) インタフェース装置
JPS59208662A (ja) リ−ドオンリ−メモリのアドレス数を拡張する回路
JPS60252980A (ja) デユアルポ−トメモリ構成方式