JPS59148966A - データ処理システム - Google Patents

データ処理システム

Info

Publication number
JPS59148966A
JPS59148966A JP2148583A JP2148583A JPS59148966A JP S59148966 A JPS59148966 A JP S59148966A JP 2148583 A JP2148583 A JP 2148583A JP 2148583 A JP2148583 A JP 2148583A JP S59148966 A JPS59148966 A JP S59148966A
Authority
JP
Japan
Prior art keywords
memory
memories
priority
processor
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2148583A
Other languages
English (en)
Japanese (ja)
Other versions
JPS645341B2 (es
Inventor
Tetsuo Goto
哲雄 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2148583A priority Critical patent/JPS59148966A/ja
Publication of JPS59148966A publication Critical patent/JPS59148966A/ja
Publication of JPS645341B2 publication Critical patent/JPS645341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP2148583A 1983-02-14 1983-02-14 データ処理システム Granted JPS59148966A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2148583A JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2148583A JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Publications (2)

Publication Number Publication Date
JPS59148966A true JPS59148966A (ja) 1984-08-25
JPS645341B2 JPS645341B2 (es) 1989-01-30

Family

ID=12056273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2148583A Granted JPS59148966A (ja) 1983-02-14 1983-02-14 データ処理システム

Country Status (1)

Country Link
JP (1) JPS59148966A (es)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259345A (ja) * 1985-05-13 1986-11-17 Panafacom Ltd 障害監視回路制御方式
JPS62127963A (ja) * 1985-11-29 1987-06-10 Fujitsu Ltd マルチプロセサシステム
JPS62174843A (ja) * 1986-01-29 1987-07-31 Hitachi Ltd メモリ優先切替方式
JPH02146667A (ja) * 1988-11-29 1990-06-05 Nec Corp 中央処理装置間ダイレクトメモリアクセス方式
JPH05282198A (ja) * 1991-03-12 1993-10-29 Oki Electric Ind Co Ltd Ｄｍａ転送方式

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
b¨m®MULTIBUSýÐc±lxbýÐ=1981 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259345A (ja) * 1985-05-13 1986-11-17 Panafacom Ltd 障害監視回路制御方式
JPS62127963A (ja) * 1985-11-29 1987-06-10 Fujitsu Ltd マルチプロセサシステム
JPS62174843A (ja) * 1986-01-29 1987-07-31 Hitachi Ltd メモリ優先切替方式
JPH02146667A (ja) * 1988-11-29 1990-06-05 Nec Corp 中央処理装置間ダイレクトメモリアクセス方式
JPH05282198A (ja) * 1991-03-12 1993-10-29 Oki Electric Ind Co Ltd Ｄｍａ転送方式

Also Published As

Publication number Publication date
JPS645341B2 (es) 1989-01-30

Similar Documents

Publication Publication Date Title
JPS59148966A (ja) データ処理システム
US5551007A (en) Method for controlling multiple common memories and multiple common memory system
JPS60173655A (ja) マルチプロセツサのメモリ方式
JP2618223B2 (ja) シングルチツプマイクロコンピユータ
JPH024936B2 (es)
JPS60144857A (ja) Ｃｐｕ周辺回路
JPH07334420A (ja) 拡張メモリ制御回路
JPS62276643A (ja) メモリ制御方式
JPS6324348A (ja) メモリ共有方式
JP3075213B2 (ja) メモリ制御回路
JPS6242308B2 (es)
JP3006487B2 (ja) エミュレーション装置
JPS60134956A (ja) 情報処理システム
JPS6136861A (ja) 記憶装置
JPS62174843A (ja) メモリ優先切替方式
JPS63253446A (ja) メモリ優先切替方式
JPS62164153A (ja) アドレス形式を選択できる半導体集積回路装置
JP2003271573A (ja) マルチプロセッサ、マルチプロセッサコア及びその制御方法
JPH02257241A (ja) メモリアクセス競合改善方式
JPH04278662A (ja) マルチプロセッサシステム
JPH08235054A (ja) 共有メモリ
JPS6119059B2 (es)
JPS60252980A (ja) デユアルポ−トメモリ構成方式
JPS61237158A (ja) 共有メモリ装置
JPS60245060A (ja) マイクロコンピユ−タ装置