JPS634951B2 - - Google Patents

Info

Publication number
JPS634951B2
JPS634951B2 JP57112052A JP11205282A JPS634951B2 JP S634951 B2 JPS634951 B2 JP S634951B2 JP 57112052 A JP57112052 A JP 57112052A JP 11205282 A JP11205282 A JP 11205282A JP S634951 B2 JPS634951 B2 JP S634951B2
Authority
JP
Japan
Prior art keywords
leads
semiconductor element
semiconductor
shaped conductor
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57112052A
Other languages
English (en)
Japanese (ja)
Other versions
JPS593960A (ja
Inventor
Kyoshi Usui
Hiroshi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57112052A priority Critical patent/JPS593960A/ja
Publication of JPS593960A publication Critical patent/JPS593960A/ja
Publication of JPS634951B2 publication Critical patent/JPS634951B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP57112052A 1982-06-29 1982-06-29 半導体装置 Granted JPS593960A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57112052A JPS593960A (ja) 1982-06-29 1982-06-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57112052A JPS593960A (ja) 1982-06-29 1982-06-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS593960A JPS593960A (ja) 1984-01-10
JPS634951B2 true JPS634951B2 (enFirst) 1988-02-01

Family

ID=14576816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57112052A Granted JPS593960A (ja) 1982-06-29 1982-06-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS593960A (enFirst)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171152A (ja) * 1983-03-17 1984-09-27 Nec Corp 半導体装置
JPH061801B2 (ja) * 1984-12-24 1994-01-05 株式会社日立製作所 リ−ドフレ−ム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011462B2 (ja) * 1977-01-31 1985-03-26 日本電気株式会社 半導体装置
JPS5429973A (en) * 1977-08-10 1979-03-06 Hitachi Ltd Lead frame for semiconductor device

Also Published As

Publication number Publication date
JPS593960A (ja) 1984-01-10

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