JPS6338129B2 - - Google Patents

Info

Publication number
JPS6338129B2
JPS6338129B2 JP56171189A JP17118981A JPS6338129B2 JP S6338129 B2 JPS6338129 B2 JP S6338129B2 JP 56171189 A JP56171189 A JP 56171189A JP 17118981 A JP17118981 A JP 17118981A JP S6338129 B2 JPS6338129 B2 JP S6338129B2
Authority
JP
Japan
Prior art keywords
timing
phase
phase shift
signal
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56171189A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5871747A (ja
Inventor
Noboru Sonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56171189A priority Critical patent/JPS5871747A/ja
Publication of JPS5871747A publication Critical patent/JPS5871747A/ja
Publication of JPS6338129B2 publication Critical patent/JPS6338129B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56171189A 1981-10-26 1981-10-26 タイミング位相同期方式 Granted JPS5871747A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56171189A JPS5871747A (ja) 1981-10-26 1981-10-26 タイミング位相同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56171189A JPS5871747A (ja) 1981-10-26 1981-10-26 タイミング位相同期方式

Publications (2)

Publication Number Publication Date
JPS5871747A JPS5871747A (ja) 1983-04-28
JPS6338129B2 true JPS6338129B2 (cg-RX-API-DMAC10.html) 1988-07-28

Family

ID=15918649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56171189A Granted JPS5871747A (ja) 1981-10-26 1981-10-26 タイミング位相同期方式

Country Status (1)

Country Link
JP (1) JPS5871747A (cg-RX-API-DMAC10.html)

Also Published As

Publication number Publication date
JPS5871747A (ja) 1983-04-28

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