JPS63288351A - メモリ・ブロックの書き込み、読み出し回路 - Google Patents

メモリ・ブロックの書き込み、読み出し回路

Info

Publication number
JPS63288351A
JPS63288351A JP12241087A JP12241087A JPS63288351A JP S63288351 A JPS63288351 A JP S63288351A JP 12241087 A JP12241087 A JP 12241087A JP 12241087 A JP12241087 A JP 12241087A JP S63288351 A JPS63288351 A JP S63288351A
Authority
JP
Japan
Prior art keywords
block
memory
address
signal
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12241087A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0562787B2 (enrdf_load_html_response
Inventor
Koichi Oya
孝一 大矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asia Electronics Co
Original Assignee
Asia Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asia Electronics Co filed Critical Asia Electronics Co
Priority to JP12241087A priority Critical patent/JPS63288351A/ja
Publication of JPS63288351A publication Critical patent/JPS63288351A/ja
Publication of JPH0562787B2 publication Critical patent/JPH0562787B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
JP12241087A 1987-05-21 1987-05-21 メモリ・ブロックの書き込み、読み出し回路 Granted JPS63288351A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12241087A JPS63288351A (ja) 1987-05-21 1987-05-21 メモリ・ブロックの書き込み、読み出し回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12241087A JPS63288351A (ja) 1987-05-21 1987-05-21 メモリ・ブロックの書き込み、読み出し回路

Publications (2)

Publication Number Publication Date
JPS63288351A true JPS63288351A (ja) 1988-11-25
JPH0562787B2 JPH0562787B2 (enrdf_load_html_response) 1993-09-09

Family

ID=14835116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12241087A Granted JPS63288351A (ja) 1987-05-21 1987-05-21 メモリ・ブロックの書き込み、読み出し回路

Country Status (1)

Country Link
JP (1) JPS63288351A (enrdf_load_html_response)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496796B1 (ko) * 1997-12-29 2005-09-15 삼성전자주식회사 반도체메모리장치의어드레스카운팅제어회로

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0771666A (ja) * 1993-08-31 1995-03-17 Nagase Chuko Kk フランジ形管継手

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58112124A (ja) * 1981-12-25 1983-07-04 Fujitsu Ltd Ｄｍａ制御方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58112124A (ja) * 1981-12-25 1983-07-04 Fujitsu Ltd Ｄｍａ制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496796B1 (ko) * 1997-12-29 2005-09-15 삼성전자주식회사 반도체메모리장치의어드레스카운팅제어회로

Also Published As

Publication number Publication date
JPH0562787B2 (enrdf_load_html_response) 1993-09-09

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