JPS63213936A - 混成集積回路装置の製造方法 - Google Patents

混成集積回路装置の製造方法

Info

Publication number
JPS63213936A
JPS63213936A JP62048020A JP4802087A JPS63213936A JP S63213936 A JPS63213936 A JP S63213936A JP 62048020 A JP62048020 A JP 62048020A JP 4802087 A JP4802087 A JP 4802087A JP S63213936 A JPS63213936 A JP S63213936A
Authority
JP
Japan
Prior art keywords
solder
holes
circuit board
bonded
solder paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62048020A
Other languages
English (en)
Inventor
Katsuaki Yanagisawa
柳沢　克明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62048020A priority Critical patent/JPS63213936A/ja
Publication of JPS63213936A publication Critical patent/JPS63213936A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 不発明は混成集積回路装置の製造方法に係ｐ１特に両面
スルホール印刷基板の両面に半導体ペレットを含む電子
部品等を搭載し定混成果績回路の製造方法に関する。
〔便米の技術〕
従来のこの種の構成の混成集積回路装置の製造方法は、
第２図に示すように、アルミナセラミック基板１からな
る両面スルホール印刷回路基板の表主面の半導体ペレッ
ト６のグイボンディング用ランド２及びチップコンデン
サ７からなる電子部品搭載ランド３のみに、印刷法にて
ハンダペーストを供給し、半導体ペレット６及び電子部
品をリフロー法によりハンダ接合した後、半導体ペレッ
ト６をＡｕワイヤ１０にてワイヤボンディングし、回路
接続する。その後、シリコン樹脂８．ｃて、ワイヤ保護
のため、半導体ペレット６を覆い、しかる後前記印刷回
路基板の裏主面に、チップコンデンサ９からなる電子部
品等を表面と同様なハンダペースト印刷方式で接合する
といｆ）製造方法が一般的であった。
〔発明が解決しようとする問題点〕
前述した従来の製造方法では、シリコン樹脂８で半導体
ペレット６を覆う際、周辺にスルホール５があると、こ
のスルホール５内にシリコン樹脂８が入り込み、まわ）
込み部分１１を形成し、長面の部品搭載ランド３に、樹
脂８がかかってしまい、この状態で長面に電子部品をハ
ンダ等で接合する場合、シリコン樹脂８が防げとな９、
良好なハンダ接合かで＠ないという欠点かめ９１１ざ顕
性が低下するという問題があった。
不発明の目的は、前記問題が解決され、両主面に艮好な
ハンダ接合がでさるよう１てＬ７た混成集積回路装置の
製造方法に提供することにある。
〔問題点を解決するだめの手段〕
本発明の構成は、表主面と裏王面とが、スルホールで電
気的に接続された両面印刷回路基板上に、半導体ペレッ
トを含む電子部品をノ・ンダ接合する混成集積回路装置
の製造方法において、前記４子部品の搭載ランドに、ハ
ンダペーストを塗布する際に、このハンダペーストにて
、前記スルホールを塞ぐ工程を含むことを特徴とする。
〔実施例〕
次に本発明について図面を参照して詳細に説明する。
第１図（げ本発明の一実施例の断面図でろる。まず、第
１図（ａ）に示すように、アルミナ基板１上に原膜抵抗
及び厚膜導体より形成された両面スルホール印刷回路基
板の片面の半導体ダイボンディング用ランド２及び電子
部品搭載ランド３上に、印刷法にて、それぞれハンダペ
ースト４を供給する。
この際、同時にスルホール５にもハンダペースト４を供
給し、穴を塞ぐ。
しかる後、第１図（ｂｌに示すように、半導体ペレット
６及びチップコンデンサ７を搭載し、リフロー法にて、
ハンダ溶融接合する。しかる後、Ａｕワイヤ１０による
ワイヤボンディング法にて、半導体ペレット６を前記両
面印刷基板とを回路接伏する。次に、半導体ペレット６
をワイヤ保護のため、シリコン樹脂８にて覆う。この樹
脂８は、／・ンダペースト４で塞がれたスルホール５内
に入り込むことはない。次に、両面スルホール印刷回路
基板の反対側の面にも、前述と同様に、リフロ一方式に
より、チップコンデン＋ｊ９を）１ンダ溶融接合する。
〔発明の効果〕
以上説明したように、本発明によれば、従来の欠点であ
った半導体ペレットの保護用のシリコン樹脂がスルホー
ル部内に入り込み、裏面の部品搭載ランドにかかり、そ
のため長面に電子部品を搭載しハンダ接合する際、電子
部品のハンダ接合を妨げるということが全くなくな９、
より信頼性の高い混成集積回路装置を製造することがで
きるという効果が得られる。
【図面の簡単な説明】
第１図（ａ）　、第１図（ｂｌは本発明の実施例の混成
集積回路装（置の製造方法を工程順に示す断面図、第２
図は従来の製造方法を示す混成集積回路装置の断面図で
ある。 ｌ・・・・・・アルミナセラミック基板、２・・・・・
・半導体ペレットダイボンディング用ランド、３・・・
・・・電子部品搭載ランド、４・・・・・・−・ンダペ
ースト、５・・・・・・スルホール、６・・・・・・半
導体ペレット、７．９・・・・・・チップコンデンサ、
８・・・・シリコン樹脂、ｌＯ・・・・・・Ａｕワイヤ
。

Claims (1)

    【特許請求の範囲】
  1. 　表主面の裏主面とが、スルホールで電気的に接続され
    た両面印刷回路基板上に、半導体ペレットを含む電子部
    品をハンダ接合する混成集積回路装置の製造方法におい
    て、前記両面印刷回路基板上の、前記半導体ペレットを
    含む電子部品の搭載ランドに、ハンダペーストを塗布す
    る際に、このハンダペーストにて前記スルホールを塞ぐ
    工程を含むことを特徴とする混成集積回路装置の製造方
    法。
JP62048020A 1987-03-02 1987-03-02 混成集積回路装置の製造方法 Pending JPS63213936A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62048020A JPS63213936A (ja) 1987-03-02 1987-03-02 混成集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62048020A JPS63213936A (ja) 1987-03-02 1987-03-02 混成集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
JPS63213936A true JPS63213936A (ja) 1988-09-06

Family

ID=12791627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62048020A Pending JPS63213936A (ja) 1987-03-02 1987-03-02 混成集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS63213936A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03200393A (ja) * 1989-12-27 1991-09-02 Fujitsu Ltd 印刷配線板及びその製造方法
JPH0590955U (ja) * 1992-05-08 1993-12-10 株式会社精工舎 両面基板
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
US6798078B2 (en) * 2000-12-14 2004-09-28 Yamaha Hatsudoki Kabushiki Kaisha Power control device with semiconductor chips mounted on a substrate
WO2016047116A1 (ja) * 2014-09-22 2016-03-31 株式会社デンソー 電子装置、及び電子装置を備えた電子構造体

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03200393A (ja) * 1989-12-27 1991-09-02 Fujitsu Ltd 印刷配線板及びその製造方法
JPH0590955U (ja) * 1992-05-08 1993-12-10 株式会社精工舎 両面基板
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
US6798078B2 (en) * 2000-12-14 2004-09-28 Yamaha Hatsudoki Kabushiki Kaisha Power control device with semiconductor chips mounted on a substrate
WO2016047116A1 (ja) * 2014-09-22 2016-03-31 株式会社デンソー 電子装置、及び電子装置を備えた電子構造体
JP2016063202A (ja) * 2014-09-22 2016-04-25 株式会社デンソー 電子装置、及び電子装置を備えた電子構造体

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