JPS63173141A - Memory interface circuit - Google Patents

Abstract

PURPOSE:To realize an exact write operation, by inputting an incremental write (IW) address set token and an IW token from a data flow processor to an interface circuit. CONSTITUTION:When an incremental operation is performed, a data flag and an IW flag input the IW address write set tokens of 0 and 1 from the data porcessor 22 a memory interface circuit 10 respectively. In a circuit 10, an address which becomes the base of the IW is set at an address register 11 by setting a latch signal S118 to the address register 11 at 1. Next, the number of times of write of the IW token is inputted from the processor 22 to the circuit 10. The circuit 10, after completing the input/output operation of the token, latches the data on a register 13 by setting a latch signal S117 to a register 13 at 1, and writes the value of the register 11 on a memory 20 by setting a memory read/write signal S105 at 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory interface circuit, and particularly to a memory interface circuit that executes read/write operations from a data flow processor to a memory.

[Conventional technology]

Conventionally, there is μP07281 manufactured by NEC Corporation as a data flow processor. In addition, as a memory interface circuit in an arithmetic processing system using this data flow processor, μPD manufactured by NEC Corporation is used.
There is 9305.

To explain the memory access operation of this μPD9305, this circuit transfers data and performs arithmetic processing using a data flow method, and the unit of input/output data is called a token. A token is a data unit composed of a data portion having a data value, an identifier indicating the meaning of this token, a destination tag indicating the destination of the token, and the like.

For example, in the case of memory reading, a read token having a data portion which is a read address, an identifier indicating that the token is a read token having a read address, and a destination tag whose destination is the memory interface circuit is input to the memory interface circuit.

When a read token is input, the memory interface circuit outputs a read address of the token and a memory read signal to the memory, and instructs a read operation. The memory executes the read operation according to the instruction, and when the read operation is completed, it issues an access end signal to the memory interface circuit, the memory interface circuit generates and outputs a token containing the read data, and ends the memory read operation.

In addition, when writing the results processed by the data flow processor to memory, the data token has a data part that is write data, an identifier indicating that the data token has write data, and a destination tag that indicates the destination is the memory interface circuit. , a data portion which is a write address, an identifier indicating that the write token has a write address, and a write token having a destination tag whose destination is the memory interface circuit, are input to the memory interface circuit in this order.

When a data token is input, the memory interface circuit sets and holds the write data of the data section in the data register, and when the next write token is input, it first sets the write address of the data section of that write token in the address register. After setting, the write data read from the data register, the write address set in the address register, and a memory write signal are output to the memory to instruct a write operation. The memory executes the write operation according to the instruction, and when the write operation is completed, it issues an access end signal to the memory interface circuit, and the memory interface circuit thereby ends the memory write operation.

In this way, in the case of memory writing, the results processed by the data flow processor are written into the memory by the memory interface circuit.

[Problem that the invention seeks to solve]

By the way, in a device using such a memory interface circuit, when writing data resulting from processing by a data flow processor to consecutive addresses in the memory, the data flow processor performs arithmetic processing on the data in parallel. By generating an address for writing these data and synchronizing the data token with the data obtained by the operation through the waiting process and the write token with the write address, the data is alternately sent to the memory interface circuit. Then, the memory interface circuit performs a write operation.

However, in this case, (1) Address generation and waiting must be realized in software by a program on the data flow processor, which creates a burden on the software on the data flow processor. (2) Regarding writing one data Two tokens are output to the bus connecting the data flow processor and the memory interface circuit, which occupies the bus accordingly. (3) Since one write requires two tokens, it takes at least two pipeline clocks. be.

An object of the present invention is to realize high-speed memory write operations without increasing the software burden on the data flow processor side and the amount of token transfer on the bus between the data flow processor memory interface circuits as described above. The purpose of this invention is to provide a memory interface circuit.

Means for Solving Problem C] The present invention provides a memory interface circuit connected to a plurality of data flow processors and a memory, comprising: a token input unit for inputting a token, which is a unit of data, from the data flow processor; a data register for holding write data for the memory; an address register for holding a read/write address for the memory; an adder for adding a constant to the value held in the address register; and the token input section. and means for selecting one of the data input from the adder and the data input from the adder as an input to the address register, and a token output to the data flow processor using the data read from the memory. The present invention is characterized by comprising means for generating and outputting the token, and means for controlling memory read/write operations and register updating according to the signal from the token input section.

[Effect]

The memory interface circuit of the present invention has an identifier that indicates that this is an incremental write token that performs an incremental write operation using the data value of the data section, based on the decoding result of the token input from the data flow processor to the token input section. In this case, an incremental write operation is performed in which the data in the data section is written to the memory using the value set in the address register in advance as an address, and then the value of the address register is increased by 1. This is also the base for the incremental write operation. If the token has an identifier indicating that it is an incremental write address set token having an address in the data field, the value of the data field of the token is set in the address register.

In this way, after the write address is set in the address register by the incremental write address cent token, the data flow processor sends a single write data value to the memory interface circuit of the present invention once by the incremental write token with it. It is possible to write data to consecutive addresses simply by accessing the address.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The memory interface circuit 10 includes a memory access controller 15, an address register 11, and a data register 1.
3. Consists of a token input section 16, a token generation section 17, a token output section 18, a multiplexer 23, and an adder 24, which are connected to each other via signal lines 100 and 101.
Data flow processor 21.2 connected at 02
2, and is connected to the memory 20 via signal lines 105 to 108.

This memory interface circuit 10 performs data transfer and arithmetic processing using a data flow one-way system.

The token input unit 16 is an input unit into which a token, which is a unit of data, is input from the data flow processor 21, and the token output unit 18 is an input unit that receives a token, which is a unit of data, from the data flow processor 21.
This is an output unit that outputs the generated token to the data flow processor 22.

The token input section 16 and the token output section 17 are connected to the signal line 1.
14. This signal line 114 is a signal line for allowing the input token input to the token input section 16 to pass through as is. FIG. 2 shows an example of the data format of a token, which is a unit of input/output data. The token includes a data portion 86 having a data value, a destination tag 80 indicating the destination of the token,
It is composed of fields 81 to 84 having information such as an identifier indicating the meaning of this token. Specifically, in FIG. 2, 81 is an address/data flag, 82 is a read/write flag, 83 is an incremental write flag, and 84 is a data token generation information field.

When the input token is a read token for a memory read operation, the address/data flag 81 is "l" and the read/write flag 82 is "1", as described later, so that it is a read token with a read address. It is shown that something is true.

When it is a data token for a memory write operation, the address/data flag 81 is 0'' and the incremental write flag 83 is O'', indicating that it is a data token with write data. , address/data flag 81
is 11111, and the read/write flag 82 is 0'', indicating that it is a write token with a write address.

The data register 13 is a register for holding write data to the memory 20, and is connected to the token input section 16 by a signal line 113, and also to the memory 20 by a signal line 107, and is connected to the signal '! A signal 5107 from the data register 13 is applied to the memory 20 as write data via a107.

The address register 11 is a register for holding read/write addresses for the memory 20, and is connected to the memory 20 by a signal line 106. Output signal 5106 is applied to memory 20 as an address.

The adder 24 is an adder that adds a constant to the value held in the address register 11.
An output of "1" is supplied to one input, and "1" is input as the other input. The multiplexer 23 is means for selecting one of the data input from the token input section 16 and the data input from the adder 24 as input to the address register 11, and is configured to select one of the data input from the token input section 16 and the data input from the adder 24 as an input to the address register 11. It is connected to the adder 24 by a signal line 109, and the selected output is sent to the address register 11 via the signal wA112.
It is designed to be given to A control signal for selection is given from the memory access controller 15 via the signal line 110 as in the conventional manner.

The token generating unit 17 generates a token to be output to the data flow processor 22 using data read from the memory 20, and is used in the case of memory reading. The token generation unit 17 includes the token input unit 1
6 and signal line 103, and memory 20 and signal line 1
08, and data read from the memory 20 during memory read operation is transmitted through this signal line 108.
The output of the token generator 17 is sent to the token output unit 1 via a signal line 104.
8.

The memory access controller 15 has a token input unit 1
means for controlling memory read/write operations and register updating based on output signals supplied from 6;
Memory 20, address register 11, data register 1
3. Send a control signal to the multiplexer 23 and the token generator 17. Memory access controller 1
5 is the token input section 16 and the signal lines 121.63 to 6.
5, the memory 20 is connected to the signal line 105, the data register 13 is connected to the signal line 117, the address register 11 is connected to the signal line 118, and the multiplexer 2
3 through a signal line 110, and the token generator 17 through a signal line 111.

This memory access controller 15 and token input section 16 have a clock CL119. Clock CL120 (see FIG. 4) is applied, and clock CL120 is also applied to data flow processors 21,22.

FIG. 3 shows the configuration of the memory access controller 15. Referring to FIG. 3 showing the detailed configuration of the memory access controller 15, the memory access controller 15 receives the signal S63 from the token input section 16 as an input. , an address/data flag register 51 that latches this by a signal 5121 indicating input of a token.
and the signal S64 from the token input section 16 is input,
A read/write flag register 52 launches it in response to a signal 5121 indicating input of a token, and an incremental write flag register 53 receives a signal S65 from the token input section 16 as an input and latches it in response to a signal 5121 indicating input of a token. , their output signals 360.361. S62, clock CL 11
9. CL 120, inputs a signal 5121 indicating token input from the token input section, memory read/write operation selection signal 5IO5 to the memory 20, latch signal 5117 to the data register 13, address register 11
The gate array 50 outputs a latch signal 3118 to the multiplexer 23, a selection command signal 5IIO to the multiplexer 23, and a token generation command signal 5111 to the token generation section 17.

As mentioned above, the memory interface circuit 10 of FIG.
is connected to a plurality of data flow processors 21 and 22 connected in a ring, two in the illustrated example, and the memory 20, and is a token input for inputting a token, which is a unit of data, input from the data flow processor 21. Part 1
6, a data register 13 for holding write data to the memory 20, an address register 11 for holding a read/write address for the memory 20, and an adder 24 for adding a constant to the value held in the address register 11. A multiplexer 23 selects one of the data input from the token input unit 16 and the data input from the adder 24 as input to the address register 11, and the data read from the memory 20 is used to control the data flow. A token generation unit 17 that generates a token to be output to the processor 22, a token output unit 18 that outputs the token generated by the token generation unit 17 to the data flow processor 22, a memory 20, an address register 11, and a data flow processor 22. register 13,
The memory access controller 15 is connected to the multiplexer 23, the token generation section 17, and the token input section 16, and controls memory read/write operations and register updating according to signals from the token input section 16.

In FIG. 1, a token input from a data flow processor 21 to a memory interface circuit 10 is decoded by a token input section 16.

The token input section 16 receives the clock C via the signal line 100.
If the value of the field 80 of the destination tag of the token input in synchronization with L119 is not a value indicating this memory interface circuit 10 set in advance in the token input section 16, this person is passed through the signal line 114 as a token. Output to. This passing token is directly output from the signal line 101 to the outside of the memory interface circuit 10 via the token output section 18.

On the other hand, if the value of the field 80 of the destination tag of the input card is a value indicating this memory interface circuit 10, the token input unit 16 inputs the address/data flag 81, read/write, etc. of the information of the token.
Write flag 82, incremental write flag 83
The information of each field of the signal line 63, 64, 6
5, the data section 86 is output to the signal line 113, the read data token generation information field 84 is output to the signal line 103, and the signal 5121 indicating token input is set to "1". In addition, the token input section 16 is connected to the CL clock 119.
The signal 5121 is kept at "1" for one period of "1", and then "
0'' and enters a state in which token input from the data flow processor 21 is possible.

In the memory access controller 15, the address/data flag 81. which is sent from the token input section 16 via the signal lines 63, 64, 65. Read/write flag 8
2. Information in each field of the incremental write flag 83 is read/read to the address/data flag register 5 when the input signal 5121 becomes “1”.
It is latched into the write flag register 52 and the incremental write flag register 53.

The above operations of the token input unit 16 and memory access controller 15 are referred to as "token input operations."

The gate array 50 is provided with a clock CL 119. as shown in FIG. CL 120 is being supplied, and after the token input/output operation described above, while the signal 5121 indicating token input is "1", the registers 51, 52, 53
Output S60. 361. Input/output operations are performed according to the following input/output correspondence table using S62 and the like as input.

In this table, 5121, S60, S61, S6 on the left
2, CL 119. CL 120 indicates an input signal in the memory access controller i5, and 5105 on the right
．． 5117.5118.5110 and 5111 indicate outputs when these inputs are given. Furthermore, the lines indicated by (1) are used when there is no input to the memory access controller 15, the lines indicated by (2) are used for read operations due to read token input, and the lines indicated by (3) are used for write token input. In the case of a write operation using normal 7 dressing, each line indicated by (4) is an operation for setting data to a data register by inputting a data token, and each line indicated by (5) is an incremental write operation by inputting an incremental write token. In the case of a write operation, each row indicated by (6) corresponds to the case of an incremental write address setting operation using an incremental write address set token.

Hereinafter, details of a memory access operation performed using a token whose destination indicated by a destination tag is a memory interface circuit will be described.

First, the read operation for the memory 20 will be explained.

When performing a memory read operation, the data flow processor 21 inputs to the memory interface circuit 10 a read token having a data portion as a read address and a destination tag with the memory interface circuit 10 as the destination. As mentioned above, in the read token, the address/data flag 81 is 1.
1'', the read/write flag 82 being "1" indicates that it is a read token having a read address.

When such a decoded token is input to the token input unit 16, the token input unit 16 and the memory access controller 15 perform the above-described token input waiting operation, and the output signals S60.
S61. 362 is confirmed.

The gate array 50 outputs a selection instruction signal 5110 to the multiplexer 23 via the signal line 110 to select the input from the signal line 113 and output it to the signal line 112, and also outputs a latch signal 5118 via the signal line 118. As a result, the input data value on the signal line 112 is latched into the address register 11.

Further, when the input read/write flag 82 outputted on the signal line 61 is "1'", the memory read/write operation selection signal 5105 becomes "0", and the memory 20 receives the output signal 8106 from the address register 11. A read operation is performed using the address 11!, and the data read from the memory 20 is signal 11! It is output to jiio8.

The gate array 50 instructs the token generation unit 17 via a signal 1111 to generate a token from the read data.
In accordance with this instruction, the token generation unit 17 generates read data 8108 and read data token generation information 51.
An output token is formed by combining the destination tag and identifier that the read data token included in 03 should have, and this output token is output to the data flow processor 22 via the signal line 104, the token output unit 18, and the signal line 101. . The above read operation is completed within one pipeline clock of the pipeline clock CL119, and the token input section 16 sets the signal S L21 to "0" in synchronization with the pipeline clock CL119, so that the memory interface circuit 10 performs the memory read operation. Finish the operation.

Next, a write operation to the memory 20 will be explained.

When performing a memory write operation, first, the data flow processor 21 sends data from the memory interface circuit 1 to the data flow processor 21.
0, a data portion that is write data and a data token having a destination tag whose destination is the memory interface circuit 10 are input. As mentioned above, in the data token, the address/data flag 81 is “O” and the incremental write flag 83 is “O”.
is "0", indicating that it is a data token with write data.

When a token is input, the above-mentioned token input waiting operation is performed, and the write data of the data section 86 of the input card is outputted to the signal vA113, and the gate array 50 outputs the latch signal 5117 to the data register 13. The memory interface circuit 10 completes the data cent operation within one pipeline cycle.

Next, the data flow processor 21 sends a write token to the memory interface circuit 10 that has a data section that is a write address, a destination tag with the memory interface circuit 10 as the destination, and also has an incremental write flag. Enter. As mentioned above, in the write token, the address/data flag 81 is “
1'', and the read/write flag 82 is 0'', indicating that it is a write token with a write address.

When a write token is input, the above-described token input waiting operation is performed, and in the case of a normal data write operation in which the gate array 50 does not perform an incremental write, the gate array 50 receives a signal S60. S61. S62 is 1″ each
, '0''110'', the address register 11 is latched by setting the latch signal 8118 for the address register 11 to “L”, and then the memory 2
0, the memory read/write operation selection signal 5105 is “
1", thereby making the signal S106 output from the address register 11 the write address, and the signal S106 output from the previously set data register 13.
Instructs a write operation using 07 as write data.

The memory 20 executes the write operation in accordance with this, thereby completing the memory write operation within one pipeline cycle.

On the other hand, when performing an incremental write operation, first, the memory interface circuit receives an incremental write address set token whose address/data flag 81 and incremental write flag 83 are "O" and "1", respectively, from the data flow processor. Input to IO. In the memory interface circuit 10, after the above-described token input operation, the address register 11 is
By setting the latch signal 5118 to "1", the base address in the incremental write in the data section of the token is set in the address register 11.

Next, the data flow processor inputs the same number of incremental write tokens as the number of consecutive memory writes to the memory interface circuit 10. In the incremental write token, the address/data flag 81, read/write flag register 52, and incremental write flag 83 are "1" and "0", respectively.
'1', and after the memory interface circuit 10 performs token input/output operations on this token, it sends the launch signal 5117 to the data register 13 as '1'.
By setting the memory read/write operation selection signal S105 to "1", the input data in the data section of the token is latched into the data register 13, and by setting the memory read/write operation selection signal S105 to "1", the value in the address register 11 is set as an address. Performs a write operation to memory.

Next, the selection command signal 5110 to the multiplexer 23 is set to "1", and the latch signal 31 to the address register 11 is set to "1".
By setting 1B to "1", the output of the adder 24 is latched into the address register 11. At this time, adder 24
Since the value of the current address register and "1" are input to , the address register 11 is newly set with the incremented write address in the current address register, and the next time an incremental write token is set. If it is input, writing will be performed to a memory address consecutive to the current one.

〔Effect of the invention〕

As explained above, according to the present invention, the memory interface circuit generates the write address in the case of a write operation to consecutive addresses in the memory, so it requires less software than the conventional case where this is realized by the program of the data flow processor. By making it possible to write data from the data flow processor to the memory interface circuit in one access using an incremental write token containing the data to be written, it is possible to reduce the burden on the memory interface circuit from the data flow processor during processing, which was previously required. Reduces bus occupancy due to two accesses to the circuit, plus one access per pipeline
It is possible to realize faster writing by performing multiple writes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of an input data format used to explain the present invention, and FIG. 3 is a detailed diagram of the memory access controller in FIG. 1. FIG. 4 is a diagram for explaining the operation of the memory access controller. 10...Memory interface circuit 11...
・Address register 13 ・Data register 15 ・Memory access controller 16 ・
... Token input section 17 ... Token generation section 18 ... Token output section 20 ... Memory 21.22 ... Data flow processor 23 ...
Multiplexer 24...Adder 50...Gate array 51...Address/data flag register 52
... Read/write flag register 53 ...
Incremental write flag registers 60-65, 100-114, 117-121...
・Signal line agent Yoshiyuki Iwasa, patent attorney Figure 4

Claims (1)

[Claims] (1) In a memory interface circuit connected to a plurality of data flow processors and a memory, a token input section for inputting a token, which is a unit of data, from the data flow processor, and data for holding data written to the memory. a register; an address register for holding read/write addresses for the memory; an adder for adding a constant to the value held in the address register; and data input from the token input section and input from the adder. means for selecting one of the data read as an input of the address register; means for generating and outputting a token to be output to the data flow processor using the data read from the memory; and the token input. 1. A memory interface circuit comprising: means for controlling memory read/write operations and register updating according to signals from a memory interface circuit.