JPH0275054A - Scan control method for multiprocessor systems - Google Patents

Abstract

PURPOSE:To attain the simultaneous scan-in process to all processors for each bit just with addition of a small hardware quantity by securing such a constitution where a service processor adds the mask information to the scan information and each processor performs a mask process to scan in a register. CONSTITUTION:A service processor 10 adds the mask information to the scan information to be put on a scan bus 14. At the same time, a register REG which holds the mask information and a circuit 30 which performs the scan-in actions for each bit based on the mask information. Thus it is possible to perform the simultaneous scan-in process to all processors 11, 12 and 13 although the processing time is kept at a level required for a single processor regardless of the number of processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scan control method, particularly for all processors in a multiprocessor system.

The present invention relates to a scan control method for a multiprocessor system suitable for performing simultaneous scan-in processing.

[Conventional technology]

A conventional scan control method in a multiprocessor system including a plurality of processors, a service processor, and a scan canvas interconnecting them will be explained with reference to FIG. In Figure 2, 1o is a service processor, 11,1
2.13 is a processor, and 14 is a scan canvas that interconnects these.

Now, the register R1Σ()] of the processor 11,...
.

When REGn is scanned by the service processor 1o, the register REG i, (i = 1.
...on) address on the scan canvas i4. It is set from the service processor 10 via the receiver 21.

When the access is a read, the contents of the ADR 23 are decoded by the decoder 24, and the decoded output is supplied to the clock control circuit 25, and the generated enable signal causes the data in the register REGi specified by the above address to be output. . This data is outputted via the multiplexer 28 by a multiplexer signal given from the decoder 24 to the multiplexer 28, set in the read data register RDG27 by the read clock C'LKR, and then sent to the service processor 10 via the driver 22 and scan canvas 14. sent to. Further, when the access is a write, data following the address is transferred from the service processor 10 to the scan canvas 14 and the receiver 21.
It is set in the write data register W D 26 in response to the write clock CLKW via the write clock CLKW. At this set completion time, the address of register ADR23 is changed to decoder 2.
3, and the decoded output is supplied to the tarlock control circuit 25 to generate an enable signal, and the output data of the register WD26 is set in the register RE G j specified by the signal. Processor 12.1
The scanning operation in step 3 is similar.

Regarding this, for example, Japanese Patent Application Laid-Open No. 62-92065
Details are given in the publication.

[Problem to be solved by the invention]

According to the conventional method described above, when scanning in the same data to the same register for all multiple processors, there is no problem in the case of scanning in register length units, but when scanning in specific bits of the register at the same time. cannot be processed. In order to scan data bit by bit for all processors, as shown in FIG.
Gi data is read and stored in the memory on the service processor 10 (step 111) - the stored data is subjected to bit processing (mask operation) (step 112), and the generated data is transferred to each processor. Operation of writing to the corresponding register REGi (step 113
) is required, and if the number of processors is m, in order to control the bits of register REGi of all processors,
The scanning operation is performed through the scan canvas 2 m times, and the processing time increases linearly by a factor of 1 for the number of devices and 2 times for the amount of processing.

An object of the present invention is to: In a multiprocessor system,
An object of the present invention is to provide a scan control method that enables simultaneous scan-in processing for all processors when scanning the same data from a service processor into the same register in a plurality of processors in bit correspondence.

[Means to solve the problem]

In order to achieve the above object, in the scan control method of the present invention, the service processor adds mask information to the scan information placed on the scan canvas, and each processor has a register that holds this mask information, and a register that holds this mask information. The feature is that a circuit is provided that performs scan-in bit by bit based on .

[For production]

When performing simultaneous scan-in from the service processor to all processors, the service processor sends a simultaneous scan-in command, address, write data, and mask data onto the scan canvas.

In response to this, each processor first reads the data from the register specified by the address, stores it in the read data register, and then generates bit-by-bit data using the write data, read data, and mask data. Furthermore, it generates parity for the data and writes it into the register specified by the address. In this way, even in the case of bit-by-bit scan-in, simultaneous scan-in processing is possible for all processors, and the processing time is not affected by the number of processors, but is the average processing time for one processor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of one embodiment of the invention.

In FIG. 1, 11 to 13 are processors constituting a multiprocessor system, 1.0 is a service processor, and service processor 10 and processors 11 to 1
3 is a scan canvas] 4. The service processor 10 controls the scan canvas 1.4.

The processor 11 includes a plurality of registers REGI.

REG2. . Write data (scan-in data) sent via the receiver 21.

A mask operation is performed in the mask circuit 30 using the mask data and the read data read above, and scan-in is executed. 23
is address register ADH.

The access address of this address register 23, which receives the access address from the service processor 10 via the scan canvas 14 and the receiver 21, is transferred to the decoder 24.
- sometimes registers REG1, REG2 . . . , one of REGn is set to be enabled for data cellar 1. Also, the multiplexer output of the decoder 24 is supplied to a multiplexer 28.

- sometimes registers REGI, REG2 . ..., RE
726 is a write data register WD which receives write data from the service processor 10, 27 is a mask data register MSK which receives mask data, and 29 is a read register which receives read data selected by the multiplexer 28. This is data register RD.

In addition, in FIG. 1, the scan error 1 to the processing section are omitted.

Below are the registers RE G1, R in the processor 11.
EG2. . . , REGn's scan-in operation will be described, but the processors 12 and 13 also perform similar operations at the same time.

In order to issue a bit-by-bit simultaneous scan-in command to all processors, the service processor 10 sends a simultaneous scan-in command, register address, write data, and mask data to the scan canvas 14 (step 101). The processors 11, 12, and 13 take in this information sent onto the scan canvas 14 and execute a register scan-in operation. Here, the operation of the processor 11 will be described.

The access address from the service processor 10 via the scan canvas 14 and the receiver 21 is set in the address register ADR23, and the address is sent to the decoder 2.
4, the decoded output is supplied to the clock control circuit 25, and in response to an enable signal from the clock control circuit 25, the data of the register REGi designated by the access address is output. This register RE
Gi data is sent from the decoder 24 to the multiplexer 28
The data is selected by the multiplexer 28 according to the multiplex signal applied to the multiplexer 28, and set in the read data register 29 by the read clock CLKR.

The service processor 10 receives mask data following the access address via the scan canvas 14 and receiver 21, and sets it in the mask data register MSK27 in response to the mask CL KM. Scanvas 14. The write data sent via the receiver 21 is sent to the write data register W in response to the write clock CLKW.
Set to D26.

After each data in the write data register WD26, mask data register MSK27, and read data register VD29 is determined, a mask operation is performed in the mask circuit 3o, and the mask operation is performed by an enable signal issued from the clock control circuit 25 to the corresponding register REGi. The value specified by the access address is set to REGi specified by the access address.

The mask circuit 30 assumes that the output data of the write data register WD26 is a, the output data of the mask data register MSK27 is 1), the output data of the read data register RD29 is C, and the output data of the mask circuit 30 is d. An arithmetic operation represented by a−b+b·C is performed.This can be easily realized by using, for example, an AND or OR circuit.

In this way, the mask data register MS is stored in the processor.
By providing K and further providing a bit-by-bit scan-in circuit corresponding to MSK, simultaneous scan-in can be performed for all processors at the pins 1- and 01.

〔Effect of the invention〕

As explained above, according to the present invention, with the addition of a small amount of hardware, it is possible to implement
- Simultaneous scan-in processing for all processors in a unit can be realized. As a result, the bit-by-bit scan-in processing time for all processors can be reduced to 5 times per processor regardless of the number of processors, and as the amount of processing increases, it can be done at a linear rate of 1. .

Also, generally the service processor is the processor number)
Since the processing speed is slow and the bus control has a specific procedure, the method of the present invention can perform scan-in processing in units of 1 pin for -1 processors at a higher speed than the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a scan control method according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional method. 10...Service processor, 11-13...Processor, 14...Scanvas, 21...
・Receiver, REG1~REGn...Register, 23...Access address register, 2
4... Decoder, 25... Clock control circuit,
26...Write data register, 27...Mask data register, 28...Multiplexer, 2
9... Read data register, 30... Mask circuit.

Claims (1)

[Claims] (1) In a multiprocessor system equipped with a plurality of processors, a service processor, and a bus that interconnects the plurality of processors and the service processor, the same data is scanned bitwise from the service processor to the same register in the plurality of processors. In the input method, the service processor adds mask information to scan information (scan address, scan-in data),
The data is sent to each processor via the above bus, and each processor reads the data in the register specified by the scan address, and masks this read data and the scan-in data from the service processor based on the mask information. A scan control method for a multiprocessor system characterized by processing and scanning into the corresponding register.