JPH01184566A - Data transfer control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a data transfer control method for transferring data between peripheral devices connected to a central processing unit. The purpose is to provide a method for performing high-speed transfer between peripheral devices using a transfer control unit, and in a system consisting of a central processing unit and peripheral devices connected to the central processing unit via a bus, A transfer control unit for direct data transfer is provided, and an address is set in the address space of the central processing unit to designate a data transfer source device and a data transfer destination device as a pair when the peripheral device transfers data. Data transfer control method.

[Industrial application field]

The present invention relates to a data transfer control method for transferring data between peripheral devices connected to a central processing unit.When processing images, a large amount of data is continuously transferred to an input device, e.g. , read from the scanner and store in image memory.

When reading large amounts of data from an input device like this,
Normally, the data is first read into the central processing unit and then transferred to the target device again, but since it is difficult to speed up the processing, there is a need for a transfer method that is suitable for such processing.

[Conventional technology]

FIG. 4 is a diagram illustrating a conventional system configuration, and is a diagram illustrating data transfer from one device to a target device via a central processing unit.

FIG. 4(a) is a configuration diagram, and FIG. 4(b) is an address space diagram.

When peripheral devices A and B are connected to the central processing unit 1 and an address, for example (OOOOH), is specified on the address bus 2 in the address space 11 of the central processing unit 1, the peripheral device A is specified by the decoder 3. Data is read into the temporary register 10 via the data bus 4.

Then, the peripheral device B is specified by specifying the address (OO02H), and data is transferred from the temporary register 10 to the peripheral device B. The central processing unit 1 controls the bus and the peripheral device A Data is fetched from the memory and read into the temporary register 10, and a pass sequence is generated and transferred to the peripheral device B.

That is, a pass sequence is generated every time data is transferred.

Alternatively, the peripheral device A or the peripheral device B is provided with means for directly generating the address of the other party, generating a path sequence, and transferring data.

[Problems to be Solved by the Invention] The former conventional method, that is, the method via the central processing unit, requires two bus cycles, one for writing and one for reading, and the data once read is stored in the central processing unit. A temporary register is required.

In order to use the latter method described above, that is, to perform direct transfer between devices without going through the central processing unit, one of the peripheral devices to be transferred is
MA (direct memory access) functionality is required, leading to increased hardware.

The present invention was created in view of these points, and provides a method in which the address space has an address that directs direct transfer between peripheral devices, and a transfer control unit performs high-speed transfer between peripheral devices. The purpose is to

[Means for solving problems]

In order to achieve the above object, a transfer control unit is provided to directly transfer data between peripheral devices, and the transfer control unit sets in an address space an address for a pair of a transfer source device and a transfer destination device to which data is transferred.

[For production]

The address space of the central processing unit has separate addresses for specifying normal access to each peripheral device, and transfer addresses that specify the peripheral device and the direction of transfer from one peripheral device to another. Set as an address.

Then, when those addresses are specified by the central processing unit, writing and reading are performed via the central processing unit as in the conventional access method, or the transfer control section Controls the direct transfer of data between peripheral devices without intervention.

〔Example〕

FIG. 1 is a diagram illustrating an embodiment of the data transfer control method of the present invention. − The same reference numerals indicate the same objects throughout the figures.

In FIG. 1, (a) is a block diagram, and (b) is an address space diagram.

As shown in Figure 3), the central processing unit 1
A has the address (OOOOOH) (H indicates 1' hexadecimal notation) the normal access address of the peripheral device A, (OO0
2H) is the normal access address of peripheral device B, (OO
The address for direct transfer from peripheral device A to peripheral device B is stored in [04H), and the address for direct transfer from peripheral device A to peripheral device B is stored in [0006H].

(000H) and (0002H) addresses are both written or read from the central processing unit 1 using conventional access methods.

(0004H) and (0006H) are direct transfer addresses, and the transfer control unit 5 transfers data between peripheral devices without the intervention of the central processing unit 1.

FIG. 2 is a diagram showing an example of the configuration of a decoder and a transfer control section, which are the main parts of the present invention.

When a 2-bit address is input to the decoder 3 via the address bus 2, it is decoded and an address select signal is output from one of the output terminals Y0 to Y3 to the transfer control section 5.

Address select signals output from the output terminals Y0 to Y3 are output from the Yo and Yl terminals of peripheral devices A and B, respectively.
This is a direct transfer select signal from the Yz and Y3 terminals to peripheral devices A-B and peripheral device B→A, respectively.

This select signal is normally used by the access timing control circuit 5.
1. Input to direct transfer timing control circuit 52.

The normal access timing control unit 51 outputs a latch signal (IA, terminal names of the selector in parentheses; the same applies hereinafter) of the peripheral bag WA, an output enable signal (2
A), the latch signal (3A) of the peripheral device B, and the output enable signal (4A) of the peripheral collection date are output to the selector 53.

On the other hand, from the direct transfer timing control unit 52, a latch signal for peripheral device A (IB), an enable signal for peripheral device A (2B), a latch signal for peripheral device B (3B), and an enable signal for peripheral device B (4B) are sent. is output.

Then, from the output terminal of the selector 53, the peripheral device A latch signal (IY), the peripheral device A enable signal (2Y
), a latch signal (3Y) for peripheral device B, and an output enable signal (4Y) for peripheral device B are output.

That is, depending on the address input to the decoder 3, signals for controlling the connection and output of the peripheral devices A and B are selected and output from the transfer control section 5.

The tick circuit 54 sends out a data acknowledge signal to notify the central processing unit 1 that data transfer from the selected address has been completed.

FIG. 3 shows another embodiment of the present invention, in which (a) is a block diagram and (bl is an address space diagram).

The example in FIG. 3 uses a scanner 6 and a printer 7 as peripheral devices.
are connected to each other, and the image data transfer bus is composed of a daisy chain bus 8.

T is a system having the configuration shown in FIG. 1, and peripheral devices A and B in FIG. 1 are input/output registers A and B of connected devices in the case of FIG. 3.

The data is transferred from the image memory 9 through the connection point with the daisy-chain bus 8, ie, the node 2, to the node 1 to which the register A is connected, and the register A receives the data.

Notifying the central processing unit 1 that register A holds data, the central processing unit 1 accesses [0004H], transfers it from register A to register B, and outputs it to the printer.

Transfer from the scanner 6 to the image memory 9 involves transferring data from the scanner 6 to register B, notifying the central processing unit ll that register B holds the data, and
Central processing unit 1 accesses (OOO6H) and transfers data from register B to register A.

Then, from register A to bus connection point node 1, node 2
The image data is stored in the image memory 9 via the .

〔Effect of the invention〕

As described above, according to the present invention, the transfer speed can be improved by adding a simple circuit compared to the conventional transfer between devices via a central processing unit.
It is extremely useful industrially.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the configuration of an embodiment of the data transfer control method of the present invention, FIG. 2 is a diagram illustrating an example configuration of a decoder and a transfer control section, and FIG. FIG. 4 is a diagram illustrating data transfer in a conventional system. In the figure, 1 is a central processing unit, 5 is a transfer control unit, A and B are peripheral devices (registers), and 11A is an address space. Floating Throat Ichiban Yu Example 6 Set Mei Riki ■ 4-IR familiarity = corner protrusion C ri to complete the creation No. 311
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Claims (1)

[Claims] In a system consisting of a central processing unit (1) and peripheral devices (A, B) connected to the central processing unit (1) via a bus, data is directly transferred between the peripheral devices (A, B). A control unit (5) is provided, and the peripheral devices (A,
B) A data transfer control method characterized in that an address is set that specifies a data transfer source device and a data transfer destination device as a pair when data is transferred.