JPS58203532A - Circuit for generating timing pulse - Google Patents

Abstract

PURPOSE:To generate pulse controlling the execution of instruction from a microcomputer, by providing FFs which are set by timing pulse requesting signals and reset by respective timing pulses and controlling a control circuit which controls the pulse generating order by the outputs of the FFs. CONSTITUTION:Timing generation requesting signals C12 C14 are inputted to plural set/reset type FFs 11-13, the FFs 11-13 are set up and outputs Q, Q' are outputted synchronously with a clock. The outputs Q, Q' from the FFs 11-13 are selected and applied to respective OR gates 14, 15 and AND gates 16-19. A timing generation order changing request signal C11 is applied to the OR gates 14, 15 and the FFs 11-13 are restet by the outputs of AND gates 16-18. The timing pulses are outputted in the order of M1, M2, M3, and M4. Consequently, the timing pulses effective for the execution of the instruction from the microcomputer are supplied to a machine cycle counter with a simple configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides timing pulse generation (gJ path), which is particularly effective for V syncycle generation circuits of microcomputers (hereinafter abbreviated as microcomputers), and which allows the generation order of timing pulses to be changed. This invention relates to a pulse generation circuit.

In general, the instructions used in microcomputers do not have a fixed word length, but include 1-byte instructions, 2-byte instructions, etc., and the execution of the instructions is completed after several machine cycles, which are determined by the data processing execution unit. Since the number of machine cycles is not uniform depending on each instruction, the information processing device proposed in No. It is known how to complete execution of an instruction by generating only a cycle signal. In these cases, the machine cycles are generated in the following order: operation code 7 etching cycle for instruction decoding, memory read cycle, arithmetic cycle, and memory write cycle. However, this NO level is not uniform depending on the instruction, and there are instructions that require a memory read cycle after an operation cycle, such as an instruction that determines a memory address based on the result of an address operation, such as in Intex addressing. Conventionally, the command of this fairy tale'fr:
In order to achieve this, I used the following methods for VC.

The first method is to provide a memory read cycle also after the calculation cycle, and the second r! However, the first method requires an extra memory write cycle generation circuit, resulting in an increase in hardware.

In addition, in the second method μ, a memory read is performed using a machine cycle signal, which is originally a memory write cycle, and it is necessary to transfer the machine cycle signal to various control systems, and requires a sophisticated control circuit. One hundred and five drawbacks were the increase in cycle signal wiring and hardware.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a tying pulse generation circuit t6 which has a simple circuit configuration and can be used in a machine cycle counter particularly effective for executing instructions of a microcomputer.

According to the present invention, in a timing pulse generation circuit that generates timing pulses of a number of values, there are 7 rip 70 tsugs set by the timing pulse generation request 1d and reset by the respective timing pulses and the nligflop. Timing pulse generation 1 comprising first and second control circuits for controlling 4 mink pulse generation 11 by output, and means for selectively energizing the control circuits.
1st place has changed uT's capable timing pulse generation circuit is here. Below is this output! An embodiment of A will be described with reference to the drawings. Figure 1 is a diagram explaining one embodiment of this invention.
6 connection diagram, set reset type 7 rig 7 to 11 to 13
It is outputted in synchronization with the clock y at 0 tsug (hereinafter abbreviated as 1 for F/'). 14 and 15μ or gate, 16-19
0011, which is an AND gate, is a timing generation client change request signal, and CI2 to 014 are timing signals M
This is generation request number 1d of 2 to M4. Figures 2 and 3 are time charts for explaining the operation in Figure 1.○
First, the operation of the circuit shown in FIG. 1 will be explained using FIG. 2.

Tizing occurs When Sanhyo Gogo C12 to C14 becomes resistant to ``1'' (hereinafter simply referred to as 1'1) with Ml's tie bank, the clock is set to 1;/k 11 to 13. In synchronization with f, the Q output becomes "1#" and the Q output becomes the processing "0" (hereinafter simply referred to as 10).OHere, since the timing generation order change request signal ELL is "0", the OR gate 14
t'X''1', and M2 is output next to the timing signal M1. While the timing signal M2 is being output, F7H''1
Since the Q output of 1 is 10#, all other timing signals are '0#. On the other hand, tf' , the Q output becomes '1#' and M3 is output.

Similarly, KM4 is output, and when all the bits are reset, Ml is output. As mentioned above, the order of typing occurrence is
+vil, M21M31M4-Ml. Then the third
Let's clarify using the time chart in the figure. The timing generation request signals C'12 and C13 are 11 at the timing of Ml.
``Then, ``YFl 1 and A・12 are set, +51 periods to clock y, Q output @ 1'', Q output is 10''
0Here, Tizening occurrence order change support 1g issue C1
Since 1 is @1'', the OR gate 15 becomes 11'', and the timing signal M3 is output next to the timing signal M1. Further, during the period of timing M3, since the OR gate 14 is @0'', M2 remains at @0''. Next, timing signal M3
When the output becomes 1”, the Q output becomes 1 in synchronization with the next clock.
0", the Q output becomes 11", and d2 is output.
Since F7113 is not set, the tying signal M
4 is not output, and Ml is output next to M2. As mentioned above, the tie bang occurrence 1- is s M 1 * M L
M 2 * M 1 and 9, the order of occurrence of M2 and M3 is changed 0 Combining this invention as a machine cycle counter for information processing equipment such as a microcomputer, M1 to M4 each, operation code 7 etching cycle, memory read cycle, calculation cycle, and memory write cycle. By allocating in this manner, for example, in the case of an instruction to transfer the result of operation between the contents of the memory and the contents of the general-purpose register to the memory, a timing signal is generated at j- of M 1 =td 4.

In the case of a button command that involves address calculation such as master index addressing, it is only necessary to change the order of occurrence of memo IJ read cycle M2 and calculation cycle M3, so extra memo 17 is needed between calculation cycle M3 and memory write cycle M4. There is no need to use all the hardware for +7- and cycle generation, and there is no need to use a control circuit that performs a memory read at 11 fcM4 timing, which is originally assigned to a memory write cycle, or a machine cycle of 1g to that control circuit. This is very effective because it eliminates the need for arranging numbers.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
3 and 3 are time charts for explaining the entire operation of the circuit shown in FIG. 1. 11-13...7 rigs 70 tsugs, 14.15
・・・・・・Or Gate, 16-19 Old...And Gate. :・:・ CIl~C14...Old...Control IB No., jl°°゛°°°Clock・Fig. 1CI4'' Fig. 2φ Fig. 3

Claims (1)

[Claims] In a timing pulse generation circuit that generates a plurality of timing pulses, the timing pulse generation order is determined by the outputs of the seven flip-flops and the free lag block, which are set by the timing pulse generation request signal and reset at each timing pulse. The first and second
A control circuit for timing pulse generation, characterized by comprising: a control circuit; and means for selectively energizing the control circuit.
r.