JPS62111329A - Method and circuit for preventing abnormal output of control circuit - Google Patents

Abstract

PURPOSE:To suppress the output of an abnormal control command to the external at the time of a program is abnormal by writing a data code in a latch register when a dummy writes signal, an address specifying signal and a write enable signal coincide with each other. CONSTITUTION:A dummy address signal 8 outputted from a dummy address '0' of a decoder 2 and a write enable signal 9 outputted from a central processor 1 are inputted to an AND gate 3, and when the input periods of both the signals coincide with each other, an dummy write enable signal 10 is outputted. The signal 10 is inputted to an one-shot circuit 4 and a dummy write signal 11 is outputted for a fixed period. When the dummy write signal 11, any one of address signals 12a-12d and the write enable signal 9 coincide with each other, any one of write signals 13a-13d is outputted from any one of AND gates 5a-5d to any one of latch registers 6a-6d.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for preventing abnormal output of a control circuit and a circuit overheating, and in particular to a method for outputting an abnormal control command to the outside when a program is abnormal in a microcomputer-controlled control device. The present invention relates to a method and circuit for preventing abnormal output of a control circuit, which is suitable for preventing the abnormal output of a control circuit.

Background of the Invention] The conventional device is as described in Japanese Patent Application Laid-Open No. 58-96301. In a microcomputer-controlled control device jS in which a control command is output to a controlled object via a memory according to a software program number, when outputting a control command to a controlled object, . There is a software program that triggers a retriggerable one-short circuit and outputs the control command stored in memory to the controlled object only while the trigger output is being output from the circuit. However, in the above method, the output of the control command manually entered into the memory is controlled on the output side of the memory, so with this method, it is necessary to add the AND gate used for this control means to all output signals. [Object of the Invention] The object of the present invention is to prevent abnormal output of a control circuit that has a simple structure and can prevent abnormal control commands from being output to the outside when an abnormality occurs in a program in mitaro computer control. An object of the present invention is to provide methods and circuits.

[Summary of the Invention] The present invention provides a control circuit that outputs a control command based on a software I/ware program number, outputs an address code and a data bus number to an address bus, and inputs an address code written in ifl. It outputs a write enable signal when the address code is stable.The central processing unit outputs the address code for the dummy address in addition to the address code for the specified address, and the address code from the address bus is manually input to the specified address.・It outputs a signal to light, and includes a decoder with a dummy address provided in a plurality of address selections, a dummy address word outputted from the decoder to the dummy address, and a dummy address word outputted from the central processing unit. A first AND gate that manually inputs a write enable signal and outputs a dummy write enable signal, and a dummy write in which the dummy write enable signal output from the first AND gate is input and the signal is stretched for a certain period of time. A one-shot circuit that outputs as a signal, a write signal output from the one-shot circuit, an address signal that was not output to another address while the signal was being output, and when the signal became stable. A second AND gate inputs the re-output write enable signal and outputs a write signal, and a second AND gate outputs a write signal by inputting the re-output write enable signal. It is characterized by consisting of a latch register that is manually operated and stored in response to the command of a write signal, and when the data code output from the central processing bag δ is taken into the latch register at the specified address, A dummy write symbol is set, and a 7 dress designation signal and a write enable signal are output while the dummy write signal is output, and when at least the three types of signals listed in @ are matched, the latch is first executed. The feature is that a signal is issued to write the data code to the register, and the data code is taken in.It has a simple structure and can output an abnormal control command to the outside when a program abnormality occurs in microcomputer control. It is designed to prevent

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 2.

In FIG. 1, reference numeral 1 denotes a central processing unit (hereinafter referred to as MPVJ), which is connected to a decoder 2 by an address bus 7. In this case, the decoder 2 can specify five addresses from $0 to $4, and logical product circuits (hereinafter referred to as "AND gates") 3 and 5a to 5d are connected to each address designation terminal. ing. Also, AND gates 3 and 5a to 5dl are wired to transmit write enable (No. 9) from MPUI. 4 is one shot < JIu, and one is connected to the output side of AND gate 3. and the other is connected to AND gates 5a to 5d.And gates 5a to 5d are further connected to decoder 2.
The connections are made corresponding to addresses $1 to $4. 6a~
A latch register 6d is connected to the AND gates 5a to 5d, and is also connected to the data bus 141 and the MPUI.

With the one-touch configuration, the MPU 1 outputs the address code 7a to the address bus 7, and if the data t<y,
14 c Data code 14 a is output, and when the output of address code 7a is stable, write enable signal 9 is output.
Output.

Decoder 2 receives address code 7 from address bus 7.
A is input, decoded, and a designated address of each address $0 to $4 is selected and a signal is output.

Here, address $0 is a dummy address.

The AND gate 3 which is the first AND circuit is connected to the decoder 2
Input the output from the tummy address $0, the tag 2-address "8", and the write enable signal 9 output from the MPUI, and manually input the dummy address signal 8 and write enable signal 9. When they match, a dummy write interrupt IL7 signal @10 is output.

The 1-1 circuit 4 inputs a dummy write enable signal 10 and outputs a dummy write signal 11 obtained by expanding the dummy write enable signal 10 for a certain period of time.

AND gates 5a to 5d, which are second AND circuits, use a decoder 2 to wta the dummy exchange signal 11 and another address code 7a re-outputted from the MPUI while the dummy write signal 11 is being output. The address signal 12a-12d output to the specified address and the signal 1
2 Write enable signal 9 re-outputted from MPUI when the output signal from any one of a to 12d becomes stable 7
When the output signals 11.12a to 12d match the write enable signal 9, one of the write signals 13a to 13d is output.

The latch register 6 receives the data code 14a output from the MPUI to the data bus 14 through the AND gates 5a to
Write signal 13a~1 output from any n of 5d
3. It is manually operated and stored in memory according to the signal command output from any one of d.

More specifically, as shown in FIG. 2, for example, when data output from the MPUI is set to the latch register 6a, the address code 7a that specifies the address $0 is first input.
is output from the MPU 1, and a dummy address signal 8 is output via the decoder 2.

When the dummy address signal 8 becomes stable, a write enable signal 9 is output, and a dummy write enable signal 10 is output from the gate 3. The write enable signal 10 is output as a dummy write signal 11 with an extended output time via the one-stop circuit 4. Further, while the dummy write signal 11 is being output, the address bus 7 has, for example,
Address code 7a specifying address $1 is output n
, an address symbol 12a is output via the decoder 2. Also, in this case, address code 7 specifies address $1.
When a is output, a data code 14a is output to the data bus 14 to the same person. When the address symbol 12a becomes stable, the write enable signal 9 is output. At this time,
The AND gate 5al inputs the dummy write signal 11, the address signal 12a, and the write enable signal 9, and outputs the input signal @13a.
Enter a. Then, data bus 141 outputs data code 14a to latch register 6.
Take it into a. Thereafter, the data in the latch register 63C is held.

On the other hand, with reference to FIG. 3, a case will be described in which, for example, a program that controls MPUI:11 goes out of control and an abnormal signal is output.

Address code 7a specifying address $0 is output, dummy address signal 8 is output, and at this time, when write enable signal 9 is output, dummy write enable (iT
Yang 10 comes out, Wangshi.

A dummy write signal @11 is output via the IT circuit 4.

Next, normally, the address code 7a where you want to write data is 1 as shown in qt2 u.
This is supposed to be output, but due to a program error, it is not output, and instead, for example, along with the address code 7a of the unspecified address $3, the unspecified data code 14 is output.
Even if a is output to the address bus 7 and data bus 14 and the write enable signal 9 is output, only the address signal 12C is output from the recorder 2 and is not output while the dummy write signal 11 is output. The write signal 13c is not output from the AND gate 5C, and no data is written to the latch register 6C.

As described above, according to this implementation 4 IAI, the latch register 63
A simple structure includes AND gates 5a to 5d that limit the write signal 13a to 6d, and an AND gate 3 and a one-shikabut circuit 4 for generating the dummy write signal 11. 1
If the address code 7a, data code 14a, and write enable signal 9 of the specified address are not output while 1 is output, it will not be possible to write to the specified latch register of the cape registers 62 to 6d. ,
While the dummy write signal 11 is being output, the old code 7
Since the probability that a, 14a, and signal 9 will be output is very small, there is an effect that a wrong data will not be output in the event of an abnormality.

[Effects of the Invention] According to the present invention, an AND gate and a one-shot circuit are provided to generate a dummy write signal, and the signal written to the latch register can be controlled. Since two write signals are issued continuously to write one output data, even if the microcomputer becomes unable to operate due to a program error, the output data of the latch register will not be changed.
This has the effect that it is possible to prevent abnormal control commands from being output to the outside without causing problems.

Brief explanation of the mountain surface: Figure 1 shows the abnormal output prevention circuit of the control circuit which is an embodiment of the present invention, and Figures 2 and 3 show the abnormal output prevention circuit.
This is the reason why the signals flowing through the circuit shown in the figure are shown.

1...MPU, 2...decoder, 3,
5a to 5d°''゛°゛°and gate, 4 ゛=-°゛Oneshi, Butto circuit, 6a to 6d...Ijiregister agent Patent attorney Katsutoshi Ogawa''-O1 figure

Claims (2)

[Claims] 1. In a control circuit that outputs control commands using a software program, a dummy write signal is set when the data code output from the central processing unit is loaded into a latch register at a specified address, and the dummy write signal is While the address is being output, an address designation signal and a write enable signal are output, and when at least the above three or more types of signals match, a command signal to write the data code to the latch register is output for the first time, and the data code is read in. A method for preventing abnormal output of a control circuit, characterized in that: 2. It outputs an address code to an address bus and a data code to a data bus, and outputs a write enable signal when the output of the address code becomes stable.
a central processing unit that outputs an address code for a dummy address before outputting an address code for a specified address; and a central processing unit that inputs an address code from the address bus and outputs a signal to the specified address light; A first decoder having a dummy address in its selection, a dummy address signal output from the decoder to the dummy address, and a write enable signal output from the central processing unit, and outputting a dummy write enable signal. a one-shot circuit that inputs the dummy write enable signal output from the first AND gate and outputs the signal as a dummy write signal by stretching the signal for a certain period of time; and a dummy write enable signal output from the one-shot circuit. A second AND which outputs a write signal by inputting the write signal, the address signal output to another address while the signal was being output, and the write enable signal output again when the signal stabilized. Abnormal output of a control circuit comprising a gate and a latch register that inputs and stores the data code outputted to the data bus according to a command of a write signal outputted from the second AND gate. prevention circuit.