JP3055903B2 - Data reading device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for reading one or a plurality of registers at a constant bit width by designating an address, and particularly, for reading a timer value and the like. The present invention relates to a device for reading a value that changes asynchronously from a read operation in a plurality of times.

[Prior Art] When data that is updated asynchronously with the timing at which the value is read, such as a timer value, is read in a plurality of times, the data is read in several times. There is a problem that an update occurs during partial reading, and an accurate value cannot be read.

Here, an example will be described with reference to FIG. FIG. 7 shows an example in which a 4-digit value is read out four times, one digit at a time.

First, in state 1, the least significant digit “9” is read. Next, in state 2, the second digit "9" from the bottom is read. Here, when an update instruction is issued to the data register to be read, the value is incremented by one. At this time, the value of the data register changes from “8999” to “900”.
0 ". In state 3, the third digit from the bottom is read. At this time, since the value has already been changed to" 9000 ", the read value becomes" 0. " Read the upper digit “9.” Here, the value to be read is originally
What should be "8999" or "9000", but the value actually read becomes "9099" which is totally random.

Conventionally, there are the following two methods for solving this problem.

The first method is to solve the problem in software. In this method, the same data register is read twice, and if the value is the same both times, the value is determined to be a correct value.

 The second method is the method shown in FIG.

First, it is assumed that there are four data registers to be read: data register 1, data register 2, data register 3, and data register 4. It is assumed that these four data registers have the same bit width and are updated independently of the read operation. Here, it is assumed that the reading side wants to read the data in four digits.

First, the address register 5 is set so that the value of the data register to be read is selected by the register selector 6 '. After that, the output of the register selector 6 'is received by the read buffer 7'. At this time, an accurate value is always set in the read buffer 7 '. Then, by reading the value of the read buffer 7 'by specifying the digit register 8' one digit at a time, an accurate value can be read.

[Problems to be Solved by the Invention] As described above, the value of one or a plurality of registers holding data whose value changes asynchronously with a read operation such as a timer value is partially changed a plurality of times. Conventionally, there are two methods for reading an accurate value separately.

The first method is, as described above, a method in which the same data register is read twice, and when the values match, it is determined that the value is an accurate value. This method has the disadvantages that it takes time and effort to read, and that if the data register is updated more than a certain speed with respect to the reading speed, the values will not match no matter how many times the data is read.

The second method is, as described above, a method in which data at that time is once stored in a read buffer and then partially read. In this case, there is a drawback in that two processes of first reading the data into the read buffer and then partially reading the data must be performed, and the read buffer must always be considered.

[Means for Solving the Problems] A data reading device according to the present invention comprises at least one data register for holding data for which reading and updating are performed at independent timings, and wherein the data held in the data register is partially stored. The intermediate data holding unit for holding data in the middle of being read when the data is read a plurality of times, and the data register and the intermediate data holding unit are divided into a fixed bit width, and the address is assigned. An address register designating an address; selecting and outputting the data held in the data register and the intermediate data holding unit according to an address from the address register; and simultaneously outputting the intermediate result of the selection to the intermediate data holding unit. And a data selection unit to be output.

Further, another data reading device of the present invention is configured such that at least one of the data selectors being selected by the intermediate data holding unit is selected by the address from the address register.
And a read instructing unit that instructs to read one of the data.

Further, another data reading device of the present invention further includes a read instruction flag for instructing the intermediate data holding unit to read at least one data being selected by the data selection unit.

Example Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a data reading device according to a first embodiment of the present invention.

In FIG. 1, a data register 1, a data register 2, a data register 3, and a data register 4 hold data, such as a timer value, which is changed asynchronously with the read timing. The address register 5 instructs a data selection unit 6 described later on the address of the data to be read.

The data selection unit 6 divides the data register 1, the data register 2, the data register 3, and the data register 4 by four digits, and stores one digit in each of them or the register 13, the register 14, and the register
Select one of 15 and output.

In the data selection unit 6, the selector 8 selects one of the most significant digits of the data register 1, the data register 2, the data register 3, and the data register 4. Selector 9
Selects the second digit from the top of the data register 1, the data register 2, the data register 3, and the data register 4, or the register 13 of the intermediate data holding unit 7. Selector 10
Selects the third digit from the top of the data register 1, the data register 2, the data register 3, and the data register 4, or one of the registers 14 of the intermediate data holding unit 7. The selector 11 selects one of the least significant digits of the data register 1, the data register 2, the data register 3, and the data register 4 or one of the registers 15 of the intermediate data holding unit 7. The selector 12 selects one of the selector 8, the selector 9, the selector 10, and the selector 11, outputs the selected one, and uses this output as the output of the data selector 6.

The intermediate data holding unit 7 outputs the selector 9 in the data selection unit 6 and the selector 9
10. Hold the output of the selector 11.

In the intermediate data holding unit 7, the register 13 stores the output of the selector 9 of the data selection unit 6, and the register 14 stores the output of the selector 10.
And the register 15 holds the output of the selector 11.

In FIG. 1, the relationship between the outputs of the selector 8, selector 9, selector 10, and selector 11 of the data selector 6 and the address register 5 is as shown in FIG.

Here, in FIG. 4, the value in parentheses indicates the number of the digit from the top. For example, the register 1 (2) means the second digit from the top of the data register 1. Also register 1
3, register 14, register 15 are data register 1, data register 2, data register 3, data register 4.
Has the same bit width as the bit width divided into four. The address register 5 has 5 bits.

FIG. 5 shows the relationship between the output of the selector 12 and the address register 5.

Here, a case where the data held in the data register 2 is read will be considered. Normally, by reading the value of the address register 5 in the order of “00100” → “00101” → “00110” → “00111”, the value of the data register 2 can be read one digit at a time from the top.

However, in this case, if the value of the data register 2 is updated during reading, an erroneous value will be read.

Therefore, first, "00100" is set in the address register 5 in order to read the most significant digit.

In this case, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 are the first digit, the second digit, the third digit, and the fourth digit from the upper side of the data register 2, respectively. As shown in FIG. 5, the output of the selector 12 outputs the output of the selector 8, that is, the most significant digit of the data register 2. At this time, the registers 13, register 14, and register 15 of the intermediate data holding unit 7 store the values of the selector 9, selector 10, and selector 11, that is, the second, third, and fourth digits of the data register 2 from the upper order. Hold. Therefore, instead of reading the second and lower digits of the data register 2, the register 13, the register 14, and the register 15 are read.

First, to read the register 13, the address register 5 is set to "10101".

At this time, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 become the data register 2 (1), the register 13, the register 14, and the register 15, respectively, as shown in FIG. Therefore, register 13, register 14, register 15
, The same value is set, so that the registers 13, 14 and 15 are held.

At this time, the output of the selector 12 becomes the value of the register 13 from FIG. At this time, the value of the register 13 is the value of the data register 2 (1) which was read earlier.
(2).

Similarly, when the values of the registers 14 and 15 are read out by setting “10110” and “10111” in the address register 5, respectively, the data register 2 (3) when the data register 2 (1) is read first is read out. ), Data register 2 (4)
Can be read, whereby the value of the data register 2 can be read accurately.

Referring to FIG. 2, a data reading device according to a second embodiment of the present invention is the same as that of FIG. 1 except that a read instruction unit 16 is added and an intermediate data holding unit is changed. It has a configuration of Therefore, the intermediate data storage
Write 7a. The intermediate data holding unit 7a has registers 13a, 14a, and 15a.

The intermediate data holding unit 7a outputs the selector 9 in the data selection unit 6, the selector
10, the output of the selector 11, the output of the read instruction unit 16 is "1"
At the time, read.

In the intermediate data holding unit 7a, the register 13a holds the output of the selector 9 of the data selection unit 6, the register 14a holds the output of the selector 10, and the register 15a holds the output of the selector 11.

FIG. 6 shows the relationship between the output of the read instruction unit 16 and the address register 5.

As in the first embodiment, a case where the data held in the data register 2 is read will be considered.

First, "00100" is set in the address register 5 in order to read the most significant digit. In this case, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 are the first digit, the second digit, the third digit, and the fourth digit from the upper side of the data register 2, respectively. As shown in FIG. 5, the output of the selector 12 outputs the output of the selector 8, that is, the most significant digit of the data register 2. At this time, since the output of the read instruction unit 16 is “1” from the value of the address register 5, the values of the selector 9, the selector 10, and the selector 11 That is, the second digit, the third digit,
Read the value of the fourth digit. Therefore, 2 of data register 2
Instead of reading the digits below, register 13a and register 14
a, read register 15a.

First, to read register 13a, address register 5
Is set to “10101”. At this time, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 become the data register 2 (1), the register 13a, the register 14a, and the register 15a as shown in FIG. Further, the output of the read instruction unit 16 becomes “0” based on the value of the address register 5, and the values of the registers 13a, 14a, and 15a are held at the current values.

Here, the output of the selector 12 is shown in FIG.
The value of a. The value of the register 13a at this time is the value of the data register 2 (2) when the data register 2 (1) is read first.
It is.

Similarly, when the values of the register 14a and the register 15a are read out by setting “10110” and “10111” in the address register 5, respectively, the data register 2 (3) when the data register 2 (1) is read first is read out, respectively. ), Data register 2
Thus, the value of (4) can be read, whereby the value of the data register 2 can be read accurately.

Referring to FIG. The data reading device according to the third embodiment of the present invention has the same configuration as that of FIG. 2 except that a reading flag 16a is provided instead of the reading instruction unit 16.

The intermediate data holding unit 7a outputs the selector 9 in the data selection unit 6, the selector
10, the output of the selector 11 is read, and the read instruction flag 16a is set to "1".
At the time, read.

Next, as in the first embodiment, a case where the data held in the data register 2 is read will be considered.

First, to read the most significant digit, “00100” is output to the address register 5 and at the same time, the read instruction flag 16 is read.
Set a to “1”. At this time, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 are the first digit, the second digit, the third digit,
This is the fourth digit. As shown in FIG. 5, the output of the selector 12 outputs the output of the selector 8, that is, the most significant digit of the data register 2. At this time, the register of the intermediate data holding unit 7a
Since the read instruction flag 16a is "1", the values of the register 9a, the selector 14a, and the register 15a
0, the value of the selector 11, that is, the second, third, and fourth digits of the data register 2 from the higher order are read. Therefore, instead of reading the second and lower digits of data register 2,
The registers 13a, 14a, and 15a are read.

First, to read register 13a, address register 5
Is set to “10101”. At this time, the outputs of the selector 8, the selector 9, the selector 10, and the selector 11 become the data register 2 (1), the register 13a, the register 14a, and the register 15a as shown in FIG. At this time, by setting the value of the read instruction flag 16a to “0”, the register 13
a, the values of the registers 14a and 15a are held at the current values.

Here, the output of the selector 12 is shown in FIG.
The value of a. The value of the register 13a at this time is the value of the data register 2 (2) when the data register 2 (1) is read first.
It is.

Similarly, when the values of the register 14a and the register 15a are read out by setting “10110” and “10111” in the address register 5, respectively, the data register 2 (3) when the data register 2 (1) is read first is read out, respectively. ), Data register 2
Thus, the value of (4) can be read, whereby the value of the data register 2 can be read accurately.

[Effects of the Invention] As described above, according to the present invention, a data register that is changed asynchronously with the read timing and a register of the intermediate data holding unit are separated by a fixed bit width, addresses are assigned, and the addresses are used. The data selector and the intermediate data holding unit for holding data in the middle of the selection by the data selecting unit, or having the data register and the intermediate data holding unit that are changed asynchronously with the read timing. A register is divided by a fixed bit width, an address is assigned, a data selection unit that is selected by a selector using the address, an intermediate data holding unit that holds data being selected by the data selection unit, and a specified address value, A read instruction unit for outputting a read instruction to the intermediate data holding unit, or The data register, which is changed asynchronously with the timing, is separated from the register of the intermediate data holding unit by a fixed bit width, an address is allocated, and a data selection unit is selected by the selector using the address. By having an intermediate data holding unit for holding the data of the first data and a read instruction flag for giving a read instruction to the intermediate data holding unit, the data is read twice to assure the data. There is an effect that there is no need to perform a software process of guaranteeing the value by performing the operation or a process of guaranteeing the value by reading the contents of the buffer after reading the buffer once.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data reading device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a data reading device according to a second embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a configuration of a data reading device according to a third embodiment of the present invention. FIG. 4 is a diagram showing a relationship between selectors 8, 9, 10, and 11 of a data selection unit and an address register 5 in FIG. FIG. 5 shows the selector of the data selection unit in FIG.
FIG. 6 is a diagram showing the relationship between the address register 5 and the address register 5, FIG. 6 is a diagram showing the relationship between the output of the read instruction unit 16 in FIG. 2 and the address register 5, and FIG. 7 explains the problem of partial reading. FIG. 8 is a block diagram showing a configuration of a conventional data reading device. 1-4 data registers, 5 address registers,
6: Data selection unit, 7, 7a: Intermediate data holding unit, 8 to
12 ... Selector, 13-15, 13a-15a ... Register, 16 ...
... Read instruction section, 16a ... Read instruction flag.

Claims (3)

(57) [Claims] At least one data register for holding data for which reading and updating are performed at independent timings, and reading when the data held in the data register is partially read a plurality of times An intermediate data holding unit that holds data in the middle of data transfer, an address register that divides the data register and the intermediate data holding unit into a fixed bit width, performs address assignment, and indicates the assigned address; And a data selector for selecting and outputting the data held in the data register and the intermediate data holding unit according to the address of the data register and outputting an intermediate result of the selection to the intermediate data holding unit. Data reading device. 2. The image processing apparatus according to claim 1, further comprising: a read instruction unit that instructs the intermediate data holding unit to read at least one piece of the data that is being selected by the data selection unit, based on an address from the address register. 2. The data reading device according to claim 1, wherein 3. The data reading device according to claim 1, further comprising a reading instruction flag for instructing said intermediate data holding unit to read at least one data being selected by said data selecting unit. .