JPH0830464A - Interruption processing circuit - Google Patents

Abstract

PURPOSE:To level the acceptance of economical interruptions of the same level. CONSTITUTION:Write address registers 1-1-1-n hold write addresses assigned to an interruption group and interruption registers 2-1-2-n hold the interruption factors of the interruption group. In an interruption memory 6, the contents of the interruption registers 2-1-2-n selected by an interruption register selection part 5 are written in the write addresses of the write address registers 1-1-1-n selected by a write address selection part 4. Interruption factors in group units which are stored in the interruption memory 6 are read out by a read address register 7 and an update circuit 8 independently of the writing operation and then held in an interruption read register 9. When plural interruption factors are present in the output 109 of the interruption read register 9, a priority circuit 10 selects and outputs those interruption factors to a host device according to previously set priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing circuit,
In particular, it relates to a method for speeding up and leveling interrupt processing for processing a plurality of interrupt requests of the same level.

[0002]

2. Description of the Related Art Conventionally, in an interrupt control device, an interrupt request to be processed by a priority circuit is selected according to a preset priority.

If this method is applied to a case where there are a plurality of interrupt requests of the same level, priority levels will be added to the interrupt requests even if they are of the same level. Therefore, interrupt requests to which low priority levels are assigned are high. There is a problem that interrupt acceptance is not leveled depending on the interrupt request to which the priority is assigned.

To solve this problem, there is a method of leveling interrupt acceptance by setting an interrupt level for each interrupt request and changing the interrupt level as necessary.

There is also a method in which a plurality of interrupt factor registers holding the representative bits of a plurality of interrupt requests are provided and these interrupt factor registers are sequentially scanned and processed one by one.

[0006]

In the above-mentioned conventional interrupt control device, the interrupt level is set in the case of the method of leveling the interrupt acceptance by changing the interrupt level set for each interrupt request as needed. Therefore, there is a problem that the amount of metal for the increase.

Further, in the case of the method of sequentially scanning the interrupt factor registers one by one, a circuit for scanning is required in proportion to the interrupt factor, which causes an increase in the amount of metal and is not economical.

There is also a problem that it takes a long time until the interrupt factor to be finally scanned is accepted depending on the scanning order.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide an economical interrupt processing circuit which can level interrupt acceptance at the same level.

[0010]

An interrupt processing circuit according to the present invention comprises a holding means for holding an interrupt factor indicating the occurrence of the interrupt request for each of a plurality of interrupt request groups each consisting of a plurality of preset interrupt requests. , The content of the holding means is stored at an address given in advance to the corresponding interrupt request group, and the content of the holding memory is read independently of the operation of writing the content of the holding means to the interrupt memory. And a means for notifying an upper level device of an interrupt request corresponding to the interrupt factor when the interrupt factor is present in the contents of the interrupt memory read by the read unit.

According to another interrupt processing circuit of the present invention, in addition to the above configuration, when a plurality of interrupt factors are present in the contents of the interrupt memory read by the reading means, a predetermined priority order is set. It is provided with means for notifying the host device of an interrupt request corresponding to one of the plurality of interrupt factors.

In addition to the above-mentioned configuration, another interrupt processing circuit according to the present invention is such that the identification information previously assigned to the interrupt request group to which the interrupt request to be notified to the host device belongs and the position of the interrupt request in the interrupt request group. And information for indicating to the higher-level device.

According to still another interrupt processing circuit of the present invention, in addition to the above configuration, all interrupt requests corresponding to interrupt factors contained in the contents of the interrupt memory read by the reading means are notified to the higher-level device. And a means for updating the read address to be output from the read means to the interrupt memory when being read.

[0014]

The write addresses of the interrupt memories respectively assigned to the preset interrupt groups are set in the write address register, and a plurality of interrupt factors pre-grouped are held in the interrupt register.

When an interrupt factor for each group is detected from the output of each interrupt register, a write address and an interrupt register corresponding to the detected interrupt factor are selected so that each interrupt group is assigned. The selected interrupt factor is stored in the address of the interrupt memory indicated by the write address.

Independently of this write operation, the interrupt factors for each group read from the interrupt memory are held in the interrupt read register. The output order of the interrupt factors is determined according to a preset priority order and output to the host device.

At this time, the interrupt number within the group indicating the position in the interrupt group of the interrupt factor selected according to the priority in the priority circuit and the interrupt group number specified by the read address to the interrupt memory are interrupted. It is sent to the host device as a number.

As a result, an increase in the amount of hardware for setting the interrupt level and an increase in the amount of hardware for the circuit for scanning are not caused, so that it is possible to level interrupt acceptance at the same level economically. it can.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, write address register 1
In -1 to 1-n, write addresses of the interrupt memory 6 assigned to preset interrupt groups are set.

The interrupt registers 2-1 to 2-n have four interrupt factors INT1 to INT4, which are grouped in advance.
.., INT (4n-3) to INT4n are held respectively.

The write control unit 3 includes interrupt registers 2-1 to 2-1.
An interrupt factor for each group is detected from the outputs 102-1 to 102-n of each 2-n, a selection signal 103 is generated according to the detection result, and is output to the write address selection unit 4 and the interrupt register selection unit 6. .

The write address selector 4 is the write controller 3
The interrupt memory 6 is selected by selecting one of the write addresses 101-1 to 101-n which are assigned to each group and held in the write address registers 1-1 to 1-n in accordance with the selection signal 103 from the. Output to.

The interrupt register selector 5 is a write controller 3
According to the selection signal 103 from the interrupt register 2-
One of the outputs 102-1 to 102-n of each of 1 to 2-n is selected and output to the interrupt memory 6.

The interrupt memory 6 has a write address selection unit 4
At the address designated by the write address 104 selected in step 1, the interrupt factor 1 selected in the interrupt register selector 5
05 is stored.

The read address register 7 holds a read address 107 for reading the interrupt factor stored in the interrupt memory 6 for each group, and the update circuit 8 updates the value of the read address 107 from the read address register 7. . In this case, the update circuit 8 uses the read address 10
The value of 7 is incremented by "1".

The interrupt read register 9 is the interrupt memory 6
The interrupt factor 106 for each group read from is held, and the content of the interrupt factor is updated from "1" to "0" in response to the interrupt acceptance signal 113 from the host device (not shown).

When a plurality of interrupt factors are present in the output 109 of the interrupt read register 9, the priority level circuit 10 determines the output level of these interrupt factors according to a preset priority level, and the determined interrupt request 110. Is output to the host device.

At this time, the priority circuit 10 outputs the information indicating the position in the interrupt group of the interrupt factor selected according to the priority to the in-group address register 12 as the in-group interrupt number 111.

The interrupt group number register 11 holds the read address 107 from the read address register 7 as an interrupt group number, and the in-group address register 12 holds the in-group interrupt number 111 from the priority order circuit 10.

The interrupt group number held in the interrupt group number register 11 and the in-group interrupt number held in the in-group address register 12 are sent to the host device as an interrupt number 112.

The operation of the embodiment of the present invention will be described with reference to FIG. Generally, in a device having a large number of interrupt requests, a priority order is assigned to a plurality of interrupt requests and the interrupt request is issued to a higher-level device according to the priority order.

Various methods have been proposed as a method for selecting one from the plurality of interrupt requests, but in one embodiment of the present invention, a large number of interrupt requests are grouped,
The interrupt factor is written into the preset address of the interrupt memory 6 for each group unit, and the interrupt factor is read from the interrupt memory 6 independently of the writing operation, so that the interrupt processing is speeded up and leveled.

Now, an interrupt request IN is issued from a lower device (not shown).
When T1 to INT4n are generated, these interrupt requests I
NT1 to INT4n are held in the interrupt registers 2-1 to 2-n and then notified to the write control unit 3.

The write control unit 3 has interrupt registers 2-1 to 2-1.
An interrupt factor for each group is detected from the outputs 102-1 to 102-n of each 2-n, a selection signal 103 is generated according to the detection result, and is output to the write address selection unit 4 and the interrupt register selection unit 6. .

In the write address selection unit 4, write address registers 1-1 to 1-n are assigned to each group according to the selection signal 103 from the write control unit 3.
One of the write addresses 101-1 to 101-n held in the memory is selected and output to the interrupt memory 6.

The interrupt register selector 5 is the write controller 3
According to the selection signal 103 from the interrupt register 2-
One of the outputs 102-1 to 102-n of each of 1 to 2-n is selected and output to the interrupt memory 6.

Therefore, the interrupt factor 105 selected by the interrupt register selecting unit 5 is written in the interrupt memory 6 at the address designated by the write address 104 selected by the write address selecting unit 4. The above operation is repeatedly executed each time an interrupt request is issued from the lower device.

The structure of the interrupt memory 6 is such that the address direction is an address of a preset group unit and the data direction is the number of bits indicating each pre-grouped interrupt factor.

On the other hand, the interrupt factor written in the interrupt memory 6 is detected, and the detected interrupt factor is sent to the interrupt request 1
It is necessary to perform an operation of notifying the host device as 10 and interrupt number 112.

The detection of the interrupt factor is performed by reading the contents of the interrupt memory 6. At this time, the read address supplied to the interrupt memory 6 is sequentially counted up by the update circuit 8 and stored in the read address register 7. To be done.

The update circuit 8 is preset to update the read address when all the contents of the interrupt read register 9 become "0".

Therefore, when there is no interrupt factor in the group-by-group interrupt factors 106 read from the interrupt memory 6 at the read address 107 from the read address register 7, the contents of the interrupt read register 9 are all "0". Therefore, the read address 107 is counted up by the update circuit 8 and the interrupt factor of the next group is read from the interrupt memory 6.

When there is an interrupt factor in the interrupt factors 106 read from the interrupt memory 6 for each group, the priority order circuit 10 determines the priority order within the group, and the selected interrupt The in-group interrupt number 111 of the factor is generated.

In this case, since the interrupt group number of the selected interrupt factor is designated by the write address stored in advance in the write address registers 1-1 to 1-n, the read from the read address register 7 is performed. It can be realized by storing the address 107 in the interrupt group number register 11.

Therefore, the contents of the interrupt group number register 11 and the in-group address register 1 are included in the upper device.
By notifying the contents of No. 2 as the interrupt number 112, information for specifying the detected interrupt factor can be notified to the host device.

When the host device receives the interrupt request 110 specified by the interrupt number 112, it outputs an interrupt acceptance signal 113.

When the interrupt acceptance signal 113 from the host device is input to the interrupt read register 9, the interrupt factor corresponding to the interrupt number 112 requested to the host device is set to "0".
To

By repeating this operation, when all the contents of the interrupt read register 9 become "0", the read address 107 is counted up by the update circuit 8 and the interrupt factor of the next group is read from the interrupt memory 6. To be done.

As described above, the plurality of interrupt requests INT1 to INT1
The INTs 4n are grouped and held in the interrupt registers 2-1 to 2-n for each group.
The interrupt factors held in -1 to 2-n are written in the address of the interrupt memory 6 indicated by the write address given in advance for each group, and the contents of the interrupt memory 6 are read independently of this write operation. When there is an interrupt factor in the read contents of the interrupt memory 6, by notifying the host device of the interrupt request corresponding to the interrupt factor,
The interrupt process can be executed without increasing the amount of metal for setting the interrupt level and the amount of metal for the circuit for scanning.

Further, since the interrupt request is written in the interrupt memory 6 at an arbitrary timing and sequentially read, it may be accepted early or late, so that it is possible to level interrupt acceptance at the same level. Become. Therefore,
Economical and equal level of interrupt acceptance can be leveled.

[0052]

As described above, according to the present invention, an interrupt factor indicating the generation of an interrupt request is held for each of a plurality of interrupt request groups each consisting of a plurality of preset interrupt requests, and this hold is held. The written contents are written in the interrupt memory based on the address given in advance to the corresponding interrupt request group, the contents of the interrupt memory are read out independently of the writing operation, and the interrupt factor is read in the read contents of the interrupt memory. By notifying the host device of the interrupt request corresponding to the interrupt factor when existing, there is an effect that the interrupt acceptance of the same level can be leveled economically.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

 1-1 to 1-n write address register 2-1 to 2-n interrupt register 3 write control unit 4 write address selection unit 5 interrupt register selection unit 6 interrupt memory 7 read address register 8 update circuit 9 interrupt read register 10 priority order Circuit 11 Interrupt group number register 12 Group address register

Claims (4)

[Claims] 1. A holding unit for holding an interrupt factor indicating the occurrence of the interrupt request for each of a plurality of interrupt request groups each including a plurality of preset interrupt requests, and an interrupt request group corresponding to the contents of the holding unit. An interrupt memory for storing the contents of the holding means into the interrupt memory independently of the operation of writing the contents of the holding means into the interrupt memory; and the reading means read by the reading means. An interrupt processing circuit, comprising means for notifying an upper level device of an interrupt request corresponding to the interrupt factor when the interrupt factor exists in the contents of the interrupt memory. 2. When a plurality of interrupt factors are present in the contents of the interrupt memory read by the reading means, an interrupt request corresponding to one of the plurality of interrupt factors according to a predetermined priority order. 2. The interrupt processing circuit according to claim 1, further comprising means for notifying the host device of the interruption. 3. A means for notifying the higher-level device of identification information given in advance to an interrupt request group to which the interrupt request of which the higher-level device is notified belongs and information indicating the position of the interrupt request in the interrupt request group. Item 1 or claim 2
The described interrupt processing circuit. 4. A read address output from the reading unit to the interrupt memory when all interrupt requests corresponding to interrupt factors included in the contents of the interrupt memory read by the reading unit are notified to the host device. 4. The interrupt processing circuit according to claim 1, further comprising means for updating.