JPH06176559A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the reading out speed of data information by providing a precedent reading out means and precedently executing the reading out of data information by the upper addresses relating to time in data access. CONSTITUTION:The precedent reading out means 10 is formed of an internal address generating means 11, a comparing means 12 and a timing control means 13. This internal address generating means 10 is inputted with the address information from the first address generating means 21 provided in an address buffer means 2 and changes the address information already stored in accordance with a prescribed control signal. The comparing means 12 compares the address information of the internal address generating means 21 and the address information from the first address generating means 21 and outputs the signal for precedently reading plural pieces of data information groups corresponding to the address information out of a memory cell 3. A prescribed control signal is simultaneously generated to the internal address generating means 11 and the address is changed by changing the counter value of the counter circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of efficiently reading data information stored in a memory at high speed.

[0002]

2. Description of the Related Art In recent years, the use of a non-volatile memory such as a batch erasing type semiconductor memory device having a floating gate and a control gate for replacement of a magnetic disk has been remarkably increased. This is because, for example, in the case of a magnetic medium, a certain amount of data (for example, 256
(Reading and writing is performed in units of bytes, 512 bytes, etc.), but when this operation is replaced with a memory or the like made of a semiconductor to increase the speed, random access to all addresses is not essential. It is said that random access is possible in a certain address unit.

Further, it is sufficient that consecutive addresses can be sequentially accessed within such a unit, but in order to improve the performance of the entire semiconductor memory device, it is desired to perform such sequential access at high speed. By the way, in a conventional semiconductor memory device or the like in which a memory is configured by using a semiconductor,
A method is adopted in which a plurality of sense amplifiers are provided per bit so that data for a plurality of addresses can be read in parallel, and the output of the sense amplifiers is selected by the address.

FIG. 3 shows the configuration of a specific example of the conventional semiconductor memory device 1. That is, in FIG. 3, at least an address buffer 2, a memory cell unit 3, a word line selection unit 4, a bit line selection unit 5, a sense amplifier 6, a sense amplifier 6, which receives an address input ADD input from an appropriate external storage circuit. A semiconductor memory device 1 including an amplifier selecting means 7 and an output buffer 8 is shown, and a first number of data information groups of a predetermined number are simultaneously accessed and read from the address buffer means 2.
Second address generating means and a second individually selecting the plurality of data information selected by the first address generating means.
Address generating means is provided, and the first address generating means selects, for example, a predetermined word line from a plurality of word lines WL and stores a plurality of word lines stored along the word line. This is the one in which all the data information is read out, and is generally called an upper address.

On the other hand, the second address generating means appropriately and individually selects each of the bit lines BL in order to select each of the plurality of data information selected by the above-mentioned upper address. Is generated, and is generally called a lower address. In the conventional semiconductor memory device 1 having such a configuration, it takes time to read the data by the first address generating means, that is, the upper address, and the second address generating means, that is, the bit line selecting means by the lower address. The read operation of the selection means data for each bit line BL is executed in an extremely short time.

That is, in the conventional semiconductor memory device, the selection of the data information by the upper address takes time, but the upper address is fixed, that is, the upper address does not change. In addition, it is possible to select the data information by the lower address at random and at high speed, but when selecting the upper address again, there is a problem that the access time becomes long.

The cause of this is
When selecting a predetermined word line WL, the word line W
Since a large amount of data is added to L, the read operation takes time, and at the same time when the data information selected from the word line WL is once written to the sense amplifier 6, Since the potential is not stable for a while after the power is turned on, it is not known whether accurate data information will be written even if the data information is written during that time. The operation of setting the time and writing the predetermined data information to the sense amplifier 6 is performed only after the sense waiting time has elapsed.

Therefore, in the prior art, as shown in the timing chart of FIG. 4, after the upper address reads the data information (0, 1, 2, 3) of the address m for a predetermined time. When writing the data information to the sense amplifier 7 or the like, the period displayed as X is set as a sense wait time, in which no operation is performed, and after the wait time has elapsed, each data Information (0, 1, 2, 3) is written in each sense amplifier 7, and then the sense amplifier selecting means 7 sequentially outputs the information from the output buffer 8.

That is, in the conventional semiconductor memory device 1, since there is such a sensing wait time, it takes a long time to read the data, so that there is a problem that it cannot be adapted to high speed operation. There was In particular, the semiconductor memory device 1
In this case, when accessing more consecutive addresses than the number of built-in sense amplifiers per bit,
Since there is a waiting time for the sense amplifier operation on the way, there is also a problem that it is impossible to read the output of the data at even time intervals and at high speed.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and provide a semiconductor memory device capable of reading a plurality of data information stored in a memory cell means at high speed. In particular, the present invention provides a semiconductor memory device capable of reading consecutive addresses at high speed and at equal intervals.

[0011]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, at least the address buffer means, the memory cell means, the word line selection means, the bit line selection means, the output buffer, and the address buffer means are connected, and a plurality of data information is regarded as one group, and one address is set for each group. In a semiconductor memory device including first address generating means for giving a first address, and second address generating means for giving a first address to each of the individual data information. First read means for selecting and reading one of the plurality of data information groups by using one address value in the means through either the word line selecting means or the bit line selecting means, the first address In the second address generating means, individual data information constituting the plurality of data information groups selectively read by one address of the generating means is generated. The second read means for selectively reading to the output buffer via either the bit line selection means or the word line selection means using the address value according to the second read means and the first address generation means. After reading the predetermined plurality of data information by the address, each of the plurality of data information read by the one address of the first address generating means is converted into the respective address in the second address generating means. By using the other address value in the first address generating means, another address corresponding to the other address in the first address generating means is used until it is selectively read by the output buffer. A semiconductor memory device provided with a preceding read means for reading a plurality of data information groups.

[0012]

In the semiconductor memory device according to the present invention, since the basic technical configuration as described above is adopted, the memory cell means is conventionally accessed by using the higher address.
After the predetermined data information is once output to the output buffer, when the next or another upper address is subsequently used to access the memory cell means again, the upper address is used to access the memory cell means. Therefore, while the predetermined data information is read out and once written and stored in the sense amplifier, the sense waiting time as described above is set and no operation is performed during that period. In the present invention, the sense waiting time is used to access the memory cell means in advance by using the next or another higher-order address, and the data information corresponding to the address is read and waited. Is.

That is, in the semiconductor memory device according to the present invention, the reading speed of the data information is increased by executing the reading of the data information by the upper address, which takes time to access the data, in advance. It is what makes me.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor memory device according to the present invention will be described in detail below with reference to the drawings. That is, FIG.
FIG. 1 is a block diagram showing a configuration of a specific example of the semiconductor memory device 1 according to the present invention. In the figure,
At least the address buffer unit 2, the memory cell unit 3, the word line selecting unit 4, the bit line selecting unit 5, the output buffer 8 and the address buffer unit 2 are connected to each other, and a plurality of pieces of data information are regarded as one group, and each group is connected. First address generating means 2 for assigning an address of 1 to
1. In the semiconductor memory device 1 including the second address generating means 22 for assigning 1 address to each of the individual data information, further, in the first address generating means 21, First read means 14 for selecting and reading one of a plurality of data information groups using any of the word line selecting means 4 and the bit line selecting means 5 by using the address value of the above, and the first address generating means. The second address generating means 22 outputs the individual data information constituting the plurality of data information groups selectively read by one address
Second read means 7 for selectively reading to the output buffer 8 via either the bit line selection means 5 or the word line selection means 4 using the address value in Each of the plurality of data information read by the one address from the first address generating means after the predetermined plurality of data information is read by the one address from the means, Output buffer 8 selectively according to each address in the generating means
While being read, the other address values in the first address generating means are used to generate a plurality of other pieces of data information corresponding to the other addresses in the first address generating means. A semiconductor memory device 1 provided with a preceding read means 10 for reading a group is shown.

That is, the semiconductor memory device 1 according to the present invention.
The configuration is basically the same as the configuration of the conventional semiconductor memory device 1 shown in FIG. 3, except that, as described above, the sensing wait time is used to Alternatively, the preceding read means 10 for accessing the memory cell means in advance by using another higher-order address to read the data information corresponding to the address and make it stand by is provided.

The first address generating means 21 used in the present invention is, for example, for generating an address for selecting the word line WL, and a plurality of different data information groups are grouped as one group. Since one address is added as, it also corresponds to the conventional concept of upper address. Also, the second address generating means 22 used in the present invention is the bit line B
An address for generating L is generated, and an address for accessing each of a group of data information consisting of a plurality of data information selected by the first address generating means 21 is generated. Therefore, it also corresponds to the conventional concept of lower address.

The first reading means 14 according to the present invention
May include the sense amplifier 6, or may include the sense amplifier 6 and the latch circuit 9. On the other hand, the second reading means 7 used in the present invention may include the sense amplifier selecting means 7.

Next, the preceding read means 10, which is one of the characteristic configurations of the present invention, receives the address information from the first address generation means 21 provided in the address buffer means 2. Means 17 having an input unit 16 for inputting and changing already stored address information based on a predetermined control signal, for example, internal address generating means 11 having an appropriate counter circuit, the internal address generating means The comparison means 12 compares the address information 11 and the address information from the first address generation means 21.

Further, the comparison means 12 in the present invention is
When the two pieces of address information match, the first read means 14 outputs a signal for reading the plurality of data information groups corresponding to the address information from the memory cell means 3 in advance. Further, the comparing means 12 is provided in the internal address generating circuit 11 for generating the predetermined control signal to the internal address generating means 11 when the both address information match.
The internal address generating means 11 is used to change the counter value of an appropriate counter circuit which is means for changing the address information.
The address of is changed.

In the present invention, when the value of the counter is changed to change the address in the internal address generating means 11, it is changed so that the address continuously increases or decreases. However, it may be randomly changed. On the other hand, it is desirable that the preceding read means 10 used in the present invention is provided with a timing control means 13 for controlling the operations of the internal address generation means 11 and the comparison means 12 in a related manner.

The timing control means 13 is
The timing of each operation of the sense amplifier 6, the latch circuit 9, and the sense amplifier selecting unit 7, which form the first reading unit 14 and the second reading unit, is also controlled. The timing control means 13 judges whether the address of the first address generation means 21 has changed, and outputs a predetermined detection signal ATD when the address has changed. It is also controlled by a detection circuit (not shown).

In the preceding read means 10 of the present invention, first, the first read means 14 is based on the one address of the internal address generation means 11.
The specific data information group read by
Utilizing a predetermined delay time until the read operation to the sense amplifier 6 in the first read means is performed, another address different from the one address is accessed in advance. It is configured like this.

Furthermore, in the present invention, when the predetermined delay time elapses, the plurality of data information groups stored in the sense amplifier 6 are transferred to the latch circuit 9.
At the same time that the latch signal for latching is output from the timing control means 13, the timing control means 13 changes the count value of the internal address generation circuit 11.

That is, according to the present invention, in order to solve the above-mentioned conventional problems, the next upper address is accessed while data is being output. Specifically, a circuit for detecting the change of the address of the first address generating means 21 is separately provided, and when the change of the address is detected, the address value is counted or added by an appropriate addition signal. Generates control signals for these circuits using a circuit that performs addition by the circuit and compares the added address with an externally input address, a latch circuit that latches the output of the sense amplifier, and predetermined timing A circuit for causing the first
When the address generating means 21 has changed, it compares the address obtained by adding in advance and, if they match, the data being accessed is latched and output.

After that, by repeating the operation of further adding the addresses of the internal address generating means 11 and starting the next access, it becomes possible to access a continuous or random address at high speed. is there. In the present invention, since the configuration as described above is adopted, regardless of the number of addresses that can be read in parallel at the same time, it has the effect of reading consecutive addresses at high speed. It is not necessary to incorporate the sense amplifier in the chip, so the chip area can be reduced.
It also has the effect of reducing the cost per bit.

The operation procedure of the semiconductor memory device 1 according to the present invention will be described below with reference to the timing chart shown in FIG. 2 and FIGS. FIG. 5 is a circuit diagram showing the initial state of the semiconductor memory device according to the present invention. At this stage, the address m from the first address generating means 21 is the comparing means 12 and the internal address generating means 11. And supplied to.

Since the internal address value does not come from the internal address generating means 11 to the comparing means 12, the comparing means 12 outputs a mismatch signal. FIG. 5 shows a state in which the comparison means 12 outputs a mismatch signal. Referring to the timing chart of FIG. 2, first, the address of the first address generating means 21 changes to m at time T1, whereby the address change detection signal ATD is output and the comparing means 12 is driven, and at the same time, At time t1, the LOAD signal is output, and at time t2, the address m of the first address generating means 21, which is an external address, is input to the internal address generating means 11 as indicated by 41. .

Therefore, referring to FIG. 6, the word line m is selected at the address m and the data information 0 to 3 contained in the word line m is read out. At the same time, as described above, at time t3, the sense waiting time S1 becomes effective, during which the processing of the data information selected by the address is temporarily interrupted.

Incidentally, the access 50 in the figure shows the timing of the data access in the preceding stage, but in this example, since it has just started, nothing is processed at the position 50. Next, at time t4, immediately before the sense waiting time S1 ends, as indicated by 51, each data information 0 to 3 read at the address m is read from the sense amplifier 6, and at time t5. When the sense waiting time S1 ends at time t6, the latch signal R1 is output at time t6, and the data information 0 to 3 stored in the sense amplifier 6 is stored in the latch circuit 9 as shown at 61. To be done.

The LOAD signal, ATD signal, sense waiting time S, latch signal and the like may be output via the timing control means 13 described above. The results up to the above procedure are shown in FIG. Next, in response to the output of the latch signal R, the addition signal A1 is output at the time t7, so that the address of the internal address generating means 11 as shown at 42 at the time t8 is, for example, It is incremented by 1 to become m + 1.

Therefore, referring to FIG. 8, the word line m + 1 is selected at the address m + 1, and the data information 4 to 7 contained in the word line m + 1 is read. During this period, the data information 0 to 3 latched in the latch circuit 9 is randomly or continuously indicated by 71 according to the address of the second address generating means 22. Is output to the output buffer 8 via.

The above relationship is shown in FIG. Next, the sense waiting time S2 becomes valid again at the time t9, during which the internal address generating means 11 operates on the memory cell means 3 from the time t10 to the time t11, that is, during the period 52 shown in the figure. Access is made at the address m + 1 and the corresponding data information 4 to 7 is read out.

After time t11, the accessed data information is read from the sense amplifier 6 as shown by 53 in FIG. After that, when the sense waiting time S2 has timed up at time t12 and the address of the external first address generation means 21 changes at time T2 to become, for example, m + 1, the address change detection means outputs the address change signal ATD. When it is output at time t13, the comparison operation is executed in the comparison means 12 in synchronization with this.

In this state, since the address m + 1 from the internal address generating means 11 has already been input to the comparing means 12, the next address m + 1 input from the first address generating means 21, which is an external address, is Since they match, the comparison means 12 outputs a match signal IC. In response to the coincidence signal IC, the latch signal R2 is output at time t14, and the data information 4 to 7 stored in the sense amplifier 6 is stored in the latch circuit 9 as shown at 62. It

The above state is shown in FIG. Then, at time t15 in response to the output of the latch signal R2.
Then, the addition signal A2 is output, so that at time t16, the address of the internal address generating means 11 is incremented by 1 for example as shown by 43 in FIG.
It becomes +2. Therefore, as shown in FIG. 10, at the address m + 2, the word line m + 2 is selected, and the data information 8-11 included in the word line m + 2 is read.

That is, the internal address generating means 11 starts the access operation in advance. During this period, each data information 3 latched by the latch circuit 9
7 to 7 are output to the output buffer 8 via the sense amplifier selecting means 7 randomly or continuously according to the address of the second address generating means 22, as shown at 72.

The above relationship is shown in FIG. next,
At time t17, the sense waiting time S3 becomes valid again, but during that time, from time t18 to time t19, that is, during the period 54 in the drawing, the internal address generating means 11 causes the memory cell means 3 to use the address m + 2. Access and read the corresponding data information 8-11.

As shown by 55 in the figure, the data information accessed at the time t immediately before the end of the sense waiting time S3 after the time t19 is read out at the address m + 2. Read from. After that, when the sense waiting time S3 has timed up at time t20 and the address of the external first address generation means 21 changes at time T3 to become, for example, m + 2, the address change detection means ATD changes the address change signal ATD.
Is output at time t21, the comparison operation is executed in the comparison means 12 in synchronization with this.

In this state, since the address m + 2 has already been input from the internal address generating means 11 to the comparing means 12, the next address m + 2 input from the first address generating means 21, which is an external address, is Since they match, the comparison means 12 outputs a match signal IC. In response to the coincidence signal IC, the latch signal R3 is output at time t23, and as shown at 63, the data information 8 to 11 stored in the sense amplifier 6 is stored in the latch circuit 9. It

The above state is shown in FIG. Then, at time t24 in response to the output of the latch signal R3.
Then, since the addition signal A3 is output, at time t25, the address of the internal address generating means 11 is advanced by, for example, 1 by m as shown at 44 in FIG.
Becomes +3, and the data information 12 to 1 included in the word line m + 3 corresponding to the address m + 3 is obtained by the same method as described above.
5 is read out and the preceding access operation is started by the internal address generating means 11.

During this time, the data information 8 to 11 latched in the latch circuit 9 are sense amplifiers randomly or continuously according to the address of the second address generating means 22, as shown at 73. It is output to the output buffer 8 via the selection means 7. The above relationship is shown in FIG. Hereinafter, the above steps will be repeated.

[0042]

According to the present invention, the sense waiting time is used to access the memory cell means in advance by using the next or another higher address, and the data information corresponding to the address is read out. It is to keep it waiting. That is, in the semiconductor memory device according to the present invention, the reading speed of the data information can be increased by executing the reading of the data information by the upper address, which takes time to access the data, in advance. is there.

Since the present invention employs the above-mentioned configuration, it has the effect of reading consecutive addresses at high speed regardless of the number of addresses that can be read simultaneously in parallel inside. Therefore, it is not necessary to incorporate a large number of sense amplifiers inside the chip, so that the chip area can be reduced and the cost per bit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a specific example of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart when the semiconductor memory device according to the present invention is used.

FIG. 3 is a block diagram illustrating a configuration example of a conventional semiconductor memory device.

FIG. 4 is a timing chart when a conventional semiconductor memory device is used.

FIG. 5 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 6 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 7 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 8 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 9 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 10 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

FIG. 11 is a block diagram illustrating an operation procedure in the semiconductor memory device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device 2 ... Address buffer means 3 ... Memory cell means 4 ... Word line selection means 5 ... Bit line selection means 6 ... Sense amplifier 7 ... Sense amplifier selection means, 2nd address generation means 8 ... Output buffer 9 ... Latch circuit 10 ... Advance reading means 11 ... Internal address generating means 12 ... Comparison means 13 ... Timing control means 14 ... First reading means 16 ... External address input section 17 ... Internal address value changing means 21 ... First address generating means 22 ... Second address generating means

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G11C 11/401

Claims (11)

[Claims] 1. At least address buffer means, memory cell means, word line selection means, bit line selection means,
Output buffer, connected to the address buffer means,
First address generating means for assigning one address to each group, with a plurality of data information as one group,
In a semiconductor memory device including second address generating means for assigning one address to each of the individual data information, one address value in the first address generating means is further used. A plurality of data information groups selected by one of the word line selection means and the bit line selection means and read out by one of the word line selection means and one address of the first address generation means. The individual data information constituting the plurality of read data information groups is read by using the address value in the second address generating means via either the bit line selecting means or the word line selecting means.
Second read means for selectively reading to the output buffer,
After reading a predetermined plurality of data information by one address in the first address generating means,
Each of the plurality of data information read by one address of the address generating means of the second address generating means is selectively read to the output buffer by each address of the second address generating means. There is provided preceding read means for reading another plurality of data information groups corresponding to the other addresses in the first address group by using the other address values in the one address generating means. A semiconductor memory device characterized by being present. 2. The semiconductor memory device according to claim 1, wherein the first address generating means generates an address for selecting a word line. 3. The semiconductor memory device according to claim 1, wherein the second address generating means generates an address for selecting a bit line. 4. The first read means is a sense amplifier,
Alternatively, the semiconductor memory device according to claim 1, further comprising a sense amplifier and a latch circuit. 5. The semiconductor memory device according to claim 1, wherein the second read means includes a sense amplifier selection means. 6. The preceding read means has an input section to which address information from the first address generation means provided in the address buffer means is input, and based on a predetermined control signal, It has internal address generating means having means for changing the stored address information, and comparing means for comparing the address information of the internal address generating means with the address information from the first address generating means. 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 7. The comparing means outputs a signal for reading the plurality of data information groups corresponding to the address information in advance by the first reading means when the both address information match. 7. The semiconductor memory device according to claim 6, wherein the semiconductor memory device is a memory device. 8. The comparing means generates the predetermined control signal to the internal address generating means and changes the address of the internal address generating circuit when the both address information match. Claim 6 characterized by the above
The semiconductor memory device described. 9. The semiconductor memory device according to claim 6, wherein the means for changing the address information stored in the internal address generating means is a counter. 10. The preceding read means is based on the one address in the internal address generation means and is based on the first address.
By utilizing a predetermined delay time until the operation of reading the specific plurality of data information groups read by the reading means of the first reading means to the sense amplifier in the first reading means. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to access another address different from the one address. 11. The timing control means outputs a latch signal for latching the plurality of data information groups stored in the sense amplifier in the latch circuit when the predetermined delay time elapses. 11. The semiconductor memory device according to any one of claims 7 to 10, wherein the count value of the internal address generation circuit is changed at the same time as the output from the.