JP4487568B2 - Data storage device, data storage control device, data storage control method, and data storage control program - Google Patents

Description

  The present invention relates to a data storage device, a data storage control device, a data storage control method, and a data storage control program that store all data in a memory composed of a plurality of memory banks and simultaneously read out a plurality of desired data from the memory.

  As shown in FIG. 15, the semiconductor memory has a structure in which a memory cell MC is accessed by designating a word line WL and a bit line BL, and is located at a position where the activated one word line intersects with the bit line. Data stored in the memory cell MC is read out.

  In the semiconductor memory having such a structure, data of a plurality of word lines share the same bit line. Therefore, when a plurality of word lines WL1 and WL2 are designated as shown in FIG. Since it is broken, data on different word lines cannot be accessed simultaneously.

  Further, data can be read from independent banks at the same time, and as shown in FIG. 17, the memory is divided into a plurality of banks BK1 to BKn, and a plurality of word lines are designated by specifying different addresses for each bank. However, data on different word lines in the bank cannot be accessed simultaneously. That is, data stored on the same word line from each bank can be read simultaneously, and data stored on different word lines in the same bank cannot be read simultaneously.

  Here, the bank means a memory unit in which a word address can be controlled independently in a memory composed of a plurality of word lines and a plurality of bit lines.

  Conventionally, processing such as pattern recognition of image data has been performed by recognizing a specific data array included in input data.

  For example, a buffer memory that can store several lines of image data and output in pixel units, a data processor that includes multiple processor elements that can process several bits of width data, and that can process data simultaneously in multiple processor elements, and matching A control information memory for storing reference data and control data, and each processor element of the data processor selects a group of image data in a matrix centered on a target pixel addressed to itself among the image data output from the buffer memory. Then, it is binarized using a threshold value, converted into target data divided into serial array bit widths that can be processed by the processor element, and it is determined whether it matches the reference data in the control information memory in the same format. (For example, refer to Patent Document 1).

JP-A-10-332378

  For example, if there is a pattern that you want to access to an image at the same time, and you want to perform a raster scan from the upper left, suppose that the data is arranged as shown in FIG. In the first five times, simultaneous access is possible. However, when the simultaneous access pattern comes to the position shown in FIG. 19, simultaneous access is impossible because bank 0 accesses a plurality of word lines. In order to access this data simultaneously, it is stored either in another bank or on the same word line. Depending on the pattern, simultaneous access may be possible if the storage location is selected appropriately. However, in order to allow simultaneous access to any pattern, the bank is divided into sections so that one bank is composed of only one word line. There is a need. However, the finer the number of banks, the larger the number of banks. As the number of banks increases, the following problems occur.

  For example, as shown in FIG. 20, if the size of the reference area is 5 pixels × 5 pixels, the required number of memory banks is 25. However, as the number of banks increases, the address management of the banks becomes difficult. There are problems such as an increase in address lines, an increase in chip area, and an increase in power consumption.

  That is, since different addresses are designated for each bank, the address bus becomes enormous.

  Further, since the number of decoders and selectors required is the same as the number of banks, the chip area increases.

  In addition, since a plurality of banks operate simultaneously, power consumption increases.

  Further, if the number of data of one word line is increased, the word line becomes longer and it takes time to access the data of one word line.

  Thus, in a semiconductor memory, if only one word line is configured per bank, data can be read simultaneously. However, if the amount of data to be stored is enormous, the hardware is burdened, which is not realistic.

  Therefore, in the conventional technique, a buffer or cache for reading data and temporarily storing it is provided, and a plurality of desired data is divided into a plurality of times in time, temporarily stored in the buffer or cache, and read.

  However, when the number of desired plural data increases and the data input / output speeds up, the data read processing is delayed in time. In order to solve this problem, the number of buffers and caches to be temporarily stored has been increased. However, if the area becomes large, a burden is imposed on hardware.

  Therefore, in view of the conventional problems as described above, the object of the present invention is to store all data in a memory composed of a plurality of memory banks without causing a burden on hardware, and to simultaneously read a desired plurality of data. An object of the present invention is to provide a data storage device, a data storage control device, a data storage control method, and a data storage control program that can be performed.

  Other objects of the present invention and specific advantages obtained by the present invention will become more apparent from the description of embodiments described below.

  In the present invention, when simultaneously accessing a plurality of data in a certain pattern for a single image, it is divided into a plurality of banks, arranged so that each data is stored in a different bank, and stored again. , Allowing simultaneous access to multiple data.

  In other words, the data storage device according to the present invention provides a desired plurality of data to be simultaneously read when the memory is composed of a plurality of memory banks and all the data is sequentially allocated and stored in the plurality of memory banks constituting the memory. Based on the access pattern indicating the data, it is determined whether or not the data to be stored is data at a position corresponding to the access pattern. By incrementing, the memory bank in which the data is to be stored is skipped, and the data at the position corresponding to the access pattern is stored in the memory bank of the incremented bank address. Sort and store all data in different memory banks Characterized in that it comprises a memory control unit.

  The data storage control device according to the present invention is a data storage control device for storing all data in a memory composed of a plurality of memory banks and simultaneously reading desired plurality of data from the memory. When sequentially allocating and storing data in a plurality of memory banks constituting a memory, data to be stored is data at a position corresponding to the access pattern based on an access pattern indicating a plurality of desired data to be simultaneously read. If the data is at the position corresponding to the access pattern, by incrementing the bank address, the memory bank where the data is to be stored is skipped, and the incremented bank address Store data at the location corresponding to the above access pattern in the memory bank. Accordingly, characterized in that it comprises a memory control means for storing in distributed to all different memory banks of data at a position corresponding to the access pattern.

  The data storage control method according to the present invention is a data storage control method for storing all data in a memory composed of a plurality of memory banks, and simultaneously reading out a plurality of desired data from the memory, wherein When sequentially allocating and storing data in a plurality of memory banks constituting a memory, data to be stored is data at a position corresponding to the access pattern based on an access pattern indicating a plurality of desired data to be simultaneously read. If the data is at the position corresponding to the access pattern, by incrementing the bank address, the memory bank where the data is to be stored is skipped, and the incremented bank address Store data at the location corresponding to the above access pattern in the memory bank. By, and storing, by distributing all different memory banks of data at a position corresponding to the access pattern.

  Furthermore, a data storage control program according to the present invention stores data in a memory composed of a plurality of memory banks, and performs data storage control for simultaneously executing data storage control for reading out a plurality of desired data from the memory by the computer. Data that is a program and is to be stored based on an access pattern indicating a plurality of desired data to be read simultaneously when all the data is sequentially allocated and stored in a plurality of memory banks constituting the memory Is the data at the position corresponding to the access pattern, and if it is the data at the position corresponding to the access pattern, by incrementing the bank address, the memory bank to store the data is determined. Skip the memory of the above incremented bank address By storing the data of the position corresponding to the access pattern to link, and storing, by distributing all different memory banks of data at a position corresponding to the access pattern.

  In the present invention, it is possible to simultaneously access a plurality of data in a certain pattern for one image. In addition, a plurality of data can be accessed simultaneously without increasing the number of banks. Furthermore, address management is easy even if data is re-stored.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Needless to say, the present invention is not limited to the following examples, and can be arbitrarily changed without departing from the gist of the present invention.

  The present invention is implemented by, for example, a data storage device 100 configured as shown in FIG.

  The data storage device 100 includes a plurality of banks of memory 10, a data storage control unit 20 that writes data to the memory 10, a read control unit 30 that reads data from the memory 10, and the memory 10. The data storage control unit 40 controls the movement of the above data, the stored data is supplied to the memory 10 and the data storage control unit 20, and the access pattern indicating the simultaneous reading of a plurality of data is the data storage control unit 20, The data read control unit 30 and the data movement control unit 40 are supplied.

  As shown in FIG. 2, the data storage control unit 20 in the data storage device 100 includes a counter 21 that counts the supplied data, and a coincidence determination unit 22 that performs a coincidence determination between the count output of the counter 21 and the access pattern. The flag generation unit 23 that generates a flag in accordance with the determination output of the match determination unit 22, the offset counter 24 that is generated by the flag generation unit 23 and counts the flag, and the bank address that is incremented by the output of the counter 21 A counter 25, a bit line address counter 26 incremented by the output of the bank address counter 25, a word line address counter 27 incremented by the output of the bit line address counter 26, and the counters 25, 26, 27 Write based on output It consists address generator 28 which generates an address output of the offset counter 24 is adapted to be supplied to the bank address counter 25 and the bit line address counter 26 as an offset value.

  Further, as shown in FIG. 3, the data read control unit 30 includes a start address extraction unit 31 that extracts a start address from the access pattern, a data read counter 32, and a bank address that is incremented by the output of the counter 32. A counter 33, a bit line address counter 34 incremented by the output of the bank address counter 33, a word line address counter 35 incremented by the output of the bit line address counter 34, and the counters 33, 34, 35 The address generation unit 36 generates a write address based on the output, and the start address obtained by the start address extraction unit 31 is given to each of the address counters 33, 34, and 35.

  Further, the data movement control unit 40 outputs the data read from the memory 10 according to the read address generated by the data read control unit 30, and writes the data to the memory 10 as movement data. As shown in FIG. 4, the inter-pattern distance calculation unit 41 that calculates the inter-pattern distance from the access pattern, and the inter-pattern distance calculated by the inter-pattern distance calculation unit 41, The transfer address calculation unit 42 generates a transfer destination address from the read address generated by the data read control unit 30.

  In the data storage device 100 having such a configuration, when simultaneously accessing a plurality of data in a certain pattern for a single image, the data storage device 100 is divided into a plurality of banks so that each data is stored in a different bank. By arranging and re-storing, multiple data can be accessed simultaneously.

  First, the arrangement of data in each bank in the data storage device 100 having such a configuration will be described.

  Here, as shown in FIG. 5, there is a case where there is a pattern corresponding to a plurality of pixels to be accessed simultaneously for a single image, and raster scanning is performed from the upper left. An access pattern corresponding to a plurality of pixels to be accessed simultaneously is not limited to the example shown in FIG.

  When storing one pixel at a time from the upper left of the image in the bank, the data storage control unit 20 increments the bank address, as shown in FIG. The bank for storing each pixel is changed. When you come to the last bank, store it in bank 1 again. The numbers in FIG. 6 represent the storage destination bank address.

  Note that the right end of a certain horizontal line and the left end one line below are considered to be continuous, and are stored in the bank in order.

  Each bank of the memory 10 has a word line address and a bit line address for each bank, and the data storage control unit 20 increments the bit line address of the bank after storing data in one bank. When the end of the bit line address is reached, the word line address is incremented.

  As shown in FIG. 7, the data storage control unit 20 sets the bank address to the value of the offset counter 24 when it comes to the location to be accessed.

  The offset counter 24 of the data storage control unit 20 counts the number of access locations, and indicates the number of access locations.

  An offset value is set in the bank address counter 25 by the offset counter 24 so that it is stored in a bank different from other access locations. Banks skipped by setting an offset value store data and increment the word line address in the bank.

  When data is stored in the bank in this way, a gap is formed in the bank skipped by the offset, as shown in FIG.

  Here, the process of storing data in each bank is performed according to the procedure shown in the flowchart of FIG. The number of banks to be prepared is the same as the number of pixels to be accessed simultaneously.

  That is, when the data to be stored is input (step S1), the data storage control unit 20 determines whether or not it is an access location by the match determination unit 22 (step S2), and the determination result is NO. If there is, the data is stored in the memory 10 at the current write address (step S3), and the process proceeds to step S8.

  If the determination result in step S2 is YES, that is, in the access location, the offset value is set in the bank address counter 25 by the offset counter 24 (step S4), and the offset counter 24 is incremented (step S4). S5) Data is stored in the memory 10 at the current write address (step S6).

  Next, the bit line address of the skipped memory bank is incremented (step S7), and the bit line address of the stored memory bank is incremented (step S8).

  Further, the data storage control unit 20 determines whether all data has been input (step S9).

  The data storage control unit determines whether or not the bit line address has returned to the beginning when the determination result in step S9 is NO (step S10), and when the determination result is NO, step S12. If the decision result in the step S10 is YES, the word line address is incremented (step S11), the bank address is incremented (step S12), and the process returns to the step S1 to return to the step S1. From step S12, the process of storing all data is performed by repeating the process of step S12. When the determination result in step S9 is YES, the storage process ends.

  Next, an access method and data re-storage will be described.

  In this data storage device 100, as shown in FIG. 10, [0, 0, 0], [1, 0, 5] as addresses [bank address, word line address, bit line address] where a plurality of addresses are to be simultaneously accessed first. , [2, 0, 9], [3, 1, 0], [4, 1, 4], the respective data are stored in different banks, so that simultaneous access is possible.

  Here, when one adjacent pixel is accessed by raster scan, each pixel is stored in the memory bank in order, so that the bank address may be incremented by one as shown in FIG. When the bank address returns to the beginning, the bit line address is incremented by one. When the bit line address returns to the beginning, the word line address is incremented by one.

  In order for this rule to always allow simultaneous access, the offset entered where it is desired is returned. Returning the offset is to store it again in the memory bank that was skipped by the offset where it was supposed to be stored when it was not where you wanted to access it. When storing data, the memory bank skipped by the offset increments the bit line address because it is stored, so nothing is stored at that address.

  Therefore, data can be stored again at that address.

  The address where the data is stored again can be obtained from the pixel interval between the address currently accessed and the previous access destination spatially and the total number of banks.

  That is, as shown in FIG. 12, the currently accessed address is [bank address b, word line address i, bit line address j], the pixel interval from the previous access destination is d, and the number of banks is n. Then, the destination bank address B is expressed by the following equation (1).

B = (d + b−1) mod n (1)
Here, the destination word line address I and the destination bit line address J are
I = i, J = j.
It is.

  However, since the destination bank address B moves in a direction that becomes smaller than b, if B−b> 0, the destination bit line address J becomes J = j−1. When the bit line address returns to the end, the destination word line address I becomes I = i-1. In other cases, the destination word line address I is I = i.

  As shown in FIG. 13, the data is re-stored by moving the data at the address [1, 0, 5] to the address [0, 0, 5] and the data at the address [2, 0, 9] to the address [1. , 0, 9], the data at address [3, 1, 0] is moved to address [1, 1, 0], and the data at address [4, 1, 4] is moved to address [0, 1, 4]. ] To move to.

  In this data storage device 100, data access and re-storing processes are performed according to the procedure shown in the flowchart of FIG.

  That is, the data read control unit 30 first sets the read address [b, i, j] in the first access location (step S21), and the data movement control unit 40 uses the inter-pattern distance calculation unit 41 to access the access location. Is determined (step S22).

  Next, the data read control unit 30 reads the data of the read address [b, i, j] from the memory 10 (step S23), and the data movement control unit 40 uses the destination address calculation unit 42 to read the read address. From [b, i, j], the destination address [B, I, J] is calculated by the above equation (1) (step S24).

  Next, the destination address calculation unit 42 determines whether the destination bank address B is larger than the read bank address b (step S25). If the determination result is YES, the destination bit line address J Is set to J = j-1 (step S26). If the determination result in step S25 is NO, the destination bit line address J is set to J = j (step S27).

  Further, the destination address calculation unit 42 determines whether or not the destination bit line address J has returned last (step S28). If the determination result is YES, the destination word line address I is set to I = i. −1 (step S29), and if the determination result in step S28 is NO, the destination word line address I is set to I = i (step S30).

  Then, the data movement control unit 40 writes the data of the read address [b, i, j] read from the memory 10 to the destination address [B, I, J] of the memory 10 (step S31).

  When the data movement control unit 40 finishes moving the data at one access location on the memory 10 in this way, the data read control unit 30 determines whether or not the processing of all the pixels has been completed. (Step S32).

  If the determination result in step S32 is NO, the data read control unit 30 increments the bank address [b] of the read address [b, i, j] (step S33), and the bank address [b] It is determined whether or not the operation has returned to the beginning (step S34).

  If the determination result in step S34 is NO, the data read control unit 30 proceeds to the process of step S36, and if the determination result in step S34 is YES, the read address [b, i, j ] Is incremented (step S35), and it is determined whether or not the bit line address [j] has returned to the beginning (step S36).

  The data read control unit 30 returns to step S23 if the determination result in step S36 is NO, and reads the address [b, i, j] if the determination result in step S36 is YES. Is incremented (step S37), the process returns to step S23, and the processing from step S23 to step S37 is repeated, whereby the data at each access location is sequentially read out on the memory 10. When the result of the determination is YES in step S32, the data access and re-store processing is terminated.

  If the offset is returned, simultaneous access is possible by incrementing the bank address, so there is no need to store the address of the re-storing destination.

  In the data storage device 100, the data storage control unit 20, the data read control unit 30, and the data movement control unit 40 are configured by, for example, a microprocessor, according to a data storage control program stored in a program memory (not shown). Storage of all data, simultaneous reading of a plurality of data, and re-storage control can also be performed.

It is a block diagram which shows the structure of the data storage apparatus which implements this invention. It is a block diagram which shows the structure of the data storage control part in the said data storage apparatus. It is a block diagram which shows the structure of the data reading control part in the said data storage apparatus. It is a block diagram which shows the structure of the data movement control part in the said data storage apparatus. It is a figure which shows typically the example of the pattern corresponding to the pixel which wants to access simultaneously with respect to a certain one image. It is a figure which shows typically the state which incremented the bank address and was stored in the bank pixel by pixel from the upper left of the image. It is a figure which shows typically the state which incremented the bank address in the location to access. It is a figure which shows typically the state in which the gap was made in the bank skipped by the increment of a bank address. It is a flowchart which shows the procedure of the process which stores data in each bank. It is a figure which shows typically the first several simultaneous access state in the said data storage device. It is a figure which shows typically the state when accessing one adjacent pixel by a raster scan. It is a figure used for description for calculating | requiring the address | destination which stores data again. It is a figure which shows the data re-storing state typically. It is a flowchart which shows the procedure of the process of data access in the said data storage device, and a re-store. It is a figure which shows typically the structure of a general semiconductor memory. It is a figure which shows typically the state which cannot access simultaneously in the said semiconductor memory. It is a figure which shows the memory structure of a several memory bank. It is a figure which shows typically the storage state to the memory in case there exists a pattern which wants to access simultaneously with respect to a certain image, and it carries out a raster scan from the upper left. It is a figure which shows typically the state which became impossible to access simultaneously. It is a figure which shows typically the state which increased the number of memory banks and enabled simultaneous access so that the inside of a reference area could be accessed.

Explanation of symbols

  10 memory, 20 data storage control unit, 21 counter, 22 match determination unit, 23 flag generation unit, 24 offset counter, 25 bank address counter, 26 bit line address counter, 27 word line address counter, 28 address generation unit, 30 data Read control unit, 31 start address extraction unit, 32 counter, 33 bank address counter, 34 bit line address counter, 35 word line address counter, 36 address generation unit, 40 data movement control unit, 41 inter-pattern distance calculation unit, 42 movement Address calculation unit, 100 data storage device

Claims (12)

A memory consisting of a plurality of memory banks;
When all the data is sequentially sorted and stored in the plurality of memory banks constituting the memory, the data to be stored corresponds to the access pattern based on the access pattern indicating the desired plurality of data to be read simultaneously. If the data is at the position corresponding to the access pattern, the bank address is incremented to skip the memory bank where the data is to be stored, and the data is incremented. A memory control means for storing all data at positions corresponding to the access pattern in different memory banks by storing the data at positions corresponding to the access pattern in the memory bank of the bank address. Data storage device.   The memory control means simultaneously reads out a plurality of desired data from the memory in accordance with a plurality of first addresses indicated by the access pattern, and increments the bank address to thereby store the address where the data was not stored. 2. The data storage device according to claim 1, wherein the plurality of read-out data are stored again at a second address indicating, and the plurality of read-out data in subsequent access are stored at the first address. In the memory control means, the accessed address is [bank address b, word line address i, bit line address j], the pixel interval from the previous access destination is d, the number of banks is n,
B = (d + b−1) mod n
I = i
J = j
When Bb> 0, the destination bit line address J becomes J = j−1. When the bit line address returns to the end, the destination word line address I becomes I = i−. 1; otherwise, each storage in each memory bank indicated by a destination address [destination bank address B, destination word line address I, destination bit line address J] where destination word line address I becomes I = i 2. The data storage device according to claim 1, wherein the data is stored again in the place. A data storage control device that stores all data in a memory composed of a plurality of memory banks and simultaneously reads a desired plurality of data from the memory,
When all the data is sequentially sorted and stored in a plurality of memory banks constituting the memory, the data to be stored is changed to the access pattern based on an access pattern indicating a plurality of desired data to be read simultaneously. It is determined whether or not the data is at the corresponding position. If the data is at the position corresponding to the access pattern, the memory address to store the data is skipped by incrementing the bank address, and the increment is performed. Memory control means is provided for storing the data at the position corresponding to the access pattern in the memory bank of the designated bank address, so that the data at the position corresponding to the access pattern is allotted and stored in different memory banks. A data storage control device.   The memory control means simultaneously reads out a plurality of desired data from the memory in accordance with a plurality of first addresses indicated by the access pattern, and increments the bank address to thereby store the address where the data was not stored. 5. The data storage control device according to claim 4, wherein the plurality of read-out data are stored again at a second address indicating, and the plurality of data read out in subsequent access are stored at the first address. In the memory control means, the accessed address is [bank address b, word line address i, bit line address j], the pixel interval from the previous access destination is d, the number of banks is n,
B = (d + b−1) mod n
I = i
J = j
When Bb> 0, the destination bit line address J becomes J = j−1. When the bit line address returns to the end, the destination word line address I becomes I = i−. 1; otherwise, each storage in each memory bank indicated by a destination address [destination bank address B, destination word line address I, destination bit line address J] where destination word line address I becomes I = i 5. The data storage control device according to claim 4, wherein the data is stored again in the place. A data storage control method for storing all data in a memory composed of a plurality of memory banks and simultaneously reading desired plural data from the memory,
When sequentially sorting and storing all the data in a plurality of memory banks constituting the memory,
Based on an access pattern indicating a plurality of desired data to be read simultaneously, it is determined whether or not the data to be stored is data at a position corresponding to the access pattern,
In the case of data at a position corresponding to the access pattern, by incrementing the bank address, the memory bank to store the data is skipped, and the memory bank of the incremented bank address corresponds to the access pattern. A data storage control method, wherein by storing position data, all position data corresponding to the detection pattern is distributed and stored in different memory banks. Simultaneously reading a plurality of desired data indicated by the access pattern from the memory,
Re-store the read multiple data in each storage location of each memory bank emptied by the above bank address increment,
8. The data storage control method according to claim 7, wherein a plurality of data read for each access is stored again in each storage location of each memory bank that has already been stored again by the above-mentioned storage. The address being accessed is [bank address b, word line address i, bit line address j], the pixel interval from the previous access destination is d, and the number of banks is n.
B = (d + b−1) mod n
I = i
J = j
When Bb> 0, the destination bit line address J becomes J = j−1. When the bit line address returns to the end, the destination word line address I becomes I = i−. 1; otherwise, each storage in each memory bank indicated by a destination address [destination bank address B, destination word line address I, destination bit line address J] where destination word line address I becomes I = i 8. The data storage control method according to claim 7, wherein the data is stored again in the place. A data storage control program for executing, by a computer, data storage control for storing all data in a memory composed of a plurality of memory banks and simultaneously reading desired multiple data from the memory,
When sequentially sorting and storing all the data in a plurality of memory banks constituting the memory,
Based on an access pattern indicating a plurality of desired data to be read simultaneously, it is determined whether or not the data to be stored is data at a position corresponding to the access pattern,
In the case of data at a position corresponding to the access pattern, by incrementing the bank address, the memory bank to store the data is skipped, and the memory bank of the incremented bank address corresponds to the access pattern. A data storage control program characterized in that by storing location data, all location data corresponding to the access pattern is distributed and stored in different memory banks. Simultaneously reading a plurality of desired data indicated by the access pattern from the memory,
Re-store the read multiple data in each storage location of each memory bank emptied by the above bank address increment,
11. The data storage control program according to claim 10, wherein a plurality of data read for each access is stored again in each storage location of each memory bank that has already been stored again by the above-mentioned storage. The address being accessed is [bank address b, word line address i, bit line address j], the pixel interval from the previous access destination is d, and the number of banks is n.
B = (d + b−1) mod n
I = i
J = j
When Bb> 0, the destination bit line address J becomes J = j−1. When the bit line address returns to the end, the destination word line address I becomes I = i−. 1; otherwise, each storage in each bank memory indicated by a destination address [destination bank address B, destination word line address I, destination bit line address J] where destination word line address I becomes I = i The data storage control program according to claim 10, wherein the data is stored again in the place.

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