JP4655220B2 - DESIGN DEVICE AND METHOD, AND DATA STORAGE DEVICE - Google Patents

Description

  The present invention relates to a design apparatus and method, and a data storage apparatus, and in particular, a design apparatus and a design apparatus that can store all data in a memory composed of a plurality of memory banks and simultaneously read a desired plurality of data. The present invention relates to a method and a data storage device.

  As shown in the example of FIG. 1, the semiconductor memory MY has a structure in which the word line WL and the bit line BL are designated to access the memory cell MC, and the designated one word line WL and the bit line BL intersect. Data stored in the memory cell MC at the position to be read is read out.

  In the semiconductor memory MY having such a structure, a plurality of word lines WL share the same bit line BL. Therefore, as shown in the example of FIG. 2, for example, when two word lines WL1 and WL2 are designated, the data of these word lines W11 and WL2 are mixedly output on the bit line BL. Cannot be accessed simultaneously.

  On the other hand, data can be read simultaneously from independent memory banks. As shown in the example of FIG. 3, the semiconductor memory MY is divided into n memory banks BK0 to BKn-1, and each memory bank BK0 to By specifying different addresses for BKn−1, data on a plurality of word lines WL can be accessed simultaneously, but data on different word lines WL in the memory bank cannot be accessed simultaneously. That is, data that can be read simultaneously is data stored on the same word line from each memory bank, and data stored on different word lines in the same memory bank cannot be read simultaneously.

  Here, the memory bank refers to a memory unit having a single word address selected in a memory composed of a plurality of word lines and a plurality of bit lines.

  Conventionally, for example, processing such as pattern recognition of image data and processing such as motion detection have been performed by recognizing a specific data array included in input data. For example, a buffer memory that can store several lines of image data and output in pixel units, a data processor that includes multiple processor elements that can process several bits of width data, and that can process data simultaneously in multiple processor elements, and matching A control information memory for storing reference data and control data, and each processor element of the data processor selects a group of image data in a matrix centered on a target pixel addressed to itself among the image data output from the buffer memory. Then, it is binarized using a threshold value, converted into target data divided into serial array bit widths that can be processed by the processor element, and it is determined whether it matches the reference data in the control information memory in the same format. (For example, refer to Patent Document 1).

  Also, in the field of moving image processing, motion, that is, the motion direction and size (or speed) of an object in a temporally different image is used. For example, a motion compensation frame in high-efficiency encoding of an image Motion is used for inter-coding, parameter control by motion in a television noise reduction device using an inter-frame time domain filter, and the like. A block matching method is known as a motion detection method for obtaining motion.

  In the motion detection method for detecting motion in an image signal, the applicant of the present application generates (a) an integrated value table by a matching method for each relatively large block obtained by dividing the entire screen or a screen into a plurality of blocks. A step of extracting one or a plurality of candidate vectors for each relatively large block obtained by dividing the entire one screen or a plurality of one screen by using an integrated value table; and (b) matching only for the candidate vectors. A two-step motion detection method has been proposed which includes a step of detecting a motion vector for each pixel or each relatively small block. In this two-step motion detection method, any two or more pixel data in the image are simultaneously read out in the two-step process of representative point matching and vector assignment in which the motion detection of the image is performed by the two-step representative point matching. There is a need (see, for example, Patent Document 2).

JP 2003-203236 A JP 2001-61152 A

  By the way, as shown in the example of FIG. 4, when there are four pixels to be simultaneously accessed (hereinafter also referred to as access candidate pixels) with respect to a predetermined image composed of pixel rows extending in the horizontal or vertical direction. The minimum necessary number of memory banks for storing a desired plurality of pixels in another memory bank is 4. In the example of FIG. 4, a circle indicates one pixel, and a black circle indicates an access candidate pixel.

  If there is a vertical (h pixel) × horizontal (w pixel) search area SR on this image, and there are n candidates to be arbitrarily accessed, the type is (h × w) C (n There are pieces. Each of these is called an access pattern. As an access pattern, a combination of any number of access candidates in the search area SR is possible. That is, the four pixels shown in FIG. 4 show an example of one access pattern in 16 × 8C4 combinations.

  Here, the search area SR moves one pixel at a time in the raster scan order, and accordingly, the access pattern access candidate pixels also move in the raster scan order, and the moved position becomes the access candidate pixel. Consider the case of acquiring data simultaneously.

  In this case, in the initial arrangement, it is necessary to devise a method for storing data other than the access candidate pixels of the access pattern. For example, the pixel data between the access candidate pixels of this image may be stored in four memory banks in the raster scan order for each pixel as shown in the example of FIG. 5, or as shown in the example of FIG. As described above, it is necessary to store data between access candidate pixels in the same memory bank.

  In the examples of FIGS. 5 and 6, the numbers attached to the circles indicate the four memory banks BK <b> 0 to BK <b> 3 in which the data of each pixel is stored. A black circle with a white numeral indicates an access candidate pixel, and indicates that data is stored in the memory bank indicated by the white numeral.

  In the example of FIG. 5, the data of each pixel is stored in the memory bank BK0, the memory bank BK1, the memory bank BK2, and the memory bank BK3 for each pixel in the raster scan order from the pixel data of the upper left pixel. That is, the data of the first access candidate pixel from the upper left pixel in the raster scan order is stored in the memory bank BK1, and the data of the second access candidate pixel is stored in the memory bank BK0, and the third access candidate. The pixel data is stored in the memory bank BK2, and the fourth access candidate pixel data is stored in the memory bank BK3.

  By storing in this way, when the search area SR moves one pixel at a time in the raster scan order, each access candidate pixel also moves one pixel at a time. For example, the first access candidate from the upper left pixel in the raster scan order , The data is moved to the pixel stored in the memory bank BK2, the second access candidate is moved to the pixel where the data is stored in the memory bank BK1, and the third access candidate is transferred to the memory bank BK3. Since the data of the pixel of the fourth access candidate is moved to the pixel in which the data is stored in the memory bank BK0, the search area SR is moved one pixel at a time in the raster scan order. Even if it moves, it is possible to simultaneously acquire the data of access candidate pixels.

  In the example of FIG. 6, data from the first access candidate pixel to the pixel immediately before the second access candidate from the upper left pixel in raster scan order is stored in the memory bank BK0. Data from the access candidate pixel to the pixel immediately before the third access candidate is stored in the memory bank BK1, and the data from the third access candidate pixel to the pixel immediately before the fourth access candidate is stored. Data is stored in the memory bank BK2, and data of the subsequent pixels from the fourth access candidate pixel is stored in the memory bank BK3.

  By storing in this way, when the search area SR moves one pixel at a time in the raster scan order, even if each access candidate pixel also moves one pixel at a time, a certain interval is a memory bank in which data is stored. Therefore, the data of the access candidate pixels can be acquired simultaneously. However, as shown in the example of FIG. 7, when the movement of the search area SR exceeds the access candidates before the movement of the search area SR shown in FIG. 6, the pixels in the same memory bank are accessed simultaneously. Become.

  In the example of FIG. 7, the access candidate pixels after the search area SR has moved 7 pixels in the raster scan order from the example of FIG. 6 are indicated by black circles. Corresponding to the movement of the search area SR by 7 pixels in the raster scan order, the first access candidate from the upper left pixel in the raster scan order moves to the pixel in which the data is stored in the memory bank BK1, and the second access The candidate moves to the pixel whose data is stored in the memory bank BK1, the third access candidate moves to the pixel whose data is stored in the memory bank BK2, and the data of the pixel of the fourth access candidate is , The data moves to the pixel stored in the memory bank BK3.

  That is, the number of pixels 7 that the search area SR has moved to becomes the number 7 of pixels between the first and second access candidates before the movement of the search area SR, and the first and second access candidates are both Since the data moves to the pixels stored in the memory bank BK1, the data in the same memory bank BK1 is accessed at the same time.

  In general, a plurality of data can be accessed at the same time either in a plurality of data stored in different memory banks or in a plurality of data stored on the same word line. Depending on the pattern, simultaneous access may be possible if the storage location is selected appropriately. However, in order to allow simultaneous access to any pattern, the memory bank is configured so that one memory bank consists of only one word line. It is necessary to divide.

  However, the smaller the number of banks, the larger the number of banks. When the number of memory banks increases, (a) the address bus becomes enormous because different addresses are designated for each bank, and (b) the decoder and selector have the number of memory banks. (C) Power consumption increases because a plurality of memory banks operate simultaneously. (D) When the number of data for one word line is increased, the word line becomes longer. There was a fear that it would take time to access the data.

  As described above, in a semiconductor memory, data can be read simultaneously if it is configured with only one word line per memory bank. However, if the amount of data to be stored becomes enormous, the hardware is burdened, which is not practical.

  Therefore, in the conventional technique, a buffer or cache for reading data and temporarily storing it is provided, and a plurality of desired data is divided into a plurality of times in time, temporarily stored in the buffer or cache, and read.

  However, when the number of desired plural data increases and the data input / output speeds up, the data read processing is delayed in time. In order to solve this problem, the number of buffers and caches to be temporarily stored has been increased. However, if the area becomes large, a burden is imposed on hardware.

  The present invention has been made in view of such a situation, and stores all data in a memory composed of a plurality of memory banks and simultaneously reads a desired plurality of data without causing a burden on hardware. To be able to do that.

According to a first aspect of the present invention, there is provided a design apparatus that designs parameters of a data storage device that reads data at the same time by distributing data to a plurality of memory banks constituting a memory and storing the data. access pattern showing a plurality of desired data to be horizontal size and the multiplication result of the vertical size of the accessible area at a time of the data, the number of the plurality of candidate memory banks to be set candidates, be read simultaneously Divided by the addition result obtained by adding 1 to the difference in the number of access candidates constituting the storage pixel, and the storage pixel number calculation means for calculating the maximum number of pixels stored in one memory bank and the storage pixel number calculation means the multiplication result between 1 minus from said maximum the plurality of candidate memory bank number and number of pixels that have been, multiplication of the horizontal size and the vertical size of the data From the addition result obtained by adding the results, the maximum number of pixels and the plurality of candidates from the memory bank number of a value obtained by subtracting the number of the access candidates multiplication result, and subtracting the value minus 1. from the number of the access candidates And a memory amount calculating means for calculating a memory amount necessary for the memory, and a memory bank in which the data is distributed and stored by the data storage device according to the memory amount calculated by the memory amount calculating means. Bank number setting means for setting the number.

According to a first aspect of the present invention, there is provided a design apparatus for designing a parameter of a data storage device that reads a plurality of data at the same time by allocating data to a plurality of memory banks constituting a memory and storing the data. access pattern showing a plurality of desired data to be horizontal size and the multiplication result of the vertical size of the accessible area at a time of the data, the number of the plurality of candidate memory banks to be set candidates, be read simultaneously The maximum number of pixels to be stored in one memory bank is calculated by dividing the difference of the number of access candidates constituting the number by the addition result obtained by adding 1, and the calculated maximum number of pixels and the plurality of candidate memory banks the multiplication result between 1 minus a few, the addition results obtained by adding the multiplication result between the horizontal size and the vertical size of the data, said plurality of climate and the maximum number of pixels Multiplication result between the value obtained by subtracting the number of the access candidates from the number of memory banks, and by subtracting the value minus 1. from the number of the access candidate, calculates the amount of memory required for the memory, the calculated the The method includes a step of setting the number of memory banks in which the data is distributed and stored by the data storage device according to the amount of memory.

A data storage device according to a second aspect of the present invention is a data storage device that stores data by allocating data to a plurality of memory banks constituting a memory, thereby simultaneously reading out a plurality of data, wherein the horizontal size of the data and the data vertical size and the result of the multiplication, and a plurality of candidate number memory banks to be set candidates, access candidates for configuring the access pattern showing a plurality of desired data to be read simultaneously in the accessible area once among The maximum number of pixels stored in one memory bank is calculated by dividing by the addition result obtained by adding 1 to the number difference, and the calculated maximum pixel number and the value obtained by subtracting 1 from the plurality of candidate memory banks multiplication result from the addition result obtained by adding the multiplication result between the horizontal size and the vertical size of the data, the plurality of candidate number memory bank and the maximum number of pixels of the Multiplication result between the value obtained by subtracting the number of al the access candidate, and by subtracting the value minus 1. from the number of the access candidate, the calculated amount of memory required, set in accordance with the memory amount calculated A memory composed of a predetermined number of memory banks, and when storing the data in the set number of memory banks, the data between the access candidates is stored based on the access pattern and the maximum number of pixels. Data storage processing means for initial placement by storing the same number of pixels in the same memory bank, and for data initially placed on a memory composed of the set number of memory banks, pixel data is stored from each memory bank. Data read storage processing means for reading out each of the data, and the data read storage processing means for reading out pixel data from the memory bank. Read out to a memory bank in which data of pixels in one adjacent range determined based on the moving direction of the access pattern out of the range determined based on each position of the access candidate of the access pattern is read Stores pixel data.

In the first aspect of the present invention, the horizontal size of the data stored in the data storage device that reads the plurality of data at the same time by storing the data distributed and stored in the plurality of memory banks constituting the memory , access to configure the multiplication result of the vertical size of the accessible area at a time of the data, a plurality of candidate number memory banks to be set candidates, the desired access pattern showing a plurality data to be read simultaneously The maximum number of pixels stored in one memory bank is calculated by dividing by the addition result obtained by adding 1 to the difference in the number of candidates. Then, from the addition result obtained by adding the multiplication result of the calculated maximum pixel count and the value obtained by subtracting 1 from the plurality of candidate memory banks, and the multiplication result of the horizontal size and vertical size of the data , the maximum pixel The amount of memory required for the memory is calculated by subtracting the value obtained by subtracting the number obtained by subtracting the number of access candidates from the number of candidate memory banks and the value obtained by subtracting 1 from the number of access candidates. In accordance with the calculated amount of memory, the data storage device sets the number of memory banks in which the data is distributed and stored.

In the second aspect of the present invention, the multiplication result of the horizontal size of the data and the vertical size of the area that can be accessed at once is read simultaneously with the number of candidate memory banks as setting candidates. The maximum number of pixels stored in one memory bank is calculated by dividing by the addition result obtained by adding 1 to the difference in the number of access candidates constituting an access pattern indicating desired multiple data to be output. the multiplication result of 1 and minus from said maximum the plurality of candidate memory bank number and the number of pixels, the addition result obtained by adding the multiplication result between the horizontal size and the vertical size of the data, the maximum number of pixels as the plurality were multiplication result from the candidate memory bank number of a value obtained by subtracting the number of the access candidate, and by subtracting the value minus 1. from the number of the access candidate, the amount of memory required is calculated Based on the access pattern and the maximum number of pixels, when the data is distributed and stored in a memory bank of a memory having a number of memory banks set according to the calculated memory amount, Are stored in the same memory bank by the maximum number of pixels. Further, pixel data is read from each memory bank with respect to data initially arranged on the memory including the set number of memory banks. Then, pixel data is read from the memory bank, and data of pixels in one adjacent range determined based on the movement direction of the access pattern out of the range determined based on each position of the access pattern access candidate The pixel data read out is stored in the memory bank in which is stored.

  According to the first aspect of the present invention, the memory capacity of the data storage device can be reduced as a whole.

  According to the second aspect of the present invention, it is possible to reduce the amount of memory as a whole and to simultaneously access a desired plurality of pixels in all data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 8 shows a configuration example of a data storage device to which the present invention is applied.

  The data storage device 11 includes input terminals 21a to 21c, an output terminal 21b, a memory 31, a data storage control unit 32, and a data read / storage control unit 33.

  Data DA such as an image to be stored is supplied from the input terminal 21a to the memory 31 and the data storage control unit 32, and an access pattern AP indicating a position to be simultaneously read out of a plurality of data is input from the input terminal 21b to the data storage control unit 32. The control signal CS for operation control is supplied from the control device (not shown) to the memory 31, the data storage control unit 32, and the data read / store control unit 33 via the input terminal 21c.

  The memory 31, the data storage control unit 32, and the data read / storage control unit 33 operate based on a control signal CS input via the input terminal 21c.

  Data of an image to be stored is input to the memory 31 from the input terminal 21a at the time of initial storage. The memory 31 includes a plurality of memory banks (for example, four memory banks BK0 to BK3).

  Based on the access pattern AP from the input terminal 21c, the data storage control unit 32 performs an initial arrangement process of arranging (storing) the data DA input from the input terminal 21a in the memory 31. That is, the data storage control unit 32 generates a write address indicating a position where the data DA input from the input terminal 21 a is stored in the memory 31 based on the access pattern AP from the input terminal 21 c, and is input to the memory 31. Data is written to the address of the memory 31 indicated by the write address.

  The data read / store control unit 33 generates a read address based on the address from the memory 31, reads data from the memory 31, generates a write address, and controls re-storing of pixels in the memory 31. I do.

  FIG. 9 is a diagram illustrating a configuration example of the data storage control unit 32 of FIG.

  The data storage control unit 32 includes a counter 41, a match determination unit 42, a flag generation unit 43, a bank address counter 44, a bit line address counter 45, a word line address counter 46, an address generation unit 47, and a storage control processing unit 48. Is done.

  The counter 41 counts the data DA supplied from the input terminal 21 a and outputs the count result to the coincidence determination unit 42 and the bank address counter 44. The coincidence determination unit 42 performs coincidence determination between the access pattern AP from the input terminal 21 b and the count result of the counter 41, and outputs the determination result to the flag generation unit 43. Although illustration is omitted, the determination result is also output to the address generation unit 47.

  The flag generation unit 43 generates a flag according to the determination result from the coincidence determination unit 42, and outputs the generated flag to the bank address counter 44, the bit line address counter 45, and the word line address counter 46.

  The bank address counter 44 is a counter whose count value is incremented according to the flag from the flag generation unit 43, and outputs the count value to the address generation unit 47. The count value of the bank address counter 44 indicates a bank address representing a memory bank number. Further, the bank address counter 44 receives the count result of the counter 41 and outputs the result to the bit line address counter 45.

  The bit line address counter 45 is a counter in which the count value is incremented in response to the result of the bank address counter 44, and outputs the count value to the address generation unit 47. Further, the bit line address counter 45 resets the count value according to the flag from the flag generation unit 43. The bit line address counter 45 stores the bit line length. When the counter value exceeds the bit line length, the count value is reset and the result is output to the word line address counter 46.

  The word line address counter 46 is a counter in which the count value is incremented in response to the result of the bit line address counter 45, and outputs the count value to the address generation unit 47. The word line address counter 46 resets the count value in accordance with the flag from the flag generation unit 43.

  The address generation unit 47 generates the write address WA based on the count values indicated by the bank address counter 44, the bit line address counter 45, and the word line address counter 46 according to the determination result from the match determination unit 42, The data is output to the storage control processing unit 48.

  The storage control processing unit 48 controls writing to the memory 31 using the write address WA. That is, the data DA delayed for a predetermined time by a delay unit (not shown) is stored at the address of the memory 31 indicated by the write address WA by the storage control processing unit 48.

  FIG. 10 is a diagram illustrating a configuration example of the data read / store control unit 33 of FIG. In the example of FIG. 10, a case where the memory 31 is configured by four memory banks (BK0 to BK3) is shown.

  The data read / store control unit 33 includes data read / store control units 53-0 to 53-3 for the memory banks BK0 to BK3. The data read / storage control units 53-0 to 53-3 include data read bit line address counters 51-0 to 51-3, word line address counters 52-0 to 52-3, and data storage bit lines, respectively. Address counters 53-0 to 53-3, word line address counters 54-0 to 54-3, read address generation units 55-0 to 55-3 for generating read addresses, and write address generation unit 56- for generating write addresses 0 to 56-3, read control processing units 57-0 to 57-3 for performing read control processing, and write control processing units 58-0 to 58-3 for performing write control processing.

  Hereinafter, data read bit line address counters 51-0 to 51-3, word line address counters 52-0 to 52-3, data storage bit line address counters 53-0 to 53-3, word lines Address counters 54-0 to 54-3, read address generation units 55-0 to 55-3, write address generation units 56-0 to 56-3, read control processing units 57-0 to 57-3, and write control processing When it is not necessary to distinguish the units 58-0 to 58-3, the read bit line address counter 51, the read word line address counter 52, the write bit line address counter 53, the write word line address counter 54, and the read address generation unit, respectively. 55, a write address generation unit 56, a read control processing unit 57 And appropriately referred to as a write control processing unit 58.

  For example, the last read address (Last RA) of each memory bank BK read from the memory 31 is input to the read bit line address counter 51.

  The read bit line address counter 51 receives the final read address of each memory bank BK and increments the count value according to the read. The bit line length is stored in the read bit line address counter 51. When the count value exceeds the bit line length, the count value is reset to 0, and the result is output to the read word line address counter 52. Is done.

  The read word line address counter 52 receives the count value of the read bit line address counter 51, and appropriately increments the count value according to the read. The read word line address counter 52 stores the word line length, and when the count value exceeds the word line length, the count value is reset to zero.

  The read address generation unit 55 generates a read address RA based on the bank address of each memory bank BK and the count values of the read bit line address counter 51 and the read word line address counter 52 and outputs the read address RA to the read control processing unit 57. To do. The read control processing unit 57 reads data corresponding to the read address RA from the read address generation unit 55 from the memory 31.

  On the other hand, for example, the last write address (Last WA) of each memory bank BK read from the memory 31 is input to the write bit line address counter 53.

  The write bit line address counter 53 receives the final write address of each memory bank BK and increments the count value according to the write. The bit line length is stored in the write bit line address counter 53. When the count value exceeds the bit line length, the count value is reset to 0, and the result is output to the write word line address counter 54. Is done.

  The write word line address counter 54 receives the result of the write bit line address counter 53 and appropriately increments the count value according to the write. The write word line address counter 54 stores the word line length, and when the count value exceeds the word line length, the count value is reset to zero.

  The write address generator 56 generates a write address WA based on the bank address of each memory bank BK, the write bit line address counter 53 and the count value of the write word line address counter 54, and outputs the write address WA to the write control processor 58. The write control processing unit 58 writes data read from another memory bank (for example, the next memory bank) to a predetermined position in the memory 31 indicated by the write address WA from the write control processing unit 58.

  In the example of FIG. 10, the final read address and the final write address are read from the memory 31. However, the present invention is not limited to this, and is stored in the data read storage control unit 33 and read from there. It may be.

  In the example of FIG. 10, a read bit line and word line address counter is provided for each memory bank. However, when reading each memory bank, the count values indicated by the bit line and word line address counter are the same. Therefore, these may be shared as appropriate. Further, the data read from the next memory bank is written to the memory bank. If the data read from the memory bank BK0 is necessary again, the data is read from the memory bank BK0. The data may be set to be written to the memory bank BK3.

  Next, an initial arrangement of image data in each bank in the data storage device 11 having such a configuration will be described.

  FIG. 11 is a diagram illustrating an example of an access pattern.

  In the example of FIG. 11, an image composed of 40 vertical pixels × 80 horizontal pixels (H × W) is shown, and among the images, an area of 8 vertical pixels × 16 horizontal pixels (h × w) The data storage device 11 is shown as a search area SR that is an area that can be accessed at one time.

  That is, when it is desired to simultaneously access a plurality of pixels with respect to this image, for example, an access pattern AP that is a pattern indicating the positions of a plurality of pixels that are desired to be simultaneously accessed is set in the search area SR. Along with the movement of the search area SR that moves pixel by pixel, the access pattern AP also moves, so that a plurality of pixels are simultaneously accessed in all areas in the image.

  In the example of FIG. 11, the pixels in the search area SR are enlarged, the circle shown in the search area SR represents one pixel, and the black circle is a plurality of pixels in the search area SR. The pixels (hereinafter also referred to as access candidates) P0 to P3 that are desired to be accessed simultaneously are shown. That is, in this case, an example in which four pixels are simultaneously accessed using the memories 31 of four memory banks is shown.

  The access pattern AP in FIG. 11 is the access candidate P0 set to the fourth pixel from the third left from the top of the search area SR (first in the raster scan order), and the third from the left from the top of the search area SR. Access candidate P1 set for the second (second in raster scan order) pixel, access candidate P2 set for the sixth pixel from the top right in the search area SR (second last from the raster scan order), The search area SR is composed of the access candidate P3 set to the seventh pixel from the top right (the last pixel in the raster scan order).

  Note that the access pattern corresponding to a plurality of pixels to be accessed simultaneously is not limited to the example shown in FIG. For example, when there is a search area SR of vertical h pixels × horizontal w pixels, and there are n (4 in the case of FIG. 11) pixels to be accessed, the type is (h × w) There are C (n). Each combination of the n access candidates is called an access pattern AP. As the access pattern AP, any combination of access candidates in the search area SR is possible. That is, the access pattern AP including the four access candidates P0 to P3 shown in FIG. 11 is an example of 16 × 8C4 (= 10,668,000) combinations.

  The number of pixels that are desired to be accessed simultaneously is referred to as the number of access candidates, and is equal to the number of access candidates that constitute the access pattern. In this example, since the access pattern AP is formed from the four access candidates P0 to P3, the number of access candidates is four.

  12 and 13 are diagrams showing examples of initial arrangement of image data in each bank. In the example of FIG. 12, the two-dimensional arrangement state in the initial arrangement of data in the case of the access pattern of FIG. 11 is shown, and the numbers attached to the circles are the memory banks BK0 in which the data of each pixel is stored. To BK3. In the example of FIG. 13, a one-dimensional arrangement state in each of the memory banks BK0 to BK3 in the initial arrangement of FIG. 12 is shown.

  In the image in the example of FIG. 12, the pixels between the access candidates P0 to P3 are stored in the same memory bank BK shown in the example of FIG.

  Specifically, data for seven pixels from the access candidate P0 in the image of FIG. 12 to the pixel immediately before the access candidate P1 is stored in the memory bank BK0 of FIG. Further, data for 232 pixels from the access candidate P1 in the image of FIG. 12 to the pixel immediately before the access candidate P2 is stored in the memory bank BK1 of FIG. Data for 84 pixels from the access candidate P2 to the pixel immediately before the access candidate P3 is stored in the memory bank BK2, and data for all the pixels (2714 pixels) from the access candidate P3 thereafter is stored in the memory bank BK3. Stored in

  That is, access candidates P0 to P3 are stored at the head of each bank in the initial arrangement of data. Therefore, hereinafter, the access candidates P0 to P3 in the initial arrangement of data are also referred to as access start positions P0 to P3.

  Here, in this data storage device 11, when image data is input, an initial arrangement process is performed by the data storage controller 32, and the input pixel (position) starts access indicated by the access pattern AP. If the position matches, the count value of the bit line address counter 45 and the count value of the word line address counter 46 at that time correspond to the write bit line address and the write word line address at which writing to the memory bank is started. Then, the bank address counter 44 is incremented, and the pixel is stored in the bank address indicated by the bank address counter 44 (that is, the next memory bank BK).

  If the pixel position does not match the access start position indicated by the access pattern AP, the pixel is stored at the bit address position where the count value of the bit line address counter 45 is incremented to the current bank address, and the bit line address Is completed, the bit line address counter 45 is returned to 0 and the count value of the word line address counter 46 is incremented, whereby the pixels between the access start positions are stored in the same memory bank BK.

  Therefore, in the case of the example of FIG. 12, when storing one pixel at a time from the upper left of the image in the bank BK, the data storage control unit 32 sets the bank every time the pixel position matches the access start position indicated by the access pattern AP. By incrementing the address, the memory bank BK0 is followed by the memory bank BK1, the next is the memory bank BK2, the next is the memory bank BK3, and the memory bank is changed to change between the access start positions (access candidates) P0 to P3. Store the pixels in the same bank. That is, the data storage control unit 32 determines whether the image data matches or does not match the access pattern (access start position) in a situation where an access pattern including the access start positions P0 to P3 is set.

  Next, the initial arrangement processing of the data storage control unit 32 will be described in detail with reference to the flowchart of FIG.

  When the data storage control unit 32 starts the initial arrangement process, in step S1, the count values of the bank address counter 44, the bit line address counter 45, and the word line address counter 46 are all initialized to “0”.

  In step S2, the counter 41 inputs image data for one pixel to be stored from the input terminal 21a. The counter 41 counts one pixel and outputs the count result to the coincidence determination unit 42.

  In step S3, the coincidence determination unit 42 performs a coincidence determination between the access pattern AP from the input terminal 21b and the count result of the counter 41, and one input pixel is an access start position (access candidate) of the access pattern AP. It is determined whether it is a pixel.

  If it is determined in step S3 that one input pixel is a pixel at the access start position, that is, if the pixel is at the access start position, in step S4, the address generation unit 47 determines the current word line address. The count values of the counter 46 and the bit line address counter 45 are stored as a write word line address and a write bit line address at which writing to the memory bank corresponding to the bank address is started.

  In step S5, the bank address counter 44 increments the count value, and the word line address counter 46 and the bit line address counter 45 reset the count value to “0”.

  That is, when it is determined that one pixel input in step S3 is a pixel at the access start position, the flag generation unit 43 determines that one pixel input by the match determination unit 42 is a pixel of an access candidate. And the generated flag is output to the bank address counter 44, the word line address counter 46, and the bit line address counter 45.

  In response to this, the bank address counter 44 increments the count value and outputs the incremented count value to the address generation unit 47. The word line address counter 46 and the bit line address counter 45 reset the count value to “0” and output the reset count value to the address generation unit 47.

  Since the address generation unit 47 generates the write address WA indicated by the count value of the bank address counter 44 and the count values “0” of the word line address counter 46 and the bit line address counter 45, the storage control process is performed in step S6. The unit 48 stores the image data of the pixel in the memory 31 with the write address WA generated by the address generation unit 47.

  On the other hand, if it is determined in step S3 that one input pixel is not the pixel at the access start position, the process skips steps S4 and S5 and proceeds to step S6.

  In this case, the address generation unit 47 generates the write address WA indicated by the count values of the current bank address counter 44, the word line address counter 46, and the bit line address counter 45. Therefore, in step S6, the storage control processing unit A write address WA generated by the address generation unit 47 stores image data of the pixel in the memory 31.

  In step S7, the counter 41 refers to the count result and determines whether or not all the image data has been input. Note that this determination processing is actually configured to be executed by, for example, the match determination unit 42 or the like.

  If it is determined in step S7 that all data has not yet been input, the count result is output to the bank address counter 44. The bank address counter 44 receives the count result and outputs the result to the bit line address counter 45.

  Correspondingly, the bit line address counter 45 increments the count value in step S8, and determines in step S9 whether or not the count value of the bit line address counter 45 has become larger than the bit line length. This determination process is actually configured to be executed by, for example, the address generation unit 47.

  If it is determined in step S9 that the count value of the bit line address counter 45 is smaller than the bit line length, the process returns to step S2, and the storage process for the next one pixel of image data is performed.

  If it is determined in step S9 that the count value of the bit line address counter 45 has become larger than the bit line length, the bit line address counter 45 resets the count value to “0” in step S10 and the result thereof. Is output to the word line address counter 46. Correspondingly, the word line address counter 46 increments the count value, and then the process returns to step S2, and the storage process for the image data for the next one pixel is performed.

  If it is determined in step S7 that all data has been input, the initial arrangement process is terminated.

  Next, how to access the pixels of the access pattern and data re-storage will be described.

  In this data storage device 11, as described above with reference to FIG. 12, the image data of each pixel initially arranged on the memory 31 stores the pixels between the access candidates in the same bank. Even if the pattern moves, a certain interval can be accessed simultaneously. However, as described above with reference to FIG. 7, when the movement of the access pattern exceeds the access pixels, the pixels in the same bank are accessed simultaneously. Become.

  Therefore, as described below, the movement of the access pattern can be accommodated by devising the re-storage position of the image data of the accessed pixel.

  FIG. 15 is a diagram schematically showing a method of accessing and restoring the word lines and bit lines in the memory banks BK0 to BK3 in the initial arrangement of FIG.

  In the example of FIG. 15, an example in which data arranged at the head of each of the memory banks BK0 to BK3 is accessed is shown, and the black portion indicates that data is stored. The horizontal thick line represents the last word line in the bank, the vertical thick line represents the last bit line in the bank, and the arrows shown between the banks indicate the data stored at the end of the arrows. It also represents storing at the beginning.

  Therefore, in the data storage device 11, when accessing the data arranged at the head of each of the memory banks BK0 to BK3, as shown by the arrows in FIG. 15, the pixel of the memory bank BK indicated by a certain bank address is accessed. Image data is read out, and the read image data is stored at a position (address) obtained by adding 1 to the last write bit line address of the previous memory bank BK indicated by the bank address −1. The

  That is, the image data stored in the top address (the leftmost 1 in the uppermost stage) of the memory bank BK1 in FIG. 15 is read, and the image data is the next (+1) of the last word line and the last bit line of the bank BK0. ) Bit line position (fourth from the right in the top row). Also, the image data stored at the top address (first leftmost) of the memory bank BK2 is read out, and the image data is read from the last word line of the bank BK1 immediately before the memory bank BK2 and the last bit. Stored at the position of the bit line next to the line (+1) (fourth from the left in the second row from the top).

  Similarly, the image data stored in the top address (first leftmost) of the memory bank BK3 is read, and the image data is read from the last word line of the memory bank BK2 immediately before the memory bank BK3, Stored at the position of the bit line next to the last bit line (+1) (third from the left in the fifth row from the top).

  Accordingly, the pixel image data read from the memory bank BK indicated by the target bank address of the image data of each pixel initially arranged on the memory 31 of FIGS. 12 and 13 is shown in FIGS. 16 and 17. As shown, the bank address of the bank address-1 is stored at a position obtained by adding 1 to the write word line address and write bit line address of the memory bank BK.

  16 and 17 show a case where the image data read from each access candidate pixel in the initial arrangement of the image data in FIGS. 12 and 13 is stored in the memory bank BK indicated by the bank address of the bank address-1 It is a figure which shows the example of.

  In the case of the examples of FIGS. 16 and 17, the image data read from the pixel of the access candidate P1 (that is, the memory bank BK1) of FIGS. The image data read from the pixel of the access candidate P2 (ie, the memory bank BK2) is stored at a position obtained by adding +1 to the final address of the memory bank BK1, and the pixel of the access candidate P3 (ie, the memory bank BK3). The image data read from is stored at a position obtained by adding +1 to the final address of the memory bank BK2.

  Note that the image data read from the pixel of the access candidate P0 in FIGS. 12 and 13 can be stored in the memory bank BK at the bank address -1 (not shown), or the rearmost memory bank. It can also be stored in the BK.

  Next, the one-pixel search area SA moves in the raster scan order, and accordingly, the access candidate moves one pixel from the initial arrangement, and from the access candidate pixel moved by one pixel, as shown in FIG. Image data is read out.

  In the example of FIG. 18, access candidates are shown when the search area SA is moved by one pixel in the raster scan order (right side in the figure).

  As the search area SA moves by one pixel, the access candidate P0 moves to the fifth pixel from the third left from the top of the search area SR, and the access candidate P1 has the third left from the top of the search area SR. From the top to the search area SR, the access candidate P2 moves from the top right to the fourth pixel from the top right, and the access candidate P3 goes from the top right to the seventh right from the top right of the search area SR. Moved to the second pixel.

  In the case of the example in FIG. 18, data for 8 pixels from the access candidate P0 in FIG. 12 to the pixel immediately before the access candidate P1 in FIG. 18 is stored in the memory bank BK0. Further, data for 233 pixels from the access candidate P1 of FIG. 12 to the pixel immediately before the access candidate P2 of FIG. 18 is stored in the memory bank BK1. Data for 85 pixels from the access candidate P2 in FIG. 12 to the pixel immediately before the access candidate P3 in FIG. 18 is stored in the memory bank BK2, and all the pixels (2714) from the access candidate P3 in FIG. Data) is stored in the memory bank BK3.

  Therefore, as shown in FIG. 18, even when the search area SA is moved by one pixel in the raster scan order, the image data of the pixel of the access candidate P0 is read from the memory bank BK0 and the pixel of the access candidate P1 is read. The image data is read from the memory bank BK1, the image data of the pixel of the access candidate P2 is read from the memory bank BK2, and the image data of the pixel of the access candidate P3 is read from the memory bank BK3.

  In the example of FIGS. 19 and 20, similarly to FIGS. 16 and 17, the image data of the pixel of the access candidate P1 read from the memory bank BK1 is incremented by 1 to the final address of the memory bank BK0. The image data of the pixel of the access candidate P2 stored at the read position and read from the memory bank BK2 is stored at the position obtained by adding 1 to the final address of the memory bank BK1, and the access candidate P3 read from the memory bank BK3. Is stored at a position obtained by adding 1 to the last address of the memory bank BK2.

  As described above, as the search area SA moves, reading from each memory bank is not changed, but the next pixel that is an access candidate (that is, one pixel before the access candidate in the raster scan order) exists. By changing the memory bank one after another, simultaneous access can be realized even if the access pattern AP moves in the raster scan order.

  Specifically, the data read / storage control unit 33 in the data storage device 11 increments the count value of the bit line address counters 51-0 to 51-3 or the word line address counters 52-0 to 52-3, If the pixels on the word line address and the bit line address are read by the number of memory banks, a desired pixel can be read. When the prepared word line address and bit line address are completed, the respective count values are returned to zero.

  If the memory bank number is the first, it is written to the last memory bank. Alternatively, if necessary for the subsequent process, the data is written in a memory used for the subsequent process. In any case, this pixel is no longer needed in this process.

  Next, the data re-storing control process of the data reading / storing control unit 33 will be described with reference to the flowchart of FIG.

  In step S <b> 21, the data read / store control unit 33 initializes all the values of the read bit line address counter 51 and the read word line address counter 52 to “0”.

  In step S22, the read control unit 57 configures an access pattern AP from the memory 31 with the read address RA indicated by the count values of the current read bit line address counter 51 and the read word line address counter 52 of each memory bank. The image data for the access candidate pixels is read and output to the write control processing unit 58 for the bank address immediately preceding the read memory bank.

  That is, the read address generation unit 55 generates a read address RA according to the count values of the read bit line address counter 51 and the read word line address counter 52 and outputs the read address RA to the read control unit 57. In response to this, the read control unit 57 reads image data for the access candidate pixels constituting the access pattern AP from the memory 31 by using the read address RA from the read address generation unit 55.

  In step S 23, the write address generation unit 56 reads the write word line address and the write bit line address of the bank address of each memory bank, for example, from the memory 31, generates the write address WA, and supplies the write address WA to the write control processing unit 58. To do.

  In step S24, the write control processing unit 58 uses the write word line address of the bank address of the corresponding memory bank based on the write address WA as the pixel image data read from the bank address immediately after the memory bank. And the write word line address and the write bit line address.

  In step S25, the read control processing unit 57 determines whether or not all one screen has been scanned based on the number of read pixels, and if it is determined that all one screen has not been scanned yet, the process proceeds to step S25. Proceeding to S26, address calculation processing is executed. This address calculation process will be described later with reference to the flowchart of FIG.

  By the address calculation processing in step S26, the read word line address and bit line address of the bank address required for the next read from each memory bank, and the write word line address of the bank address required for writing to each memory bank Since the bit line address is calculated and stored in the memory 31, for example, the process returns to step S22, and the subsequent processes are repeated.

  On the other hand, if it is determined in step S25 that the entire screen has been scanned based on the number of read pixels, the data re-storing control process is terminated.

  Next, the address calculation process in step S26 of FIG. 21 will be described in detail with reference to the flowchart of FIG.

  In step S24 of FIG. 21, the write bit line address counter 53 receives the write bit line address WA written at the end of the memory bank, and increments the count value in step S31.

  In step S32, the write bit line address counter 53 determines whether or not the count value has become larger than the bit line length.

  If it is determined in step S32 that the count value has become larger than the bit line length, the write bit line address counter 53 resets the value to “0” and outputs the result to the write word line address counter 54. In step S33, the write word line address counter 54 increments the count value. As a result, the write word line address written at the end of the target memory bank in step S24 of FIG. 21 is incremented.

  In step S34, the write word line address counter 54 determines whether or not the counter value is larger than the word line length.

  Note that the determination processing in steps S32 and S34 is actually configured to be executed by the write address generation unit 56, for example.

  If it is determined in step S34 that the value of the write word line address counter 54 has become larger than the word line length, the write bit line address counter 53 resets the count value to “0”. Then, the process returns to step S26 in FIG. 21, proceeds to step S22, and the subsequent processes are repeated.

  On the other hand, if it is determined in step S34 that the value of the write bit line address counter 53 is still smaller than the bit line length, or if the value of the write word line address counter 54 is still smaller than the word line length, The process returns to step S26 in FIG. 21 and proceeds to step S22, and the subsequent processes are repeated.

  The calculation of the read word line address and bit line address in step S26 of FIG. 21 is performed in the same manner. At this time, the write bit line address counter 53 (53-0 to 53-3) and the write word line address counter 54 (54-0 to 54-3) used in the write address calculation respectively read the read bit line address. It will be read as a counter 51 and a read word line address counter 52.

  Further, in the address calculation for writing, in step S31, the write bit line address last written in each memory bank in step S24 of FIG. 21, and in step S31, the last read in each memory bank in step S23 of FIG. The write word line address written in is used, but in the read address calculation, in step S31, the last read bit line address read from each memory bank in step S22, and in step S33, each memory in step S22. The read word line address read last from the bank is used.

  In the above description, when the area between the access candidates of the access pattern is scanned in the raster direction, the data in the memory bank BK3 is written in the memory bank BK2, the data in the memory bank BK2 is written in the memory bank BK1, and the memory bank The data of BK1 is written to the memory bank BK0, but this memory bank address is not limited to this, the data of the memory bank BK3 is stored in the memory bank BK0, and the data of the memory bank BK0 is stored in the memory bank BK2. A structure may be adopted in which data is read / written according to a certain pattern in which data in the memory bank BK2 is written into the memory bank BK1.

  Further, the scanning direction is not limited to the raster scanning direction, and may be opposite to the raster scanning direction, the vertical direction, the oblique direction, or the like.

  In the above description, the data read storage processing unit reads the pixel data on the word line address and the bit line address by the number of banks while incrementing the word line address and the bit line address. However, the present invention is not limited to this, and it is sufficient if reading is performed according to a certain pattern. Therefore, the word line address and bit line address may be decremented, and the pixels of the word line address and bit line address may be read based on a predetermined pattern.

  Furthermore, in the above description, the read pixel data is stored behind the already written area of the previous memory bank. Instead, the read pixel data is already read from the previous memory bank. May be overwritten on the existing area. In other words, it may be overwritten from the beginning of the previous memory bank. In this case, it is necessary to sequentially overwrite the address following the overwritten address in the same manner as when the data is stored behind the written area. Further, writing is not limited to the previous memory bank.

  That is, as described above with reference to FIG. 18, the pixel image data is read from the memory bank indicated by a certain bank address from the image data of each pixel initially arranged on the memory 31 as described above. As described above with reference to FIG. 4, the data is stored in the write word line address and write bit line address of the bank address indicated by the bank address −1.

  Also in this case, as the search area moves, reading from each memory bank does not change, but the memory banks to which accessed pixels are written are changed one after another, so that the pattern moves in the raster scan order. Even at the same time, simultaneous access can be realized.

  By the way, in the above description, it is explained that a plurality of images can be simultaneously accessed with a certain access pattern by preparing the memory 31 with the number of memory banks corresponding to the access pixels (minimum necessary). However, depending on the image size and the size of the search area SR, the required memory amount may increase. This is because it is necessary to prepare a memory amount assuming the worst case shown in FIGS.

  23 to 26, the access is performed when the image size is 40 pixels vertically and 80 pixels horizontally, the search area SR is 8 pixels vertically and 16 pixels horizontally, and the number of access candidates is 4 (access candidates P0 to P3). It is a figure which shows the example of a pattern. In this case, the pixel data from the access candidate P0 pixel to the access candidate P1 is stored in the memory bank BK0, and the pixel data from the access candidate P1 pixel to the access candidate P2 is stored in the memory bank BK1. The stored pixel data from the pixel of the access candidate P2 to the front of the access candidate P3 is stored in the memory bank BK2, and the data of all the remaining pixels from the pixel of the access candidate P3 is stored in the memory bank BK3.

  In the example of FIG. 23, an access pattern in the case where the required memory amount of the memory bank BK0 is the worst case (ie, maximum) is shown. That is, the access pattern AP0 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR (the first pixel in the raster scan order), and the third from the right from the top of the search area SR. Access candidate P1 set for the th (third from the last in the raster scan order) pixel, access candidate set for the eighth pixel from the top right in the search area SR (second from the last in the raster scan order) P2 is composed of the access candidate P3 set in the eighth pixel from the top right in the search area SR and the first pixel from the right (the last pixel in the raster scan order).

  Therefore, in the example of FIG. 23, the memory bank BK0 includes data of 573 (= 80 × (8-1) + 16-3) pixels from the pixel of the access candidate P0 to the pixel immediately before the access candidate P1. Is stored in the memory bank BK1, the data of one pixel of the access candidate P1 is stored in the memory bank BK2, the data of one pixel of the access candidate P2 is stored in the memory bank BK2, and the access candidate P3 is stored in the memory bank BK3. 2625 (= 80 × 40−80 × 7−16 + 1) pixels that are all remaining pixels from the pixel are stored.

  In the example of FIG. 24, an access pattern in the case where the required memory amount of the memory bank BK1 is the worst case is shown. In other words, the access pattern AP1 includes the access candidate P0 set to the first pixel from the first left from the top of the search area SR (the first pixel in the raster scan order) and the first two from the left from the top of the search area SR. Access candidate P1 set for the second (second in raster scan order) pixel, access candidate P2 set for the eighth pixel from the top right in search area SR (second last from raster scan order), The search area SR is composed of access candidates P3 set to the eighth pixel from the top right (the last pixel in the raster scan order).

  Therefore, in the example of FIG. 24, data of one pixel of the access candidate P0 is stored in the memory bank BK0, and from the pixel of the access candidate P1 to the pixel immediately before the access candidate P2 in the memory bank BK1. 573 (= 80 × (8−2) + (80−1) + 16−2) pixel data is stored, one pixel data of the access candidate P2 is stored in the memory bank BK2, and the memory bank BK3 is stored. Stores 2625 pixels which are all remaining pixels from the pixel of the access candidate P3.

  In the example of FIG. 25, an access pattern in the case where the required memory amount of the memory bank BK2 is the worst case is shown. In other words, the access pattern AP2 includes the access candidate P0 set to the first pixel from the top left (first in the raster scan order) from the top of the search area SR, and the top left from the top left of the search area SR. Access candidate P1 set for the second (second in raster scan order) pixel, access candidate P2 set for the third pixel from the left (third in raster scan order) from the top of the search area SR, search area The access candidate P3 is set to the eighth pixel from the top right of SR and the first pixel from the right (last in the raster scan order).

  Therefore, in the example of FIG. 25, the data of one pixel of the access candidate P0 is stored in the memory bank BK0, the data of one pixel of the access candidate P1 is stored in the memory bank BK1, and the memory bank BK2 is stored in the memory bank BK2. , 573 (= 80 × (8−2) + (80−2) + 16−1) pixel data from the pixel of the access candidate P2 to the pixel immediately before the access candidate P3 is stored in the memory bank BK3. Stores data of 2625 pixels, which are all remaining pixels from the pixel of the access candidate P3.

  In the example of FIG. 26, an access pattern in the case where the required memory amount of the memory bank BK3 is the worst case is shown. In other words, the access pattern AP3 includes the access candidate P0 set to the first pixel from the first left from the top of the search area SR (first in the raster scan order), and the first two from the left from the top of the search area SR. Access candidate P1 set for the second (second in raster scan order) pixel, access candidate P2 set for the third pixel from the left (third in raster scan order) from the top of the search area SR, search area The access candidate P3 is set to the fourth pixel from the left from the top of the SR (fourth in the raster scan order).

  Therefore, in the example of FIG. 26, the data of one pixel of the access candidate P0 is stored in the memory bank BK0, the data of one pixel of the access candidate P1 is stored in the memory bank BK1, and the memory bank BK2 is stored in the memory bank BK2. The data of one pixel of the access candidate P2 is stored, and the memory bank BK3 stores data of 3197 pixels (= 80 × 40−3) which are all remaining pixels from the pixel of the access candidate P3.

  From the above, considering all the worst cases of the required memory amounts of the memory banks BK0 to BK3, it is necessary to store data of 4916 (= 573 × 3 + 3197 × 1) pixels as a whole. Accordingly, when the image size is 40 pixels in the vertical direction and 80 pixels in the horizontal direction, the memory amount is 4916 / (80 × 40) = approximately 1.54 sheets.

  This is due to the fact that access candidates in the access pattern are separated by configuring with the minimum number of memory banks, and depending on the image size and search area size, there are severe restrictions on the amount of memory. Below, it may be difficult to achieve. Therefore, in the following, an example will be described in which the memory is configured with the number of memory banks equal to or greater than the minimum number of memory banks.

  FIG. 27 shows a configuration example of a data storage device to which the present invention is applied.

  The data storage device 111 of FIG. 27 is common to the data storage device 11 of FIG. 8 in that it includes input terminals 21a to 21c, an output terminal 21b, a memory 31, and a data read / store control unit 33. 8 differs from the data storage device 11 of FIG. 8 in that 32 is replaced with the data storage control unit 121 and a selector setting unit 122 and a selector 123 are added.

  The memory 31 in the example of FIG. 27 includes a number of memory banks (for example, eight memory banks BK0 to BK7) designed in advance by the design device 201 of FIG.

  The data storage control unit 121 uses not only the access pattern AP from the input terminal 21c but also the input terminal 21a based on the maximum number of stored pixels per memory bank designed in advance by the design device 201 in FIG. Initial arrangement processing for arranging (storing) input data DA in the memory 31 is performed.

  That is, when the data storage control unit 121 determines whether the pixel input from the input terminal 21a is an access candidate constituting the access pattern AP from the input terminal 21c, and determines that the pixel is not an access candidate Then, it is determined whether or not the number of pixels currently stored in the memory bank BK to be stored exceeds the maximum number of stored pixels.

  When it is determined that the input pixel is an access candidate, or when it is determined that the pixel currently stored in the memory bank BK to be stored exceeds the maximum storage pixel number, the data storage control unit 121 changes the memory bank BK to be stored to the next memory bank BK, and stores the data of the target pixel in the memory bank BK. Further, the data storage control unit 121 controls the selector setting unit 122 so that the data from the changed memory bank BK is selected only when it is determined that the input pixel is an access candidate.

  If it is determined that the input pixel is not an access candidate and the pixel currently stored in the memory bank BK to be stored does not exceed the maximum storage pixel number, the data storage control unit 121 The pixel data is stored in the memory bank BK that is currently stored.

  The selector setting unit 122 is set so that, under the control of the data storage control unit 121, the memory bank BK storing access candidate data among the plurality of memory banks BK of the memory 31 is selected by the selector 123. To do.

  The selector 123 selects and reads data from the memory bank BK storing access candidate data among the plurality of memory banks BK of the memory 31 and outputs the read data from the output terminal 22.

  27 is configured by the number of data read / store control units 33 corresponding to the number of memory banks of the memory 31, the data read / store control unit described above with reference to FIG. 10. 33 is different from the data read / storage control units 33-1 to 33-4 corresponding to the four memory banks BK, and the basic configuration is the same, and the description thereof is omitted.

  FIG. 28 is a diagram illustrating a configuration example of the data storage control unit 121 of FIG.

  The data storage control unit 121 of FIG. 28 includes a counter 41, a match determination unit 42, a flag generation unit 43, a bank address counter 44, a bit line address counter 45, a word line address counter 46, and a storage control processing unit 48. 9 is common to the data storage control unit 32 of FIG. 9, but the point that the address generation unit 47 is replaced with the address generation unit 142 and the point that the pixel number determination unit 141 is added are the data storage control unit of FIG. 32.

  The determination result of the coincidence determination unit 42 in FIG. 28 is also output to the pixel number determination unit 141.

  The pixel number determination unit 141 stores the maximum number of pixels stored per memory bank designed in advance by the design device 201 of FIG. 35, and when the determination result from the match determination unit 42 is inconsistent, the bit line address Based on the count values of the counter 45 and the word line address counter 46, it is determined whether or not the number of pixels stored in the memory bank BK exceeds the maximum number of stored pixels, and the determination result is output to the flag generation unit 43. . Although not shown, this determination result is also output to the address generation unit 142.

  The flag generation unit 43 in FIG. 28 generates a flag not only according to the determination result from the coincidence determination unit 42 but also according to the determination result from the pixel number determination unit 141, and the generated flag is stored in the bank address counter 44, bit The data is output to the line address counter 45 and the word line address counter 46.

  When the determination result from the match determination unit 42 indicates a match, the address generation unit 141 generates the write address WA based on the count values indicated by the bank address counter 44, the bit line address counter 45, and the word line address counter 46. And output to the storage control processing unit 48. At this time, the address generation unit 141 outputs the count value (that is, the bank address) indicated by the bank address counter 44 to the selector setting unit 122.

  In addition, when the determination result from the pixel number determination unit 141 indicates that the maximum storage pixel number is exceeded, the address generation unit 141 counts the bank address counter 44, the bit line address counter 45, and the word line address counter 46. Based on the value, a write address WA is generated and output to the storage control processing unit 48. At this time, the count value (that is, the bank address) indicated by the bank address counter 44 is not output to the selector setting unit 122.

  FIG. 29 is a diagram showing an example of an initial arrangement of image data in each memory bank BK in the case of the access pattern AP0 of FIG.

  That is, as in the example of FIG. 23, this access pattern AP0 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR and the eighth right from the top of the search area SR. The access candidate P1 set for the third pixel, the access candidate P2 set for the second pixel from the right from the top of the search area SR, and the eighth pixel from the top right of the search area SR It is comprised by the access candidate P3 set to.

  In the example of FIG. 29, the number of memory banks is set to 8 and the maximum number of stored pixels per memory bank is set to 160 pixels by the design apparatus 201 of FIG.

  Therefore, data for 160 pixels including the pixel of the access candidate P0 is stored in the memory bank BK0. The 161st pixel (the third pixel from the top left of the search area SR, the first pixel from the left) Q0 including the pixel of the access candidate P0 is stored in the memory bank BK0 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q0 is stored in the next memory bank BK1.

  The next memory bank BK1 stores data for 160 pixels including the pixel Q0. For the 161st pixel (the 5th pixel from the top left in the search area SR) including the pixel Q0, the pixel stored in the memory bank BK1 even if it is determined not to match the access candidate Since the number exceeds 160 pixels, which is the maximum storage pixel number, the data from the pixel Q1 is stored in the next memory bank BK2.

  The next memory bank BK2 stores data for 160 pixels including the pixel Q1. For the 161st pixel (the 7th pixel from the top left in the search area SR) including the pixel Q1, the pixel stored in the memory bank BK2 even if it is determined not to match the access candidate Since the number exceeds 160 pixels which is the maximum storage pixel number, the data from the pixel Q2 is stored in the next memory bank BK3.

  The next memory bank BK3 stores data of 93 (= 80 + 16-3) pixels from the pixel Q1 to the pixel immediately before the access candidate P1, and the memory bank BK4 stores one pixel of the access candidate P1. Data is stored, and data of one pixel of the access candidate P2 is stored in the memory bank BK5.

  The memory bank BK6 stores data for 160 pixels including the access candidate P3. The 161st pixel (the 10th pixel from the top left in the search area SR, the 16th pixel from the left) Q3 including the access candidate P3 is stored in the memory bank BK6 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q3 is stored in the next memory bank BK7.

  The memory bank BK7 stores 2465 (= 80 × 40− (80 × 9 + 15)) pixels which are all the remaining pixels from the pixel Q3. Note that the maximum number of stored pixels is not applied to the last memory bank BK.

  Note that the access pattern AP1 in FIG. 24 is basically the same, and thus illustration and detailed description thereof are omitted. However, one pixel is stored in the memory bank BK0 and stored in the memory banks BK1 to BK3. 160 pixels are stored, 93 pixels are stored in the memory bank BK4, 1 pixel is stored in the memory bank BK5, 160 pixels are stored in the memory bank BK6, and 2465 pixels are stored in the memory bank BK7. The

  Similarly, in the case of the access pattern AP2 in FIG. 25, one pixel is stored in the memory bank BK0 and the memory bank BK1, 160 pixels are stored in the memory banks BK2 to BK4, and 93 pixels are stored in the memory bank BK5. One pixel is stored in the memory bank BK6, 160 pixels are stored in the memory bank BK6, and 2465 pixels are stored in the memory bank BK7.

  That is, the access patterns AP1 and AP2 are stored in the memory banks BK1 to BK5 because the access candidates P1 and P2 and the positions of the pixels Q0 to Q2 in the search area SR are different from the access pattern AP1. Only the number of pixels is changed in the memory banks BK1 to BK5.

  FIG. 30 is a diagram illustrating an example of initial arrangement of image data in each memory bank BK in the case of the access pattern AP3 of FIG.

  That is, as in the example of FIG. 26, the access pattern AP3 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR and the first left from the top of the search area SR. The access candidate P1 set to the second pixel, the access candidate P2 set to the third pixel from the left from the top of the search area SR, and the first pixel from the left to the top of the search area SR It is comprised by the access candidate P3 set to.

  Also in the example of FIG. 30, the number of memory banks is set to 8 and the maximum number of stored pixels per memory bank is set to 160 pixels by the design device 201 of FIG.

  Therefore, one pixel data of the access candidate P0 is stored in the memory bank BK0, one pixel data of the access candidate P1 is stored in the memory bank BK1, and one pixel of the access candidate P2 is stored in the memory bank BK2. The data for 160 pixels including the pixel of the access candidate P3 is stored in the memory bank BK3.

  The 161st pixel (the third pixel from the top left of the search area SR, the fourth pixel from the left) Q0 including the pixel of the access candidate P3 is stored in the memory bank BK3 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q0 is stored in the next memory bank BK4.

  As a result, data for 160 pixels including the pixel Q0 is stored in the memory bank BK4. The 161st pixel (the 5th pixel from the top left of the search area SR, the 4th pixel from the left) Q1 including the pixel Q0 is stored in the memory bank BK4 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q1 is stored in the next memory bank BK5.

  Similarly, data for 160 pixels including the pixel Q1 is stored in the memory bank BK5. For the 161st pixel (the 7th pixel from the top left in the search area SR, the 4th pixel from the left) Q2 including the pixel Q1, the pixel stored in the memory bank BK5 even if it is determined not to match the access candidate Since the number exceeds 160 pixels, which is the maximum storage pixel number, the data from the pixel Q2 is stored in the next memory bank BK6.

  The memory bank BK6 stores data for 160 pixels including the pixel Q2. For the 161st pixel (the 9th pixel from the top left in the search area SR), including the pixel Q2, the pixel stored in the memory bank BK6 even if it is determined not to match the access candidate Since the number exceeds 160 pixels, which is the maximum storage pixel number, the data from the pixel Q3 is stored in the next memory bank BK7.

  The memory bank BK7 stores 2557 (= 80 × 40− (80 × 8 + 3)) pixels which are all the remaining pixels from the pixel Q3.

  As described above, the number of memory banks and the maximum number of pixels stored in one memory bank BK are set more than the number of access candidates, and even if the number of pixels stored in the memory bank BK is not the access candidate, When the number of stored pixels is exceeded, the data is stored in the next memory bank BK.

  Accordingly, in consideration of all the worst cases of the required memory amounts of the memory banks BK0 to BK7, it is necessary to store data of 3777 (= 160 × 7 + 2557) pixels as a whole.

  Therefore, when the image size is 40 pixels in the vertical direction and 80 pixels in the horizontal direction, the memory amount is only 3677 / (80 × 40) = 1.15. 26, the amount of memory is reduced from the amount of memory corresponding to approximately 1.54 when the number of memory banks BK corresponding to the number of access candidates described above is used.

  Next, a data selection method of the selector 123 will be described with reference to FIG. 31 and FIG.

  FIG. 31 is a diagram illustrating an example of an initial arrangement of image data in each memory bank BK in the case of another access pattern. Although not shown, the example of FIG. 31 also shows a search area consisting of 8 vertical pixels and 16 horizontal pixels on an image composed of 40 vertical pixels and 80 horizontal pixels. Also in this case, the number of memory banks is set to 8, and the maximum number of stored pixels per memory bank is set to 160 pixels.

  The access pattern shown in FIG. 31 is set to the access candidate P0 set at the third pixel from the top left from the top of the search area SR and the eleventh pixel from the top left at the top of the search area SR. Access candidate P1, access candidate P2 set to the third pixel from the top left in the search area SR, access candidate P3 set to the seventh pixel from the top left in the search area SR It consists of

  Therefore, the memory bank BK0 stores 7-pixel data from the access candidate P0 to the pixel immediately before the access candidate P1, and the memory bank BK1 stores data for 160 pixels including the access candidate P1. Stored.

  The 161st pixel (the third pixel from the top left of the search area SR and the eleventh pixel from the left) Q0 including the pixel of the access candidate P1 is stored in the memory bank BK1 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q0 is stored in the next memory bank BK2.

  The memory bank BK2 stores data of 72 pixels from the pixel Q0 to the pixel immediately before the access candidate P2, and the memory bank BK3 stores 84 data from the access candidate P2 to the pixel immediately before the access candidate P3. Pixel data is stored. The memory bank BK4 stores data for 160 pixels including the pixel of the access candidate P3.

  The 161st pixel (the ninth pixel from the top left of the search area SR, the seventh pixel from the left) Q1 including the pixel of the access candidate P3 is stored in the memory bank BK4 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 160 pixels, the data from the pixel Q1 is stored in the next memory bank BK5.

  The memory bank BK5 stores data for 160 pixels including the pixel Q1. For the 161st pixel (the seventh pixel from the top left in the search area SR, the seventh pixel from the left) Q2 including the pixel Q1, the pixel stored in the memory bank BK5 even if it is determined not to match the access candidate Since the number exceeds 160 pixels, which is the maximum storage pixel number, the data from the pixel Q2 is stored in the next memory bank BK6.

  The memory bank BK6 stores data for 160 pixels including the pixel Q2. For the 161st pixel including the pixel Q2 (the 13th pixel from the 13th left from the top of the search area SR) Q3, even if it is determined not to match the access candidate, the pixel stored in the memory bank BK6 Since the number exceeds 160 pixels, which is the maximum storage pixel number, the data from the pixel Q3 is stored in the next memory bank BK7.

  The memory bank BK7 stores 2234 (= 80 × 40− (80 × 12 + 6)) pixels, which are all the remaining pixels from the pixel Q3.

  Here, in the data read / store control unit 33 of the data storage device 111, the data re-store control process described above with reference to FIG. 21 is executed for the eight memory banks BK0 to BK8. At this time, the data of the four access candidates P0 to P3 and the data of the four pixels Q0 to Q3 are read and re-stored by the eight data read / store control units 33 corresponding to the eight memory banks BK0 to BK8. .

  That is, the data of the access candidate P0 is read from the memory bank BK0, the data of the access candidate P1 is read from the memory bank BK1, the data of the access candidate P2 is read from the memory bank BK3, and the data of the access candidate P3 is Read from the memory bank BK4. Further, the data of the pixel Q0 is read from the memory bank BK2, the data of the pixel Q1 is read from the memory bank BK5, the data of the pixel Q2 is read from the memory bank BK6, and the data of the pixel Q3 is read from the memory bank BK7. Read out.

  However, since the four pixels Q0 to Q3 are not access candidates, the data of the four pixels Q0 to Q3 need not be output from the data storage device 111. Therefore, as shown in FIG. 32, the selector 123 selects to output only the data from the memory bank BK storing the access candidate data.

  FIG. 32 is a diagram schematically showing the configuration of the selector.

  In the example of FIG. 32, the memory 31 includes memory banks BK0 to BK7, and the selector 123 selects and outputs the data of the access candidate P0 from the memory bank BK0 in which the data of the access candidate P0 is stored. The data of the access candidate P1 is selected and output from the memory bank BK1 in which the data of the access candidate P1 is stored.

  Further, the selector 123 selects and outputs the data of the access candidate P2 from the memory bank BK3 in which the data of the access candidate P2 is stored, and from the memory bank BK4 in which the data of the access candidate P3 is stored. The data of the access candidate P3 is selected and output.

  That is, based on the determination result by the match determination unit 42, the address generation unit 141 outputs the bank address with the incremented count value to the selector setting unit 122 when the input pixel is an access candidate. In response to this, the selector setting unit 122 sets the selector 123 so as to select the memory bank BK corresponding to the bank address.

  On the other hand, the address generation unit 141 stores the maximum number of pixels stored in the memory bank BK by the pixel number determination unit 141 when the input pixel is not an access candidate based on the determination result by the match determination unit 42. When it is determined that the number of pixels is exceeded, even if the count value of the bank address is incremented, the bank address is not output to the selector setting unit 122.

  As described above, the selector 123 can select only the data from the memory bank BK in which the access candidates are stored and output it from the output terminal 22.

  Next, the initial arrangement processing of the data storage control unit 121 in FIG. 27 will be described in detail with reference to the flowchart in FIG. Note that steps S101 to S105 and steps S110 and S111 in FIG. 33 perform basically the same processing as steps S1 to S5 and steps S108 and S109 in FIG. 14, and thus detailed description thereof will be repeated. Therefore, it is omitted as appropriate.

  When the data storage control unit 32 starts the initial arrangement process, in step S101, the count values of the bank address counter 44, the bit line address counter 45, and the word line address counter 46 are all initialized to “0”.

  In step S102, the counter 41 inputs image data for one pixel to be stored from the input terminal 21a. The counter 41 counts one pixel and outputs the count result to the coincidence determination unit 42.

  In step S103, the coincidence determination unit 42 performs a coincidence determination between the access pattern AP from the input terminal 21b and the count result of the counter 41, and one input pixel is an access start position (access candidate) indicated by the access pattern AP. ) Is determined.

  If it is determined in step S103 that one input pixel is the pixel at the access start position, that is, if the pixel is at the access start position, in step S104, the address generator 142 determines the current word line address. The count values of the counter 46 and the bit line address counter 45 are stored as a write word line address and a write bit line address at which writing to the memory bank BK corresponding to the bank address is started.

  In step S105, the bank address counter 44 increments the count value, and the word line address counter 46 and the bit line address counter 45 reset the count value to “0”.

  That is, the flag generation unit 43 generates a flag according to a determination result that one pixel input by the match determination unit 42 is an access candidate pixel, and uses the generated flag as the bank address counter 44 and the word line address counter. 46 and the bit line address counter 45.

  In response to this, the bank address counter 44 receives the count result of the counter 41, increments the count value, and outputs the incremented count value to the address generation unit 142. The word line address counter 46 and the bit line address counter 45 reset the count value to “0” and output the reset count value to the address generation unit 142.

  In step S <b> 106, the address generation unit 142 outputs the count value of the bank address counter 44 to the selector setting unit 122. Thereby, the selector setting unit 122 sets the selector 123 so as to select the memory bank (memory bank in which the pixel data of the access candidate) corresponding to the bank address is selected.

  Since the address generation unit 142 generates the write address WA indicated by the count value of the bank address counter 44 and the count values “0” of the word line address counter 46 and the bit line address counter 45, the storage is performed in step S110. The control processing unit 48 stores the image data of the pixel in the memory 31 with the write address WA generated by the address generation unit 142.

  On the other hand, if it is determined in step S103 that one input pixel is not the pixel at the access start position, the pixel number determination unit 141 refers to the count values of the word line address counter 46 and the bit line address counter 45, and It is determined whether or not the number of stored pixels in the corresponding memory bank BK exceeds the maximum number of stored pixels per memory bank set by the design device 201 in FIG. Note that this determination processing is actually configured to be executed by, for example, the match determination unit 42 or the like.

  If it is determined in step S107 that the number of stored pixels in the corresponding memory bank BK exceeds the maximum number of stored pixels per memory bank, the address generator 142 determines that the current word line address counter 46 and The count value of the bit line address counter 45 is stored as a write word line address and a write bit line address at which writing to the memory bank BK corresponding to the bank address is started.

  In step S109, the bank address counter 44 increments the count value, and the word line address counter 46 and the bit line address counter 45 reset the count value to “0”.

  That is, the flag generation unit 43 generates a flag according to the determination result that one pixel input by the pixel number determination unit 141 is an access candidate pixel, and uses the generated flag as the bank address counter 44 and the word line address. The data is output to the counter 46 and the bit line address counter 45.

  In response to this, the bank address counter 44 receives the count result of the counter 41, increments the count value, and outputs the incremented count value to the address generation unit 142. The word line address counter 46 and the bit line address counter 45 reset the count value to “0” and output the reset count value to the address generation unit 142.

  Since the address generation unit 142 generates the write address WA indicated by the count value of the bank address counter 44 and the count values “0” of the word line address counter 46 and the bit line address counter 45, the storage is performed in step S110. The control processing unit 48 stores the image data of the pixel in the memory 31 with the write address WA generated by the address generation unit 142.

  If it is determined in step S107 that the number of stored pixels in the corresponding memory bank BK exceeds the maximum number of stored pixels per memory bank, the process skips steps S108 and S109 and proceeds to step S110.

  In this case, the address generation unit 142 generates the write address WA indicated by the count values of the current bank address counter 44, the word line address counter 46, and the bit line address counter 45. Therefore, in step S110, the storage control processing unit Reference numeral 48 denotes a write address WA generated by the address generation unit 142, which stores image data of the pixel in the memory 31.

  In step S111, the counter 41 refers to the counting result to determine whether or not all the data of the image has been input. If it is determined that all the data has not yet been input, the counter result is used as the bank address counter 44. Output to. The bank address counter 44 receives the count result and outputs the result to the bit line address counter 45.

  Correspondingly, in step S112, an initial storage address calculation process is executed. This initial storage address calculation process will be described with reference to the flowchart of FIG. Note that the processing in steps S131 through S133 in FIG. 34 is basically the same as the processing in steps S8 through S10 in FIG. 14, and therefore detailed description thereof will be omitted as appropriate.

  In step S131, the bit line address counter 45 increments the count value. In step S132, the bit line address counter 45 determines whether or not the count value of the bit line address counter 45 has become larger than the bit line length. This determination process is actually configured to be executed by, for example, the address generation unit 47.

  If it is determined in step S132 that the count value is smaller than the bit line length, the process returns to step S102 in FIG. 33, and the storage process for the next one pixel of image data is performed.

  If it is determined in step S132 that the count value has become larger than the bit line length, the process proceeds to step S133, and the bit line address counter 45 resets the count value to “0” and the result is The data is output to the word line address counter 46. Correspondingly, the word line address counter 46 increments the count value, and then the process returns to step S102 in FIG. 33, and the storage process for the next one pixel of image data is performed.

  If it is determined in step S111 that all data has been input, the initial arrangement process is terminated.

  As described above, the number of memory banks and the maximum number of stored pixels stored in one memory bank are set more than the number of access candidates, and the pixels in the memory bank being stored are the maximum stored pixels even if they are not access candidates. When the number exceeds the number, the number of memory banks BK is stored in the next memory bank BK. As a result, the memory capacity of the memory 31 is reduced.

  Next, a design apparatus for designing the number of memory banks and the maximum number of pixels stored per memory bank, which are parameters of the data storage device 111 described above, will be described.

  FIG. 35 is a block diagram illustrating a hardware configuration example of a design apparatus to which the present invention is applied.

  The design apparatus 201 is composed of, for example, a computer shown in FIG.

  A CPU (Central Processing Unit) 211 executes various processes according to a program stored in a ROM (Read Only Memory) 212 or a storage unit 418. A RAM (Random Access Memory) 213 appropriately stores programs executed by the CPU 211 and data. The CPU 211, ROM 212, and RAM 213 are connected to each other by a bus 214.

  An input / output interface 215 is also connected to the CPU 211 via the bus 214. The input / output interface 215 is connected to an input unit 216 including a keyboard, a mouse, and a microphone, and an output unit 217 including a display and a speaker. The CPU 211 executes various processes in response to commands input from the input unit 216. Then, the CPU 211 outputs the processing result to the output unit 217.

  The storage unit 218 connected to the input / output interface 215 includes, for example, a hard disk, and stores programs executed by the CPU 211 and various data. The communication unit 219 communicates with an external device via a network such as the Internet or a local area network.

  A program may be acquired via the communication unit 219 and stored in the storage unit 218.

  The drive 220 connected to the input / output interface 215 drives a removable medium 221 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives the programs and data recorded therein. Get etc. The acquired program and data are transferred to and stored in the storage unit 218 as necessary.

  Note that the data storage devices 11 and 111 described above can also be configured by a computer having basically the same configuration as the design device 201 shown in FIG.

  Here, when the CPU 211 executes various programs, the computer in FIG. 35 functions as the design device 201 or the data storage devices 11 and 111. In this case, the program can be recorded in advance in a ROM 212 or a storage unit 218 as a recording medium built in the computer of FIG. Alternatively, the program can be stored (recorded) temporarily or permanently in a removable medium 221 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and provided as so-called package software.

  The program is installed on the computer shown in FIG. 35 from the removable medium 21 as described above, or transferred from the download site via the digital satellite broadcasting artificial satellite to the computer shown in FIG. It is also possible to install the program by transferring it to the computer shown in FIG.

  FIG. 36 is a block diagram illustrating a functional configuration example of the design apparatus 201. The functional blocks shown in FIG. 36 are realized by a predetermined program being executed by the CPU 211 of the design apparatus 201.

  This functional block includes a storage pixel number calculation unit 231, a memory amount calculation unit 232, and a bank number setting unit 233.

  For example, the designer sets predetermined parameters (image size, search area size, number of access patterns, and number of memory banks to be used) for designing the data storage device 111, a keyboard constituting the input unit 216, and the like. Is input to the design apparatus 201.

  The storage pixel number calculation unit 231 temporarily sets the number of memory banks that are candidates for use in response to the operation of the input unit 216, and sets the image size, the size of the search area, the number of access patterns, and the temporarily set number of memory banks. Based on the above, the maximum number of pixels stored per memory bank is calculated, and the calculated maximum number of pixels stored is output to the memory amount calculator 232.

  In the case of the temporarily set memory bank number based on the maximum storage pixel number calculated by the storage pixel number calculating unit 231, the temporarily set memory bank number, the image size, and the access pattern number, the memory amount calculating unit 232 The required memory amount is calculated, and the calculated required memory amount and the temporarily set memory bank number are output to the bank number setting unit 233.

  The bank number setting unit 233 sets the memory amount used in the data storage device 111 based on a plurality of temporarily set memory bank numbers and the corresponding required memory amount, and corresponds to the set memory amount. The number of memory banks is set to the number of memory banks used in the data storage device 111.

  A method for setting the number of memory banks will be specifically described below.

  FIG. 37 is a diagram showing an example of the initial arrangement of image data in each bank when the access pattern AP0 of FIG. 23 and the temporarily set memory bank number (hereinafter referred to as the temporarily set memory bank number) is 5. .

  That is, as in the example of FIG. 23, this access pattern AP0 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR and the eighth right from the top of the search area SR. The access candidate P1 set for the third pixel, the access candidate P2 set for the second pixel from the right from the top of the search area SR, and the eighth pixel from the top right of the search area SR It is comprised by the access candidate P3 set to.

  In the example of FIG. 37, when the position of the access candidate or the distance between the access candidates (that is, the maximum number of stored pixels) exceeds 320 (= 80 × 8 / (5-4 + 1)) pixels, the memory is stored. Bank BK is switched. The maximum number of pixels to be stored is the number of pixels that can be switched from the horizontal size of the image × the vertical size of the search area other than the position of the access candidate (that is, the number of temporarily set memory banks−the number of access candidates) +1. Divided. Specifically, the maximum number of stored pixels is expressed by the following equation (1).

Maximum number of storage pixels ≒ Image horizontal size x Search area vertical size /
(Temporary setting memory bank number-number of access candidates + 1)
... (1)

  Strictly speaking, the maximum number of pixels to be stored can be obtained by dividing the number of pixels up to the pixel immediately before the access candidate P0 and the access candidate P1 by the number of pixels that can be switched outside the access candidate position + 1. In the normal case, the above-described equation (1) is used. Strictly speaking, the maximum number of stored pixels is expressed by Expression (2).

Maximum number of storage pixels = horizontal size of image x vertical size of search area-number of pixels outside count /
(Temporary setting memory bank number-number of access candidates + 1)
... (2)

  The horizontal size of the image × the vertical size of the search area−the number of pixels outside the count represents the number of pixels up to the pixel immediately before the access candidate P0 and the access candidate P1, and the number of pixels outside the count is the horizontal size × search. Of the vertical size of the area, the pixels (3 + 64) after the access candidate P1 are represented in the raster scan order.

  That is, strictly speaking, the maximum number of stored pixels is obtained by equally dividing the number of pixels included in the horizontal size of the image × the vertical size of the search area by the number of pixels to be switched other than the access candidate position + 1. Using (2), it is obtained as 286.5 (= 80 × 8− (64 + 3) / (5-4 + 1)).

  As described above, the data for 320 pixels including the pixel of the access candidate P0 is stored in the memory bank BK0. The 321st pixel (the 5th pixel from the top left of the search area SR) including the access candidate P0 Q0 is stored in the memory bank BK0 even if it is determined not to match the access candidate. Since the number of pixels exceeds the maximum storage pixel number of 320 pixels, the data from the pixel Q0 is stored in the next memory bank BK1.

  The next memory bank BK1 stores data of 253 (= 80 × 3 + 16−3) pixels from the pixel Q0 to the pixel immediately before the access candidate P1, and the memory bank BK2 stores 1 of the access candidate P1. Pixel data is stored, and data for one pixel of the access candidate P2 is stored in the memory bank BK3.

  The memory bank BK4 stores 2625 (= 80 × 40− (80 × 8 + 13)) pixels, which are all remaining pixels from the access candidate P3. Note that the maximum number of stored pixels is not applied to the last memory bank BK.

  FIG. 38 is a diagram illustrating an example of the access patterns of FIGS. 24 to 26 when the number of temporarily set memory banks is 5. In the example of FIG. 38, the number of the memory bank BK corresponding to the pixel is omitted.

  In the example of FIG. 38, the access patterns AP1 to AP3 shown in FIG. 24 to FIG. 26 are shown in order from the left, and the number of temporarily set memory banks is 5. Therefore, as in the example of FIG. The memory bank BK is switched when the position of the access candidate or the distance between the access candidates (that is, the maximum number of stored pixels) exceeds 320 pixels.

  First, as in the example of FIG. 24, the access pattern AP1 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR, and the second from the first left from the top of the search area SR. The access candidate P1 set to the th pixel, the access candidate P2 set to the second pixel from the right from the top of the search area SR, and the eighth pixel from the right to the first pixel from the top of the search area SR The access candidate P3 is set.

  One pixel of the access candidate P0 is stored in the memory bank BK0. Data for 320 pixels including the access candidate P1 is stored in the memory bank BK1. The 321st pixel (the fifth pixel from the top left of the search area SR from the left) Q0 including the access candidate P1 is stored in the memory bank BK1 even if it is determined not to match the access candidate. Since the number of processed pixels exceeds the maximum number of stored pixels of 320, the data from the pixel Q0 is stored in the next memory bank BK2.

  The next memory bank BK2 stores data of 253 (= 80 × 3-1 + 16-2) pixels from the pixel Q0 to the pixel immediately before the access candidate P2, and the memory bank BK3 stores the access candidate P1. 1 pixel data is stored, and 2625 (= 80 × 40− (80 × 8 + 13)) pixels which are all remaining pixels from the access candidate P3 are stored in the memory bank BK4.

  Next, as in the example of FIG. 25, the access pattern AP2 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR, and the first left from the top of the search area SR. The access candidate P1 set for the second pixel, the access candidate P2 set for the third pixel from the left from the top of the search area SR, and the eighth pixel from the right for the eighth from the top of the search area SR It is comprised by the access candidate P3 set to.

  One pixel of the access candidate P0 is stored in the bank BK0. One pixel of the access candidate P1 is stored in the memory bank BK1. The data for 320 pixels including the access candidate P2 is stored in the memory bank BK2. The 321st pixel (third pixel from the top left in the search area SR) Q0 including the access candidate P2 in the raster scan order is stored in the memory bank BK2 even if it is determined not to match the access candidate. Since the number of pixels that are stored exceeds the maximum number of stored pixels of 320, the data from the pixel Q0 is stored in the next memory bank BK3.

  The next memory bank BK3 stores data of 253 (= 80 × 3-2 + 16-1) pixels from the pixel Q0 to the pixel immediately before the access candidate P3, and the memory bank BK3 stores the access candidate P1. 1 pixel data is stored, and 2625 (= 80 × 40− (80 × 8 + 13)) pixels which are all remaining pixels from the access candidate P3 are stored in the memory bank BK4.

  Finally, as in the example of FIG. 26, the access pattern AP3 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR and the first left from the top of the search area SR. The access candidate P1 set to the second pixel, the access candidate P2 set to the third pixel from the left from the top of the search area SR, and the first pixel from the left to the top of the search area SR It is comprised by the access candidate P3 set to.

  One pixel of the access candidate P0 is stored in the memory bank BK0. One pixel of the access candidate P1 is stored in the memory bank BK1. One pixel of the access candidate P2 is stored in the memory bank BK2. The data for 320 pixels including the access candidate P3 is stored in the memory bank BK3. The 321st pixel (the 5th pixel from the top left of the search area SR from the left) Q0 including the access candidate P3 is stored in the memory bank BK3 even if it is determined not to match the access candidate. Since the number of processed pixels exceeds 320, which is the maximum number of stored pixels, data from the pixel Q0 is stored in the next memory bank BK4.

  In the next memory bank BK4, 2877 (= 80 × 40− (80 × 4 + 3)) pixels, which are all the remaining pixels, are stored from the pixel Q0.

  As described above, considering all the worst cases of the required memory amounts of the memory banks BK0 to BK4, it is necessary to store data of 4157 (= 320 × 4 + 2877) pixels as a whole.

  Therefore, when the image size is 40 pixels in the vertical direction and 80 pixels in the horizontal direction, the memory amount is only 4157 / (80 × 40) = 1.29. Therefore, FIG. 23 to FIG. 26, the amount of memory is reduced from the amount of memory corresponding to about 1.54 when the number of memory banks having the number of access candidates described above is used.

  FIG. 39 is a diagram illustrating an example of an initial arrangement of image data in each memory bank when the access pattern AP0 of FIG. That is, the case where the number of temporarily set memory banks is increased by one from the case of the example of FIG. 37 is shown.

  That is, as in the example of FIG. 23, this access pattern AP0 is the access candidate P0 set to the first pixel from the first left from the top of the search area SR and the eighth right from the top of the search area SR. The access candidate P1 set for the third pixel, the access candidate P2 set for the second pixel from the right from the top of the search area SR, and the eighth pixel from the top right of the search area SR It is comprised by the access candidate P3 set to.

  In the example of FIG. 37, the position of the access candidate or the distance between access candidates (that is, the maximum number of stored pixels) obtained using Expression (1) is 213 (= 80 × 8 / (6-4 + 1). )) Banks are switched when the number of pixels is exceeded. In this case as well, strictly speaking, the maximum number of pixels to be stored is obtained as 191 (= 80 × 8− (64 + 3) / (6-4 + 1)) using Expression (2).

  Therefore, the memory bank BK0 stores data for 213 pixels including the pixel of the access candidate P0. Even if it is determined that the 214th pixel (the third pixel from the top third in the search area SR from the left) Q0 including the pixel of the access candidate P0 in the raster scan order does not match the access candidate, the memory bank BK0 Since the number of pixels stored in exceeds the maximum number of stored pixels of 213, the data from the pixel Q0 is stored in the next memory bank BK1.

  The next memory bank BK1 stores data for 213 pixels including the pixel Q0. The 214th pixel (the sixth pixel from the top left in the search area SR and the 26th pixel from the left) Q1 including the pixel Q0 is stored in the memory bank BK1 even if it is determined that it does not match the access candidate. Since the number of pixels exceeds 213 pixels, which is the maximum storage pixel number, the data from the pixel Q1 is stored in the next memory bank BK2.

  The next memory bank BK2 stores data of 148 (= 80 × 2-25 + 16-3) pixels from the pixel Q1 to the pixel immediately before the access candidate P1, and the memory bank BK3 stores the access candidate P1. 1 pixel data is stored, and the memory bank BK4 stores 1 pixel data of the access candidate P2.

  The memory bank BK5 stores 2625 (= 80 × 40− (80 × 8 + 13)) pixels, which are all remaining pixels from the access candidate P3.

  Although the illustration of the access patterns AP1 to AP3 when the number of temporarily set memory banks is 6 is omitted, in summary, when the number of temporarily set memory banks is 6 in the access pattern AP1, the memory bank BK0 includes One pixel of the access candidate P0 is stored, and data for 213 pixels including the access candidate P1 is stored in the memory bank BK2.

  The memory bank BK3 stores data for 213 pixels including the 214th pixel (the third pixel from the left from the top of the search area SR) Q0 in the raster scan order including the access candidate P1. The memory bank BK4 includes 148 pixels from the 214th pixel (sixth pixel from the top left of the search area SR to the 27th pixel from the left) Q1 including the pixel Q0 to the pixel immediately before the access candidate P2. (= 80 × 2−26 + 16−2) Pixel data is stored.

  The memory bank BK4 stores data for one pixel of the access candidate P2, and the memory bank BK5 stores 2625 (= 80 × 40− (80 × 8 + 13)) pixels that are all the remaining pixels from the access candidate P3. Is done.

  Similarly, in the access pattern AP2, when the number of temporarily set memory banks is 6, one pixel of the access candidate P0 is stored in the memory bank BK0, and one pixel of the access candidate P1 is stored in the memory bank BK1. The memory bank BK2 stores data for 213 pixels including the access candidate P2.

  The memory bank BK3 stores data for 213 pixels including the 214th pixel (third pixel from the top left of the search area SR from the left) Q0 in the raster scan order including the access candidate P2. The memory bank BK4 includes 148 pixels from the 214th pixel (the 6th pixel from the top left of the search area SR to the 28th pixel from the left) Q1 including the pixel Q0 to the pixel immediately before the access candidate P3. Data of (= 80 × 2-27 + 16-1) pixels is stored.

  The memory bank BK5 stores 2625 (= 80 × 40− (80 × 8 + 13)) pixels, which are all remaining pixels from the access candidate P3.

  Further, in the access pattern AP3, when the temporarily set memory bank number is 6, one pixel of the access candidate P0 is stored in the memory bank BK0, and one pixel of the access candidate P1 is stored in the memory bank BK1. The memory bank BK2 stores one pixel of the access candidate P2, and the memory bank BK3 stores data of 213 pixels including the access candidate P3.

  The memory bank BK4 stores data for 213 pixels including the 214th pixel (the third pixel from the top left of the search area SR, the 56th pixel from the left) Q0 in the raster scan order including the access candidate P3. The memory bank BK5 includes all the remaining pixels 2772 (= 80 × 40) from the 214th pixel (the sixth pixel from the top left in the search area SR to the 29th pixel) Q1 in the raster scan order including the pixel Q0. − (80 × 5 + 28)) pixels are stored.

  As described above, considering all the worst cases of the required memory amounts of the memory banks BK0 to BK5, it is necessary to store data of 3837 (= 213 × 5 + 2772) pixels as a whole.

  Therefore, when the image size is 40 pixels vertically and 80 pixels horizontally, the memory amount is only 3837 / (80 × 40) = 1.19 sheets. 26, the amount of memory is reduced from the amount of memory corresponding to approximately 1.54 when the number of memory banks BK corresponding to the number of access candidates described above is used.

  Here, when the example described above with reference to FIG. 37 to FIG. 39 is generalized, the maximum number of pixels stored per memory bank in the case of the temporarily set memory bank number is obtained by Expression (1). The required memory amount is expressed by the following equation (3).

Necessary memory ≒ Maximum storage pixel number x (Temporary setting memory bank number-1)
+ Image horizontal size x Image vertical size-Maximum number of pixels stored in one bank x (Number of temporarily set memory banks-Number of access candidates)
-(Number of access candidates-1) (3)

  As described above, the required memory amount can be obtained according to the predetermined number of temporarily set memory banks.

  FIG. 40 is a diagram showing the relationship between the number of memory banks and the required memory amount.

  In the example of FIG. 40, the horizontal axis represents the number of memory banks (pieces), and the vertical axis represents the required memory amount (sheets: (number of images)).

  If the number of memory banks is 4, approximately 1.54 memory is required, and if the number of memory banks is 5, approximately 1.29 memory is required. If the number of memory banks is 6, approximately 1.19 memory amounts are required. In addition, when the number of memory banks is 7, approximately 1.17 memory is required, and when the number of memory banks is 8, approximately 1.15 memory is required. In the case where the number of memory banks is 9, approximately 1.1 memory is required. Thereafter, when the number of memory banks is the number of search area pixels (128), the required memory amount gradually approaches 1 as the number of memory banks increases until the required memory amount becomes 1.

  In other words, even if the number of memory banks is increased unnecessarily, the address becomes enormous, the chip area increases, and the power consumption increases, but on the other hand, how to reduce the required amount of memory gradually Since the amount of memory decreases, it is desirable to determine the amount of memory where the amount of memory decreases.

  Since the number of memory banks and the necessary memory amount are in a trade-off relationship, the minimum necessary memory bank number can be obtained at that time by determining the memory amount.

  Next, the bank number setting process of the design apparatus 201 will be described with reference to the flowchart of FIG.

  For example, the designer inputs predetermined values (image size, search area size, number of access patterns, and number of memory banks that are use candidates) necessary for designing parameters of the data storage device 111 to the input unit 216. An operation is performed on a keyboard or the like to be input to the design apparatus 201. Note that a plurality of memory banks as use candidates are input.

  The storage pixel number calculation unit 231 inputs a predetermined value in response to the operation of the input unit 216, and temporarily sets the number of memory banks that are candidates for use in step S151. In step S152, the image size and search Based on the size of the area, the number of access patterns, and the temporarily set number of memory banks, the maximum number of stored pixels per memory bank is calculated, and the calculated maximum number of stored pixels is output to the memory amount calculation unit 232. .

  In step S153, the memory amount calculation unit 232 determines the temporarily set memory based on the maximum storage pixel number calculated by the storage pixel number calculation unit 231, the temporarily set memory bank number, the image size, and the access pattern number. The required memory amount in the case of the number of banks is calculated, and the calculated required memory amount and the temporarily set memory bank number are output to the bank number setting unit 233.

  In step S154, the stored pixel number calculation unit 231 determines whether or not the processing for all candidates has been completed. If it is determined that the processing for all candidates has not yet been completed, the processing returns to step S152. Then, the process for the next temporarily set memory bank number is executed.

  If it is determined in step S154 that the processing for all candidates has been completed, in step S155, the bank number setting unit 233 sets the plurality of temporarily set memory bank numbers as described above with reference to FIG. Based on the required amount of memory corresponding thereto, the amount of memory used in the data storage device 111 is set, and the number of memory banks corresponding to the set memory amount is set to the number of memory banks used in the data storage device 111. Set.

  As described above, based on the image size, the size of the search area, the number of access patterns, and the temporarily set number of memory banks, the maximum number of stored pixels per memory bank is calculated, and the calculated maximum number of stored pixels Based on the temporarily set memory bank number, image size, and access pattern number, the required memory amount for the temporarily set memory bank number is calculated, and the optimal one of the calculated required memory amounts is calculated. And the number of memory banks is set accordingly.

  Therefore, it is possible to design a data storage device in which the memory amount is reduced as a whole.

  Further, in the data storage device 111 designed in this way, it is possible to simultaneously access a desired plurality of pixels in all data by reducing the memory amount as a whole.

  According to the present invention, it is possible to reduce the amount of memory as a whole and simultaneously access a desired plurality of pixels in all data.

  The present invention can easily simultaneously acquire the pixel data of a plurality of pixels specified by the access pattern at each position where the access pattern access candidates are sequentially moved from the start position in the raster scan order. For example, the present invention can be applied to an apparatus that recognizes a specific data array and performs processing such as pattern recognition and motion detection.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  As shown in FIG. 35, a program recording medium for storing a program that is installed in a computer and is ready to be executed by the computer is a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only). Memory, DVD (Digital Versatile Disc), a magneto-optical disk, a removable medium 221 that is a package medium made of a semiconductor memory, a ROM 212 in which a program is temporarily or permanently stored, and a storage unit 218 It is comprised by the hard disk etc. which comprise. The program is stored in the program recording medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 219 which is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the program recording medium is not limited to the processing performed in time series in the order described, but is not necessarily performed in time series. Or the process performed separately is also included.

It is a figure which shows typically the structure of a general semiconductor memory. FIG. 2 is a diagram schematically showing a state where simultaneous access is not possible in the semiconductor memory of FIG. 1. It is a figure which shows the memory structure of a several memory bank. It is a figure which shows the pattern of 4 pixels which want to access simultaneously with respect to a certain image. It is a figure which shows typically the state which stored the pixel between access candidates in another memory bank for every pixel. It is a figure which shows typically the state which stored the pixel between access candidates in the same memory bank. It is the figure which showed typically the case where the movement of an access pattern exceeded between access pixels. It is a block diagram which shows the structural example of the data storage apparatus to which this invention is applied. It is a block diagram which shows the structural example of the data storage control part of FIG. It is a block diagram which shows the structural example of the data read-out storage control part of FIG. It is a figure which shows the example of an access pattern. It is a figure which shows the two-dimensional arrangement | sequence state in the initial arrangement | positioning to each memory bank of image data. It is a figure which shows the one-dimensional arrangement | sequence state in the initial arrangement | positioning to each memory bank of image data. It is a flowchart explaining the initial arrangement | positioning process of the data storage control part of FIG. It is a figure which shows typically the method of access to a word line and a bit line, and a re-storing. It is a figure which shows the two-dimensional arrangement | sequence state at the time of storing the data of the pixel of the access candidate in the initial arrangement | positioning of FIG. 12 in the next bank address. It is a figure which shows the one-dimensional arrangement | sequence state at the time of storing the data of the pixel of the access candidate in the initial arrangement | positioning of FIG. 13 in the next bank address. It is a figure which shows the access candidate when a search area moves 1 pixel in the raster scan order. It is a figure which shows the two-dimensional arrangement | sequence state at the time of storing the data of the pixel of the access candidate in FIG. 16 in the next bank address. It is a figure which shows the one-dimensional arrangement | sequence state at the time of storing the data of the pixel of the access candidate in FIG. 17 in the next bank address. It is a flowchart explaining the data re-storing control process of the data read-out storage control part of FIG. It is a flowchart explaining the address calculation process of step S26 of FIG. It is a figure which shows an access pattern in case the required memory amount of memory bank BK0 becomes a worst case. It is a figure which shows an access pattern in case the required memory amount of memory bank BK1 becomes a worst case. It is a figure which shows the access pattern in case the required memory amount of memory bank BK2 becomes a worst case. It is a figure which shows an access pattern in case the required memory amount of memory bank BK3 becomes a worst case. It is a block diagram which shows the other structural example of the data storage apparatus to which this invention is applied. It is a block diagram which shows the structural example of the data storage control part of FIG. FIG. 29 is a diagram showing an example of initial arrangement of image data in each bank in the case of the access pattern of FIG. FIG. 29 is a diagram showing an example of initial arrangement of image data in each bank in the case of the access pattern of FIG. It is a figure which shows the example of the initial arrangement | positioning to each bank of the image data in the case of another access pattern. FIG. 32 is a diagram schematically showing a configuration of a selector in the case of the access pattern of FIG. 31. It is an initial arrangement processing flowchart of the data storage control unit of FIG. It is a flowchart explaining the address calculation process of the initial storage of step S112 of FIG. It is a block diagram which shows the hardware structural example of the design apparatus to which this invention is applied. FIG. 36 is a block diagram illustrating a functional configuration example of the design apparatus of FIG. 35. FIG. 24 is a diagram illustrating an example of initial arrangement of image data in each bank when the access pattern in FIG. 23 and the number of temporarily set memory banks are five. FIG. 27 is a diagram illustrating an example of access patterns in FIGS. 24 to 26 when the number of temporarily set memory banks is five. FIG. 24 is a diagram showing an example of initial arrangement of image data in each bank when the access pattern of FIG. 23 and the number of temporarily set memory banks are six. It is a figure which shows the relationship between the number of memory banks, and a required memory amount. It is a flowchart explaining the bank number setting process of the design apparatus of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 Data storage device, 31 Memory, 32 Data storage control part, 33 Data read-out storage control part, 41 Counter, 42 Match determination part, 43 Flag production | generation part, 44 Bank address counter, 45 Bit line address counter, 46 Word line address counter , 47 address generation unit, 48 storage control processing unit, 111 data storage device, 121 data storage control unit, 122 selector setting unit, 123 selector, 141 pixel number determination unit, 142 address generation unit, 201 design device, 211 CPU, 212 ROM, 213 RAM, 216 input unit, 231 storage pixel number calculation unit, 232 memory amount calculation unit, 233 bank number setting unit

Claims (3)

In a design device for designing parameters of a data storage device that reads out a plurality of data at the same time by allocating data to a plurality of memory banks constituting the memory and storing the data,
The multiplication result of the vertical size of the accessible area at a time of the horizontal size and the data of the data shows a plurality of candidate number memory banks to be set candidates, a plurality of desired data to be read simultaneously Storage pixel number calculating means for calculating the maximum number of pixels stored in one memory bank by dividing by the addition result obtained by adding 1 to the difference in the number of access candidates constituting the access pattern;
Multiplication result and the addition result obtained by adding the multiplication result between the horizontal size and the vertical size of the data of one minus the number of the maximum pixel calculated from the plurality of candidate memory bank number by the stored pixel number finding means Is necessary for the memory by subtracting the result of multiplying the maximum number of pixels by the value obtained by subtracting the number of access candidates from the number of candidate memory banks and the value obtained by subtracting 1 from the number of access candidates. A memory amount calculating means for calculating a correct memory amount;
A design apparatus comprising: a bank number setting unit configured to set the number of memory banks in which the data is distributed and stored by the data storage device according to the memory amount calculated by the memory amount calculation unit. A design device for designing parameters of a data storage device that reads out a plurality of data simultaneously by distributing data to a plurality of memory banks constituting a memory and storing the data,
The multiplication result of the vertical size of the accessible area at a time of the horizontal size and the data of the data shows a plurality of candidate number memory banks to be set candidates, a plurality of desired data to be read simultaneously By dividing by the addition result obtained by adding 1 to the difference in the number of access candidates constituting the access pattern, the maximum number of pixels stored in one memory bank is calculated,
Number calculated the maximum pixel and the multiplication result of 1 and minus from said plurality of candidate memory bank number, from the addition result obtained by adding the multiplication result between the horizontal size and the vertical size of the data, the maximum number of pixels and By subtracting the result obtained by subtracting the number of access candidates from the number of candidate memory banks and the value obtained by subtracting 1 from the number of access candidates, the amount of memory required for the memory is calculated,
A design method including a step of setting the number of memory banks in which the data is distributed and stored by the data storage device according to the calculated amount of memory. In a data storage device that reads out a plurality of data simultaneously by allocating data to a plurality of memory banks constituting the memory,
The multiplication result of the vertical size of the accessible area at a time of the horizontal size and the data of the data shows a plurality of candidate number memory banks to be set candidates, a plurality of desired data to be read simultaneously The maximum number of pixels to be stored in one memory bank is calculated by dividing the difference of the number of access candidates constituting the access pattern by the addition result of 1, and the calculated maximum pixel number and the plurality of candidates From the multiplication result of the value obtained by subtracting 1 from the number of memory banks and the addition result obtained by adding the multiplication result of the horizontal size and vertical size of the data, the access candidate is calculated from the maximum number of pixels and the plurality of candidate memory banks. multiplication result between the value obtained by subtracting the number, and by subtracting the value minus 1. from the number of the access candidate, the calculated amount of memory required, depending on the amount of memory that is calculated And a memory consisting of a set number of memory banks,
When distributing the data to the set number of memory banks and storing the data, the data between the access candidates is stored in the same memory bank by the maximum number of pixels based on the access pattern and the maximum number of pixels. Data storage processing means to be initially arranged by
A data read storage processing means for reading out pixel data from each memory bank for data initially arranged on a memory composed of the set number of memory banks,
The data read storage processing unit reads pixel data from the memory bank, and one adjacent range determined based on a moving direction of the access pattern among ranges determined based on each position of access candidates of the access pattern A data storage device for storing the read pixel data in a memory bank in which the pixel data is stored.

Images