JP2006309602A - Data access device, data access method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate simultaneous acquisition of a plurality of pixel data corresponding to an access pattern at each setting position of the pattern. <P>SOLUTION: In the Kth (K=1 to 3) phase processing, a data storage control part 120 defines each pixel column of a picture as the repetition of the first to third pixel columns with the Kth pixel column as the first pixel column, and stores the pixel data of the first to third pixel columns in host memory banks BK0 to BK2. In the Kth phase processing, a data access control part 140 simultaneously reads the pixel data of 12 pieces of pixels to be specified by an access pattern ACP at each setting position of the pattern ACP from 12 pieces of low rank memory banks BK00 to BK03, BK10 to BK13 and BK20 to BK23, and when moving the setting position of the pattern ACP, executes the movement processing of the pixel data so that the pixel data of the 12 pieces of pixels to be specified by this can be respectively stored in those different low rank memory banks. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  In the present invention, a pattern of a plurality of pixels set on a predetermined screen is used as an access pattern, and the setting position of the access pattern is specified by the access pattern at each setting position sequentially moved in the pixel column direction from the start position. The present invention relates to a data access device, a data access method, a program, and a recording medium that simultaneously acquire pixel data of a plurality of pixels.

  Specifically, according to the present invention, pixel data of a plurality of pixels specified by the access pattern are stored in different memory banks at each setting position where the access pattern setting position is sequentially moved in the pixel column direction from the start position. The present invention relates to a data access device that facilitates simultaneous acquisition of the plurality of pixel data by allowing the plurality of pixel data to be accessed simultaneously.

  Conventionally, as shown in FIG. 29, the semiconductor memory MY has a structure in which a memory cell MC is accessed by designating a word line WL and a bit line BL, and the designated word line WL and the bit line BL intersect. Data stored in the memory cell MC at the position is read out. In the semiconductor memory MY having such a structure, a plurality of word lines WL share the same bit line BL. Therefore, as shown in FIG. 30, for example, when two word lines WL1 and WL2 are designated, the data of these word lines WL1 and WL2 are mixed and appear on the bit line BL. Cannot be accessed simultaneously.

  On the other hand, as shown in FIG. 31, the memory MY is divided into a plurality of memory banks BK0 to BKn-1, and a plurality of word lines WL are designated by designating different addresses to the memory banks BK0 to BKn-1. However, data of different word lines WL in the memory bank cannot be accessed simultaneously.

  In general, a plurality of data can be accessed at the same time either by storing the plurality of data in different memory banks or by storing the plurality of data on the same word line.

  Conventionally, processing such as pattern recognition and motion detection is performed by recognizing a specific data array included in input data. For example, data processing that includes a buffer memory that can store pixel data of several lines and that can output in units of pixels, and a plurality of processor elements that can process several bits of width data, and that can process data in parallel with the plurality of processor elements And a control information memory for storing matching reference data and control data, and each processor element of the data processor has a pixel center matrix of the pixel of interest addressed to itself in the image data output from the buffer memory. Whether the pixel data group is binarized using a threshold value, converted into target data divided into serial array bit widths that can be processed by the processor element, and whether the data matches the reference data in the control information memory in the same format Is determined (see, for example, Patent Document 1).

  Also, in the field of moving image processing, motion, that is, the motion direction and size (or speed) of an object in a temporally different image is used. For example, a motion compensation frame in high-efficiency encoding of an image Motion is used for inter-coding, parameter control by motion in a television noise reduction device using an inter-frame time domain filter, and the like. A block matching method is known as a motion detection method for obtaining motion. In the motion detection method for detecting motion in an image signal, the applicant of the present application generates (a) an integrated value table by a matching method for each relatively large block obtained by dividing the entire screen or a screen into a plurality of blocks. A step of extracting one or a plurality of candidate vectors for each relatively large block obtained by dividing an entire screen or a plurality of screens using an integrated value table; and (b) performing matching only on the candidate vectors. A two-step motion detection method that includes a step of detecting a motion vector for each pixel or relatively small block has been proposed. In this two-step motion detection method, any two or more pixel data in the screen are simultaneously read out in the two-step process of representative point matching and vector assignment in which image motion detection is performed by two-step method representative point matching. There is a need (see, for example, Patent Document 2).

JP 2003-203236 A JP 2001-61152 A

  Here, a plurality of pixel patterns are set as an access pattern on a predetermined screen in which pixel rows extending in the horizontal or vertical direction are sequentially arranged in the vertical or horizontal direction, and the setting position of the access pattern is set from the start position. Consider simultaneously acquiring pixel data of a plurality of pixels specified by an access pattern at each set position sequentially moved pixel by pixel in the pixel column direction.

  For example, as shown in FIG. 32, a pattern of four pixels IM1 to IM4 is set as an access pattern ACP on a screen SRN in which pixel columns extending in the horizontal direction are sequentially arranged in the vertical direction. Consider a case where the set position is moved in the pixel column direction from the start position. In this case, the pixel column direction is the horizontal direction, and the setting position of the access pattern ACP moves in the raster scan order. Further, “□” in FIG. 32 indicates one pixel, and the setting position of the access pattern ACP in FIG. 32 indicates the start position.

  It is assumed that the pixel data of each pixel column on the screen SRN is stored in the four memory banks BK0 to BK3 in the raster scan order as shown in FIG. The numbers in the squares in FIG. 33 indicate the bank addresses 0-3. In this case, when the setting position of the access pattern ACP is at the start position, as shown in FIG. 34, the pixel data of the four pixels IM1 to IM4 specified by this access pattern ACP are stored in the memory banks BK0 to BK3. Since it is stored at the address position indicated by the mark, it is possible to simultaneously access and read the four pixel data.

  Until the set position of the access pattern ACP moves one pixel at a time from the start position to 9 pixels, four pixel data can be simultaneously accessed and read out as in the case where the set position is at the start position. it can. However, as shown in FIG. 35, when the set position of the access pattern ACP moves by 10 pixels, the pixel data of the four pixels IM1 to IM4 specified by the access pattern ACP are stored in the memory bank as shown in FIG. Since it is stored in the address positions indicated by ◯ in BK0 to BK3 and it is necessary to access data of a plurality of word lines in the memory bank BK1, four pixel data can be accessed and read simultaneously. Disappear.

  It has been proposed that a plurality of pixel data corresponding to an access pattern is accessed in a time-sharing manner and temporarily stored in a cache or buffer to achieve apparent simultaneous access (Japanese Utility Model Publication No. 63-35146). And Japanese Utility Model Laid-Open No. 8-896), there is a problem that a time delay occurs.

  An object of the present invention is to easily obtain pixel data of a plurality of pixels specified by the access pattern at each setting position where the setting position of the access pattern is moved in the pixel column direction from the start position. Is to make it.

The concept of this invention is
A memory unit comprising a lower memory bank specified by a lower bank address, and having a plurality of upper memory banks specified by an upper bank address;
A pixel in each pixel column in a predetermined screen in which pixel columns extending horizontally or vertically are sequentially arranged in a vertical or horizontal direction is set as a target pixel in order, and pixel data of the target pixel is set to a plurality of pixels set on the predetermined screen. A data storage control unit that performs control for allocating and storing in the plurality of upper memory banks based on an access pattern that is a pixel pattern;
Control for simultaneously acquiring pixel data of a plurality of pixels specified by the access pattern from each of the plurality of upper memory banks at each setting position where the setting position of the access pattern is moved in the pixel column direction from the start position. A data access control unit to perform,
The data storage control unit
It is assumed that first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and each pixel column on the predetermined screen is Kth in the Kth (K = 1 to N) phase processing. And the first to Nth pixel columns are repeated, and the pixel data of the first to Nth pixel columns are stored in the first to Nth upper memory banks, respectively. Shall be
When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank at the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position. (K-1) Based on a plurality of pixels specified by an access pattern set at a position shifted by a pixel, when a target pixel in the Mth pixel column first corresponds to any of the plurality of pixels, When the pixel data of the pixel of interest starts to be stored in the first lower memory bank of the Mth upper memory bank, and then the pixel of interest in the Mth pixel column corresponds to any of the plurality of pixels , Sequentially switching lower memory banks of the Mth upper memory bank for storing pixel data of the target pixel,
The data access control unit
The first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and in the Kth (K = 1 to N) phase processing, in the direction orthogonal to the pixel column direction from the start position. (K-1) The position shifted by the pixel is set as the first set position, and each time the movement for one column is finished, the column moves to the beginning of the column shifted by N pixels, and each of the access patterns sequentially moved in the pixel column direction At the set position, pixel data of a plurality of pixels specified by the access pattern are simultaneously read from the lower memory banks constituting the first to Nth upper memory banks, and the set position is moved in the pixel column direction. In this case, each upper memory bank is read from a predetermined lower memory bank so that pixel data of a plurality of pixels specified by the access pattern at the set position is stored in different lower memory banks. Certain pixel data in the data access device, characterized in that stored in the previous lower memory banks of the lower memory bank pixel data has been stored.

  In the present invention, pixels of each pixel column in a predetermined screen in which pixel columns extending in the horizontal or vertical direction are sequentially arranged in the vertical or horizontal direction are set as the target pixels in order, and the pixel data of the target pixel is a plurality of higher-order pixels. Sorted and stored in memory banks.

  For example, the data storage control unit sets the target pixel at a position shifted by (K−1) pixels in the direction orthogonal to the pixel column direction from the start position during the K-th (K = 1 to N) phase processing. A matching determination unit that determines whether or not the pixel matches a plurality of pixels specified by the access pattern, a counting unit that counts the first pixel in the pixel row from the beginning of the pixel column, An address generation unit that generates a write address for the memory unit for each target pixel based on the determination output of the coincidence determination unit and the count value of the count unit during the K phase processing.

  In this case, at the time of the K-th phase processing, each pixel column on the predetermined screen is a repetition of the first to N-th pixel columns with the K-th pixel column as the first pixel column. The pixel column data is stored in the first to Nth upper memory banks, respectively.

  When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank in the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position (K -1) When the target pixel in the Mth pixel column first corresponds to any of the plurality of pixels based on the plurality of pixels specified by the access pattern set at the position shifted by the pixel, the pixel of the target pixel Data is stored in the first lower memory bank of the Mth upper memory bank. Thereafter, when the target pixel of the Mth pixel column corresponds to any of the plurality of pixels, the lower memory bank of the Mth upper memory bank that stores the pixel data of the target pixel is switched.

  In the present invention, the pixel data of a plurality of pixels (access pixels) specified by the access pattern is received from a plurality of upper memory banks at each setting position where the setting position of the access pattern is moved in the pixel column direction from the start position. Acquired at the same time.

  For example, the data access control unit includes a read address generation unit that generates read addresses of lower memory banks constituting the first to Nth upper memory banks during the Kth phase processing, and first to first data during the Kth phase processing. A write address generation unit that generates a write address of a lower memory bank constituting the Nth upper memory bank.

  Then, the read address generation unit sets the first read address to the read start address given from the outside for each of the lower memory banks constituting the first to Nth upper memory banks, and sets the pixel at each setting position. When data is read, the read address is incremented to generate the next read address. The write address generation unit sets the first write address to the write start address given from the outside for each of the lower memory banks constituting the first to Nth upper memory banks, and sets the pixel at each setting position. When data is written, the write address is incremented to generate the next write address.

  In this case, at the time of the K-th phase processing, a position shifted by (K−1) pixels in the direction orthogonal to the pixel column direction from the start position is set as the first set position, and N pixels are obtained each time movement for one column is completed. The pixel data of a plurality of pixels specified by this access pattern form the first to Nth upper memory banks at each setting position of the access pattern moved to the head of the shifted column and sequentially moved in the pixel column direction. Are simultaneously read from the lower memory bank.

  Then, when this set position moves in the pixel column direction, the pixel data of the plurality of pixels specified by the access pattern at the set position are stored in different lower memory banks, for each upper memory bank, The pixel data read from a predetermined lower memory bank is subjected to pixel data movement processing for storing the pixel data in the lower memory bank immediately preceding the lower memory bank in which the pixel data was stored.

  As described above, the pixel data of the plurality of pixels specified by the access pattern are stored in different lower memory banks at the setting positions where the access pattern setting position is sequentially moved in the pixel column direction from the start position. The plurality of pixel data can be accessed simultaneously, and the plurality of pixel data can be easily acquired simultaneously.

  Further, each of the pixel data of the first to Nth pixel columns is distributed and stored in the first to Nth upper memory banks at the time of initial storage, and data movement processing is performed for each upper memory bank at the time of data access. In addition, it is possible to reduce pixel data movement processing during data access.

  For example, the pattern of a plurality of pixels is a pattern of a plurality of central pixels and peripheral pixels located around each central pixel. In this case, the number of pixels constituting the access pattern increases, but as described above, the pixel data of the first to Nth pixel columns are distributed and stored in the first to Nth upper memory banks. In addition, it is possible to reduce pixel data movement processing during data access.

  Further, for example, when a pixel group including a central pixel and peripheral pixels located around the central pixel extends over L pixel columns, N is set equal to L. In this case, during the K-th (K = 1 to N) phase processing, a plurality of access patterns specified by access patterns set at positions shifted by (K−1) pixels in the direction orthogonal to the pixel column direction from the start position Since the pixels are distributed in the first to Nth pixel columns, it is possible to reduce the required number of lower memory banks in each upper memory bank.

  Further, for example, the read start address and the write start address given to the data access control unit are given from the data storage control unit. In this case, the data storage control unit further includes a start address generation unit that generates a read start address and a write start address corresponding to each of the lower memory banks constituting the first to Nth upper memory banks. The address generation unit sets, for each memory bank, an address at which the first pixel data is stored as a read start address, and an address next to the address at which the last pixel data is stored as a write start address.

  As described above, by giving the read start address and the write start address from the data storage control unit to the data access control unit, for example, the control device that controls the data storage control unit and the data access control unit reads based on the access pattern. It is not necessary to generate a start address and a write start address and give them to the data access control unit.

  According to the present invention, pixel data of a plurality of pixels specified by the access pattern is stored in different memory banks at each setting position where the setting position of the access pattern is sequentially moved from the start position in the pixel column direction. The plurality of pieces of pixel data can be accessed simultaneously, and the plurality of pieces of pixel data can be easily acquired simultaneously.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a data access apparatus 100 as an embodiment.

  The data access device 100 includes a memory unit 110, a data storage control unit 120, and a data access control unit 140.

  Each of the memory units 110 includes three upper memory banks BK0 to BK2 that are specified by upper bank addresses. The upper memory bank BK0 is composed of four lower memory banks BK00 to BK03 each specified by a lower bank address. The upper memory bank BK1 is composed of four lower memory banks BK10 to BK13, each specified by a lower bank address. The upper memory bank BK2 is composed of four lower memory banks BK20 to BK23, each specified by a lower bank address. The memory unit 110 operates based on a control signal SCL given from a control device (not shown) via the input terminal 150.

  The memory unit 110 receives pixel data Di of a predetermined screen to be stored from the input terminal 111 at the time of initial storage. Here, the predetermined screen has a configuration in which pixel columns extending in the horizontal direction are sequentially arranged in the vertical direction, and pixel data of each pixel column is sequentially input to the memory unit 110 as a target pixel in the raster scan order. . A plurality of pixel patterns are set as an access pattern ACP on the predetermined screen. The pixel data of the target pixel is distributed and stored in the three upper memory banks BK0 to BK2 of the memory unit 110 based on the access pattern ACP.

  FIG. 2 shows an access pattern ACP set on the screen SRN in this embodiment. This access pattern ACP is a pattern of four central pixels IM1 to IM4 and eight peripheral pixels IM1U, IM1D, IM2U, IM2D, IM3U, IM3D, IM4U, and IM4D positioned above and below each central pixel. “□” in FIG. 2 indicates pixels constituting the screen SRN. Further, the setting position of the access pattern ACP shown in FIG. 2 is its start position.

  Further, at the time of data access, the 12 positions specified in the access pattern ACP (hereinafter referred to as appropriate) at each setting position in which the setting position of the access pattern ACP is moved by one pixel in the pixel column direction from the start position (see FIG. 2). Pixel data Do01 to D12 (referred to as “access pixels”) are simultaneously read from the lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 constituting the upper memory banks BK0 to BK2 and output to the output terminal 112. Is done. The pixel data Do01 to Do12 read out at each setting position in this way are re-input to the memory unit 110 for data movement processing to other lower memory banks.

  The data storage control unit 120 operates based on a control signal SCL supplied from a control device (not shown) via the input terminal 150. As described above, the data storage control unit 120 performs control for distributing and storing the pixel data of each target pixel in the three upper memory banks BK0 to BK2 of the memory unit 110.

  The data storage control unit 120 sequentially performs the first to third phase processes. Then, the data storage control unit 120, in the K-th (K = 1 to 3) phase processing, sets each pixel column on the screen SRN as the first pixel column to the first pixel column with the Kth pixel column as the first pixel column. Assuming that the column is repeated, the data of the first to third pixel columns are stored in the upper memory banks BK0 to BK2, respectively.

  When storing the pixel data of the Mth (M = 1 to 3) pixel columns in the Mth upper memory bank during the Kth phase processing, the data storage control unit 120 is orthogonal to the pixel column direction from the start position. Attention of the Mth pixel column based on 12 pixels (hereinafter referred to as “initial access pixels” as appropriate) specified by the access pattern ACP set at a position shifted by (K−1) pixels in the direction of When the pixel first corresponds to one of the 12 initial access pixels, the pixel data of the pixel of interest is started to be stored in the first lower memory bank of the Mth upper memory bank. Thereafter, when the target pixel in the Mth pixel column corresponds to any of the plurality of pixels, the lower memory bank of the Mth upper memory bank that stores the pixel data of the target pixel is switched.

  The data storage control unit 120 will be described in further detail. FIG. 3 shows the configuration of the data storage control unit 120. The data storage control unit 120 includes a counter (counter A) 121, a counter (counter B) 122, a match determination unit 123, an upper bank address counter 124, a lower bank address counter 125, and a bit line address counter 126. A word line address counter 127 and an address generation unit 128.

  The counter (counter A) 121 counts the number of input pixel data of each pixel of interest that is sequentially input to the memory unit 110 during the K-th (K = 1 to 3) phase processing. The counter 121 is supplied with a data clock DCK synchronized with the pixel data of each pixel of interest input to the memory unit 110. The data clock DCK constitutes one of the control signals SCL described above and is supplied from a control device (not shown). The counter 121 is initially set to 0, and thereafter incremented by the data clock DCK each time pixel data of each pixel of interest is input to the memory unit 110.

  When the pixel data of a predetermined pixel of interest is input to the memory unit 110 described above during the K-th phase processing, the coincidence determination unit 123 causes the pixel of interest to be in a direction orthogonal to the pixel column direction from the start position ( K-1) It is determined whether or not it matches the 12 initial access pixels specified by the access pattern ACP set at the position shifted by the pixel. For this reason, the match determination unit 123 receives the count values CN1 to CN12 output from the counter 121 when the target pixel becomes the 12 initial access pixels in each of the first to third phase processes. A value corresponding to is supplied as access pattern information IAP. This access pattern information IAP constitutes one of the control signals SCL described above, and is supplied from a control device (not shown). When the count value of the counter 121 at a certain target pixel matches the count values CN1 to CN12, the match determination unit 123 determines that the target pixel is the first to twelfth initial access pixel.

  The counter (counter B) 122 counts the number of pixels from the beginning of the pixel column of the pixel of interest. The counter 122 is supplied with a data clock DCK synchronized with the pixel data of each pixel of interest input to the memory unit 110. The counter 122 initially has a count value of 0, and thereafter is incremented by the data clock DCK every time pixel data of each pixel of interest is input to the memory unit 110. Each time the count value becomes equal to the number m of pixels in the pixel column (22 in this embodiment), the count value is reset to zero.

  The upper bank address counter 124 outputs a count value indicating the upper memory bank in which the pixel data of the pixel of interest should be stored, that is, the upper bank address, among the three upper memory banks BK0 to BK2. The counter 124 is supplied with the count value of the counter (counter B) 122 described above. The counter 124 is initially incremented when the count value of the counter 122 is reset to 0 after the count value is set to 0 and the target pixel becomes a pixel in the Kth and subsequent pixel columns. The counter 124 has a count value of 0 after the count value of 2, and is configured as a ternary counter. The count values 0 to 2 of the counter 124, that is, the upper bank addresses 0 to 2, indicate the upper memory banks BK0 to BK2, respectively.

The lower bank address counter 125 is a count value indicating a lower memory bank that actually stores pixel data of the pixel of interest among lower memory banks constituting the upper memory bank indicated by the count value of the upper bank address counter 124 described above. That is, the lower bank address is output. The counter 125 includes three counters 125 _{-0 to} 125 _-2 corresponding to the upper memory banks BK0 to BK2, respectively. The counter 125 is supplied with the determination output of the coincidence determination unit 123 and the count value (upper bank address) of the counter 124 described above.

These counters 125 _{-0 to} 125 _-2 are initially set to their count value, that is, the lower bank address is 0, and thereafter the upper bank address (count value of the counter 124) is 0 to 2, respectively. When the target pixel corresponds to the initial access pixel and is not the first initial access pixel at the upper bank address, the counter corresponding to the upper bank address is incremented.

  The bit line address counter 126 is composed of 12 counters respectively corresponding to the 12 lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 constituting the upper memory banks BK0 to BK2. The bit line address counter 126 is supplied with a data clock DCK synchronized with the pixel data of each pixel of interest input to the memory unit 110, and with the count values (bank addresses) of the counters 124 and 125.

  The twelve counters are initially set to the count value, that is, the bit line address is set to 0, and thereafter, every time pixel data of each pixel of interest is input and stored in the memory unit 110, The counter corresponding to the bank address is incremented. In this embodiment, the word line length of each lower-order memory bank is 10, and the 12 counters have a count value 0 after the count value 9 and have a decimal counter configuration. Here, the bank address includes a count value (upper bank address) of the counter 124 and a count value (lower bank address) of the counter in the counter 125 corresponding to the upper bank address.

  The word line address counter 127 is composed of 12 counters respectively corresponding to the 12 lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 constituting the upper memory banks BK0 to BK2. Each of the 12 counters is supplied with a carry CA that is a carry signal of 12 counters in the counter 126 described above. The twelve counters are incremented each time carry CA is supplied.

  The address generation unit 128 generates a write address W to be supplied to the memory unit 110. The address generation unit 128 is supplied with the count values of the counters 124 to 127. The address generation unit 128 combines the upper bank address, the lower bank address, the bit line address, and the word line address to generate a write address W to be supplied to the memory unit 110.

Here, the upper bank address is given by the count value of the counter 124. The lower bank address is given by the count value of the counter corresponding to the upper bank address among the counters 125 _{-0 to} 125 _-2 constituting the counter 125. The bit line address is given by the count value of the counter corresponding to the bank address (upper bank address and lower bank address) among the 12 counters constituting the counter 126. The word line address is given by the count value of the counter corresponding to the bank address (upper bank address and lower bank address) among the 12 counters constituting the counter 127.

  The address generator 128 generates a read start address RS and a write start address WS for each lower memory bank used in the data access controller 140. In this case, the address generation unit 128 uses the first write address W of each lower memory bank, that is, the address where the pixel data is first stored as the read start address RS, and the address next to the address where the last pixel data is stored. Is set as a write start address WS.

  Next, the operation at the time of initial storage (during the K-th phase process) under the control of the data storage control unit 120 shown in FIG. 3 will be described using the flowchart of FIG. The data storage control unit 120 is constituted by, for example, a microprocessor and performs a control operation according to a data storage control program stored in a program memory (not shown).

In step ST1, and starts operating, in step ST2, the count value of the higher bank address counter 124 (higher bank address), three counters 125 _-0 to 125 _-2 count value constituting the lower bank address counter 125 ( Lower bank address), the count values (bit line addresses) of the 12 counters constituting the bit line address counter 126, and the count values (word line addresses) of the 12 counters constituting the word line address counter 127 are each 0. The count values of the counter (counter A) 121 and the counter (counter B) 122 are set to 0, respectively.

  Next, in step ST3, it is determined whether pixel data of the target pixel has been input. In this case, when the data clock DCK is supplied, it is determined that the pixel data of the target pixel has been input. When it is determined that the pixel data of the target pixel has been input, the counter (counter A) 121 is incremented in step ST4, and the counter (counter B) 122 is incremented in step ST5.

  Next, in step ST6, the target pixel input in step ST3 is specified by the access pattern ACP set at a position shifted by (K-1) pixels in a direction orthogonal to the pixel column direction from the start position 12. The coincidence determination unit 123 determines whether the pixel is one of the initial access pixels. In this case, when the count value of the counter (counter A) 121 matches any of the count values CN1 to CN12 as the access pattern information IAP, it is determined that the target pixel is the initial access pixel.

  When it is determined that the target pixel is the initial access pixel, it is determined in step ST7 whether or not the initial access pixel is the first initial access pixel at the current upper bank address. The current upper bank address is given by the count value of the upper bank address counter 124.

  When it is determined that the pixel is the first initial access pixel, the process immediately proceeds to step ST10. On the other hand, when it is determined that the pixel is not the first initial access pixel, in step ST8, the write address W is set to the write start address WS of the lower memory bank corresponding to the bank address.

  Here, the bank address includes an upper bank address and a lower bank address. The upper bank address is given by the count value of the counter 124. The lower bank address is given by the count value of the counter in the counter 125 corresponding to the upper bank address. The write address W is generated by the address generator 128 by combining the bit line address and the word line address in addition to the bank address described above. The bit line address is given by the count value of the counter in the counter 126 corresponding to the bank address. The word line address is given by the count value of the counter in the counter 127 corresponding to the bank address.

  Next, in step ST9, the count value (lower bank address) of the counter in the counter 125 corresponding to the upper bank address is incremented. Thereafter, the process proceeds to step ST10. In step ST10, the write address W is set to the read start address RS of the lower memory bank corresponding to the bank address.

  Next, the process proceeds to step ST11. When it is determined in step ST6 that the target pixel is not the initial access pixel, it is determined in step ST12 whether the target pixel is a pixel after the first initial access pixel at the current upper bank address. When it is determined that the target pixel is a pixel after the first initial access pixel, the process immediately proceeds to step ST11. In this step ST11, based on the write address W generated by the address generation unit 128, specified by the bit line address and word line address of the write address W of the lower memory bank specified by the bank address of the write address W The pixel data of the target pixel is stored at the address position.

  Next, in step ST13, the count value (bit line address) of the counter corresponding to the bank address of the bit line address counter 126 is incremented. In step ST14, when the count value of the counter becomes 0 in step ST13, the count value (word line address) of the counter corresponding to the bank address of the word line address counter 127 is generated by the carry CA output from the counter. ) Is incremented. Thereafter, the process proceeds to step ST15.

  When it is determined in step ST12 that the target pixel is not a pixel after the first initial access pixel, the process immediately proceeds to step ST15. In step ST15, it is determined whether or not the count value of the counter (counter B) 122 is equal to the number of pixels m in the pixel column. When the count value is equal to m, it is determined in step ST16 whether or not the pixel of interest is a pixel in the Kth and subsequent pixel columns.

  When it is determined that the target pixel is a pixel in the Kth and subsequent pixel columns, the count value (upper bank address) of the upper bank address counter 124 is incremented in step ST17, and the process proceeds to step ST18. If it is determined that the target pixel is not a pixel in the Kth and subsequent pixel columns, the process immediately proceeds to step ST18. In step ST18, the counter (counter B) 122 is reset to 0, and then the process proceeds to step ST19.

  When the count value is not equal to m in step ST15 described above, the process immediately proceeds to step ST19. In this step ST19, it is determined whether or not the pixel data of all the pixels on the screen SRN has been input. In this case, when the count value of the counter (counter A) 121 is equal to the number of pixels constituting the screen SRN, it is determined that the pixel data of all the pixels has been input. When it is determined that the pixel data of all the pixels has been input, the operation ends in step ST20. On the other hand, when it is determined that the pixel data of all the pixels has not been input, the process returns to step ST3 and waits for the input of the pixel data of the next pixel of interest.

  By the operation at the time of initial storage described above, the data of each pixel of the screen SRN is distributed and stored in the upper memory banks BK0 to BK2.

  FIG. 5 shows the initial setting position of the access pattern ACP during the first phase processing. The initial setting position of the access pattern ACP is the start position of the setting position of the access pattern ACP. “□” in FIG. 5 indicates one pixel as in FIG. The same applies to the following similar figures. The numbers in the squares in FIG. 5 indicate which pixel column each pixel column is 0 to 2. In this case, in each pixel column in the screen SRN, the first pixel column is the first pixel column and the pixel columns 0 to 2 are repeated, and the pixel data of the pixel columns 0 to 2 are respectively Stored in the upper memory banks BK0 to BK2. Here, the pixel columns 0 to 2 constitute first to third pixel columns, respectively.

  FIG. 6 shows an initial storage state of pixel data of each pixel during the first phase processing. The numbers in the squares in FIG. 6 indicate the bank addresses of the lower memory banks in which the pixel data of the pixels are stored. Here, “00” to “03” indicate the lower memory banks BK00 to BK03 constituting the upper memory bank BK0, respectively. “10” to “13” indicate the lower memory banks BK10 to BK13 constituting the upper memory bank BK1, respectively. “20” to “23” indicate the lower memory banks BK20 to BK23 constituting the upper memory bank BK2, respectively.

  FIG. 7 shows an access pattern on the screen SRN related to the upper memory bank BK0 and pixel allocation to the lower memory banks BK00 to BK03. FIG. 8 shows the data storage state of the lower memory banks BK00 to BK03. Here, “■” indicates a memory cell MC in which pixel data is stored, and “□” indicates a memory cell MC in which pixel data is not stored. The same applies to the following drawings.

  FIG. 9 shows an access pattern on the screen SRN related to the upper memory bank BK1 and pixel allocation to the lower memory banks BK10 to BK13. FIG. 10 shows the data storage state of the lower memory banks BK10 to BK13. Further, FIG. 11 shows an access pattern on the screen SRN related to the upper memory bank BK2 and pixel allocation to the lower memory banks BK20 to BK23. FIG. 12 shows the data storage state of the lower memory banks BK20 to BK23.

  Initially, the upper bank address is “0”, and the lower bank address corresponding to each upper bank address is also “0”. In this state, the first pixel in the first column becomes the target pixel. This target pixel is not any of the twelve initial access pixels specified by the access pattern ACP, and is not a pixel after the first initial access pixel IM1U at the current upper bank address “0”. For this reason, the pixel data of the target pixel is not stored in the upper bank address BK0.

  Thereafter, the second pixel in the first column becomes the target pixel. The target pixel is the first initial access pixel IM1U at the current upper bank address “0”, and storage of pixel data from the pixel IM1U to the first lower memory bank BK00 constituting the upper memory bank BK0 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM1U is to be stored is used as the read start address RS of the lower memory bank BK00 (see bank BK00 in FIG. 8).

  After that, the pixel following this pixel IM1U becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK00. The ninth pixel in the first column is the second with the current upper bank address “0”. When this is the initial access pixel IM2U and this pixel IM2U is the target pixel, the lower bank address corresponding to the current upper bank address “0” is incremented to “1”, and the lower memory bank to store the pixel data is BK01.

  Therefore, the lower memory bank BK00 is in a state where pixel data of 7 pixels is stored (see the first seven address positions of the bank BK00 in FIG. 8). In this case, the write start address WS of the lower memory bank BK00 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of the seven pixels (see bank BK00 in FIG. 8). ).

  As described above, when the pixel IM2U becomes the target pixel, the lower memory bank to store the pixel data is BK01, and storage of the pixel data from the pixel IM2U to the lower memory bank BK01 constituting the upper memory bank BK0 is started. . In this case, the write address W indicating the address position where the pixel data of the pixel IM2U is to be stored is used as the read start address RS of the lower memory bank BK01 (see the bank BK01 in FIG. 8).

  Thereafter, the pixels following the pixel IM2U become the target pixel in order, and the pixel data is stored in the lower memory bank BK01. When the pixel data of the 22nd pixel in the first column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “1”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the second column becomes the target pixel. This target pixel is not any of the twelve initial access pixels specified by the access pattern ACP, and is not a pixel after the first initial access pixel IM1 at the current upper bank address “1”. For this reason, the pixel data of the target pixel is not stored in the upper bank address BK1.

  Thereafter, the second pixel in the second column becomes the target pixel. This target pixel is the first initial access pixel IM1 at the current upper bank address “1”, and storage of pixel data from this pixel IM1 to the first lower memory bank BK10 constituting the upper memory bank BK1 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM1 is to be stored is used as the read start address RS of the lower memory bank BK10 (see bank BK10 in FIG. 10).

  Thereafter, the pixel subsequent to the pixel IM1 becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK10. The ninth pixel in the second column is the second one at the current upper bank address “1”. When it is the initial access pixel IM2 and this pixel IM2 is the target pixel, the lower bank address corresponding to the current upper bank address “1” is incremented to “1”, and the lower memory bank to store the pixel data is BK11.

  Therefore, the lower memory bank BK10 is in a state where pixel data of 7 pixels is stored (see the first seven address positions of the bank BK10 in FIG. 10). In this case, the write start address WS of the lower memory bank BK10 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of the seven pixels (see the bank BK10 in FIG. 10). ).

  As described above, when the pixel IM2 is the target pixel, the lower memory bank to store the pixel data is BK11, and storage of the pixel data from the pixel IM2 to the lower memory bank BK11 constituting the upper memory bank BK1 is started. . In this case, the write address W indicating the address position where the pixel data of the pixel IM2 is to be stored is used as the read start address RS of the lower memory bank BK11 (see the bank BK11 in FIG. 10).

  After that, the pixel following this pixel IM2 becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK11. When the pixel data of the 22nd pixel in the second column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “2”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the third column becomes the target pixel. This target pixel is not any of the twelve initial access pixels specified by the access pattern ACP, and is not a pixel after the first initial access pixel IM1D at the current upper bank address “2”. Therefore, the pixel data of the target pixel is not stored in the upper bank address BK2.

  Thereafter, the second pixel in the third column becomes the target pixel. The target pixel is the first initial access pixel IM1D at the current upper bank address “2”, and storage of pixel data from the pixel IM1D to the first lower memory bank BK20 constituting the upper memory bank BK2 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM1D is to be stored is used as the read start address RS of the lower memory bank BK20 (see the bank BK20 in FIG. 12).

  Thereafter, the pixel following this pixel IM1D becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK20. The ninth pixel in the third column is the second pixel at the current upper bank address “2”. When it is the initial access pixel IM2D and this pixel IM2D becomes the target pixel, the lower bank address corresponding to the current upper bank address “2” is incremented to “1”, and the lower memory bank to store the pixel data is It becomes BK21.

  Therefore, the lower memory bank BK20 is in a state in which pixel data of 7 pixels is stored (see the first seven address positions of the bank BK20 in FIG. 12). In this case, the write start address WS of the lower memory bank BK20 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of the seven pixels (see bank BK10 in FIG. 12). ).

  As described above, when the pixel IM2D becomes the target pixel, the lower memory bank to store the pixel data is BK21, and storage of the pixel data from the pixel IM2D to the lower memory bank BK21 constituting the upper memory bank BK2 is started. . In this case, the write address W indicating the address position where the pixel data of the pixel IM2D is to be stored is used as the read start address RS of the lower memory bank BK21 (see the bank BK21 in FIG. 12).

  Thereafter, the pixels following this pixel IM2D become the target pixel in order, and the pixel data is stored in the lower memory bank BK21. When the pixel data of the 22nd pixel in the third column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the higher bank address is incremented to become “0” again, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the fourth column becomes the target pixel. The target pixel is a pixel after the first initial access pixel IM1U at the current upper bank address “0”. Therefore, storage of pixel data from this pixel to the lower memory bank BK01 constituting the upper memory bank BK0 is started again.

  Thereafter, the pixel following this pixel becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK01. When the pixel data of the 22nd pixel in the fourth column is stored, the counter 122 The count value B becomes equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “1”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the fifth column becomes the target pixel. The target pixel is a pixel after the first initial access pixel IM1 at the current upper bank address “1”. Therefore, storage of pixel data from this pixel to the lower memory bank BK11 constituting the upper memory bank BK1 is started again.

  Thereafter, the pixel following this pixel becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK11. The fifth pixel in the fifth column is the third initial initial value at the current upper bank address “1”. When the access pixel IM3U is the pixel of interest, the lower bank address corresponding to the current upper bank address “1” is incremented to “2”, and the lower memory bank to store the pixel data is BK12. It becomes.

  Therefore, the lower memory bank BK11 is in a state where pixel data of 18 pixels is stored (see the first 18 address positions of the bank BK11 in FIG. 10). In this case, the write start address WS of the lower memory bank BK11 is an address indicating the address position next to the address position where the last pixel data of the 18-pixel pixel data is stored (see bank BK11 in FIG. 10). ).

  As described above, when the pixel IM3U becomes the pixel of interest, the lower memory bank to store the pixel data is BK12, and storage of the pixel data from the pixel IM3U to the lower memory bank BK12 constituting the upper memory bank BK1 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM3U is to be stored is used as the read start address RS of the lower memory bank BK12 (see bank BK12 in FIG. 10).

  Thereafter, the pixel following this pixel IM3U becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK12. When the pixel data of the 22nd pixel in the fifth column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “2”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the sixth column becomes the target pixel. This pixel of interest is a pixel after the first initial access pixel IM1D at the current upper bank address “2”. Therefore, storage of pixel data from this pixel to the lower memory bank BK21 constituting the upper memory bank BK2 is started again.

  Thereafter, the pixel following this pixel becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK21. The fifth pixel in the sixth column is the third initial initial value at the current upper bank address “2”. When it is the access pixel IM3 and this pixel IM3 is the target pixel, the lower bank address corresponding to the current upper bank address “2” is incremented to “2”, and the lower memory bank to store the pixel data is BK22. It becomes.

  Therefore, the lower memory bank BK21 is in a state where pixel data of 18 pixels is stored (see the first 18 address positions of the bank BK21 in FIG. 12). In this case, the write start address WS of the lower memory bank BK21 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of 18 pixels (see bank BK21 in FIG. 12). ).

  As described above, when the pixel IM3 becomes the target pixel, the lower memory bank to store the pixel data is BK22, and storage of the pixel data from the pixel IM3 to the lower memory bank BK22 constituting the upper memory bank BK2 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM3 is to be stored is used as the read start address RS of the lower memory bank BK22 (see the bank BK22 in FIG. 12).

  Thereafter, the pixel following this pixel IM3 becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK22. When the pixel data of the 22nd pixel in the sixth column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the higher bank address is incremented to become “0” again, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the seventh column becomes the target pixel. The target pixel is a pixel after the first initial access pixel IM1U at the current upper bank address “0”. Therefore, storage of pixel data from this pixel to the lower memory bank BK01 constituting the upper memory bank BK0 is started again.

  Thereafter, the pixel following this pixel becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK01, but the fifth pixel in the seventh column is the third initial initial at the current upper bank address “0”. When the access pixel IM3D is the pixel of interest, the lower bank address corresponding to the current upper bank address “0” is incremented to “2”, and the lower memory bank to store the pixel data is BK02. It becomes.

  Therefore, the lower memory bank BK01 is in a state where pixel data of 40 pixels is stored (see the first 40 address positions of the bank BK01 in FIG. 8). In this case, the write start address WS of the lower memory bank BK01 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of 40 pixels (see the bank BK01 in FIG. 8). ).

  As described above, when the pixel IM3D becomes the target pixel, the lower memory bank to store the pixel data is BK02, and storage of the pixel data from the pixel IM3D to the lower memory bank BK02 constituting the upper memory bank BK0 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM3D is to be stored is used as the read start address RS of the lower memory bank BK02 (see the bank BK02 in FIG. 8).

  Thereafter, the pixel following this pixel IM3D becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK02. When the pixel data of the 22nd pixel in the seventh column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “1”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the eighth column becomes the target pixel. This pixel of interest is the fourth initial access pixel IM4U at the current upper bank address “1”, and the lower bank address corresponding to the current upper bank address “1” is incremented to “3”, and the pixel data is The lower memory bank to be stored is BK13.

  Therefore, the lower memory bank BK12 is in a state where pixel data of 18 pixels is stored (see the first 18 address positions of the bank BK12 in FIG. 10). In this case, the write start address WS of the lower memory bank BK12 is an address indicating the address position next to the address position where the last pixel data is stored among the pixel data of 18 pixels (see bank BK12 in FIG. 10). ).

  As described above, when the pixel IM4U becomes the target pixel, the lower memory bank to store the pixel data is BK13, and storage of the pixel data from the pixel IM4U to the lower memory bank BK13 constituting the upper memory bank BK1 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM4U is to be stored is used as the read start address RS of the lower memory bank BK13 (see the bank BK13 in FIG. 10).

  Thereafter, the pixels following this pixel IM4U become the target pixel in order, and the pixel data is stored in the lower memory bank BK13. When the pixel data of the 22nd pixel in the eighth column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “2”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the ninth column becomes the target pixel. The target pixel is the fourth initial access pixel IM4 at the current upper bank address “2”, and the lower bank address corresponding to the current upper bank address “2” is incremented to “3”, and the pixel data is The lower memory bank to be stored is BK23.

  For this reason, the lower memory bank BK22 is in a state where pixel data of 18 pixels is stored (see the first 18 address positions of the bank BK22 in FIG. 12). In this case, the write start address WS of the lower memory bank BK22 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of 18 pixels (see bank BK22 in FIG. 12). ).

  As described above, when the pixel IM4 becomes the target pixel, the lower memory bank to store the pixel data is BK23, and storage of the pixel data from the pixel IM4 to the lower memory bank BK23 constituting the upper memory bank BK2 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM4 is to be stored is used as the read start address RS of the lower memory bank BK23 (see bank BK23 in FIG. 12).

  Thereafter, the pixel following this pixel IM4 becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK23. When the pixel data of the 22nd pixel in the ninth column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to become “0” again, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the tenth column becomes the target pixel. The target pixel is the fourth initial access pixel IM4D at the current upper bank address “0”, and the lower bank address corresponding to the current upper bank address “0” is incremented to “3”, and the pixel data is The lower memory bank to be stored is BK03.

  Therefore, the lower memory bank BK02 is in a state where pixel data of 18 pixels is stored (see the first 18 address positions of the bank BK02 in FIG. 8). In this case, the write start address WS of the lower memory bank BK02 is an address indicating an address position next to the address position where the last pixel data is stored among the pixel data of 18 pixels (see bank BK02 in FIG. 8). ).

  As described above, when the pixel IM4D becomes the target pixel, the lower memory bank to store the pixel data is BK03, and storage of the pixel data from the pixel IM4D to the lower memory bank BK03 constituting the upper memory bank BK0 is started. In this case, the write address W indicating the address position where the pixel data of the pixel IM4D is to be stored is set as the read start address RS of the lower memory bank BK03 (see the bank BK03 in FIG. 8).

  Thereafter, the pixel following this pixel IM4D becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK03. When the pixel data of the 22nd pixel in the 10th column is stored, the counter 122 Is equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “1”, and the count value B of the counter 122 is also reset to “0”.

  In this state, the first pixel in the eleventh column becomes the target pixel. The target pixel is a pixel after the first initial access pixel IM1 at the current upper bank address “1”. Therefore, storage of pixel data from this pixel to the lower memory bank BK13 constituting the upper memory bank BK1 is started again.

  Thereafter, the pixel following this pixel becomes the target pixel in order, and the pixel data is stored in the lower memory bank BK03. When the pixel data of the 22nd pixel in the 11th column is stored, the counter 122 The count value B becomes equal to the number of pixels m (= 22) in the pixel column, the upper bank address is incremented to “2”, and the count value B of the counter 122 is also reset to “0”.

  Similarly, the pixel data is sequentially stored in the lower memory banks BK23, BK03, and BK13 sequentially for each pixel column, and the pixel data of all the pixels is stored (BK23 in FIG. 12, FIG. 12). 8 BK03, see FIG. 10 BK13).

  The above description using FIGS. 5 to 12 describes the initial storage operation during the first phase processing. Although detailed description is omitted, the initial storage operation during the second phase processing and the third phase processing is performed in the same manner.

  FIG. 13 shows the initial setting position of the access pattern ACP during the second phase processing. The initial setting position of the access pattern ACP is a position shifted by one pixel in the direction orthogonal to the pixel column direction from the start position. In this case, in each pixel column in the screen SRN, the second pixel column is the first pixel column and the pixel columns 0 to 2 are repeated, and the pixel data of the pixel columns 0 to 2 are respectively Stored in the upper memory banks BK0 to BK2. FIG. 14 shows an initial storage state of pixel data of each pixel in the lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 during the second phase processing.

  FIG. 15 shows the initial setting position of the access pattern ACP during the third phase processing. The initial setting position of the access pattern ACP is a position shifted by two pixels in the direction orthogonal to the pixel column direction from the start position. In this case, in each pixel column in the screen SRN, the third pixel column is the first pixel column, and the pixel columns 0 to 2 are repeated. The pixel data of the pixel columns 0 to 2 are respectively Stored in the upper memory banks BK0 to BK2. FIG. 16 shows an initial storage state of pixel data of each pixel in the lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 during the third phase processing.

  Returning to FIG. 1, the data access control unit 140 operates based on a control signal SCL supplied from a control device (not shown) via the input terminal 150. The data access control unit 140 has twelve access pixels IM1 to IM4, IM1U to IM4U specified by the access pattern ACP at each setting position where the setting position of the access pattern ACP is moved in the pixel column direction from the start position. Control is performed to simultaneously read out the pixel data of IM1D to IM4D from the three upper memory banks BK0 to BK2.

  The data access control unit 140 sequentially performs the first to third phase processes. Then, the data access control unit 140 sets a position shifted by (K−1) pixels in the direction orthogonal to the pixel column direction from the start position at the initial setting position during the K-th (K = 1 to 3) phase processing. (Initial setting position), each time the movement for one column is completed, the position is shifted to the top of the column shifted by 3 pixels, and each access pattern ACP is sequentially moved in the pixel column direction. The pixel data of 12 access pixels IM1 to IM4, IM1U to IM4U, IM1D to IM4D are divided into 12 lower memory banks BK00 to BK03, BK10 to BK13, BK20 to Read simultaneously from BK23.

  In addition, when the setting position of the access pattern ACP moves in the pixel column direction, the data access control unit 140 includes twelve access pixels IM1 to IM4, IM1U to IM4U specified by the access pattern ACP at the setting position. As the pixel data of IM1D to IM4D are stored in different lower memory banks, the pixel data read out from a predetermined lower memory bank for each upper memory bank is stored in the lower memory bank in which the pixel data is stored. Store in the previous lower memory bank.

  The data access control unit 140 will be described in further detail. FIG. 17 shows the configuration of the data access control unit 140. The data access control unit 140 includes a counter 141, an address counter control unit 142, a read address counter 143, a write address counter 144, a read address generation unit 145, and a write address generation unit 146.

  The counter 141 outputs a count value indicating the set position of the access pattern ACP. The counter 141 is supplied with a moving clock MCK for moving the set position of the access pattern ACP. The moving clock MCK constitutes one of the control signals SCL described above and is supplied from a control device (not shown). The counter 141 is first set to 0, and then incremented by the first moving clock MCK when the set position of the access pattern ACP is set as the start position, and then the count value becomes 1. Thereafter, the set position is set to the pixel. Each time the pixel moves in the column direction, it is incremented by the moving clock MCK.

  The read address counter 143 includes 12 counters corresponding to the 12 lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23, respectively. Each of the twelve counters includes a bit line address counter for obtaining a count value indicating a bit line address and a word line address counter for obtaining a count value indicating a word line address (in FIG. 3). (See bit line address counter 126 and word line address counter 127). The twelve counters in the counter 143 are read addresses (bit line addresses and word lines) for the twelve lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23, respectively, under the control of the address counter control unit 142. A count value indicating (address) is output.

  The write address counter 144 includes nine counters corresponding to the nine lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22, respectively. Each of the nine counters includes a bit line address counter for obtaining a count value indicating a bit line address and a word line address counter for obtaining a count value indicating a word line address. Under the control of the address counter control unit 142, the nine counters in the counter 144 are write addresses (bit line addresses and word lines) for the nine lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22, respectively. A count value indicating (address) is output.

  The address counter control unit 142 controls the operations of the read address counter 143 and the write address counter 144 described above. The address counter control unit 142 includes a movement clock MCK for moving the set position of the access pattern ACP and each of the lower memory banks BK00 to BK00 generated by the address generation unit 128 of the data storage control unit 120 described above. A read start address RS and a write start address WS are supplied to BK03, BK10 to BK13, and BK20 to BK23.

  The address counter control unit 142 first sets the read start address RS for each of the twelve lower-level memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 to the twelve counters in the counter 143, and nine Write start addresses WS for the lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22 are set in nine counters in the counter 144, respectively.

  Further, the address counter control unit 142 increments the 12 counters in the counter 143 every time pixel data is read at each setting position of the access pattern ACP, and each time pixel data is written. The nine counters in 144 are incremented.

  The read address generation unit 145 generates a read address R for each of the twelve lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23. The read address generation unit 145 is supplied with count values (bit line address and word line address) of each counter constituting the read address counter 143. The read address generation unit 145 combines the upper bank address and the lower bank address with the count values (bit line address and word line address) of each counter, respectively, so that the lower memory banks BK00 to BK03 and BK10 to BK13 are combined. , BK20 to BK23 are generated.

  The write address generator 146 generates a write address W for each of the nine lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22. The write address generation unit 146 is supplied with count values (bit line address and word line address) of each counter constituting the write address counter 144. The write address generation unit 146 combines the upper bank address and the lower bank address with the count values (bit line address and word line address) of each counter, respectively, so that the lower memory banks BK00 to BK02 and BK10 to BK12 are combined. , BK20 to BK22 are generated.

  Next, the operation at the time of data access (during the K-th phase process) under the control of the data access control unit 140 shown in FIG. 17 will be described using the flowchart of FIG. The data access control unit 140 is composed of, for example, a microprocessor, and performs a control operation according to a data access control program stored in a program memory (not shown).

  In step ST31, the operation is started. In step ST32, the address counter control unit 142 sets the read address R and the write address W. In this case, the count values (read addresses) of the twelve counters in the read address counter 143 are equal to the read start address RS at the time of the K-th phase process supplied from the data storage control unit 120, respectively. Set. The nine count values (write addresses) in the write address counter 144 are set to be equal to the write start address WS supplied from the data storage control unit 120 during the K-th phase process. .

  Next, in step ST33, the counter 141 is incremented by the moving clock MCK. In step ST34, the access pattern ACP is specified from the address position indicated by the read address R generated by the read address generator 145 in the 12 lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23. The pixel data Do01 to Do12 of the 12 access pixels IM1 to IM4, IM1U to IM4U, and IM1D to IM4D are read and output.

  In this case, the pixel data of the access pixels IM1U, IM2U, IM3D, and IM4D are read from the lower memory banks BK00, BK01, BK02, and BK03, respectively, and the access pixels IM1, UK11, BK12, and BK13 are accessed from the lower memory banks BK10, BK11, BK12, and BK13, respectively. Pixel data of IM2, IM3U, and IM4U are read out, and pixel data of access pixels IM1D, IM2D, IM3, and IM4 are read out from lower memory banks BK20, BK21, BK22, and BK23, respectively (FIGS. 7, 9, and FIG. 11).

  Next, in step ST35, the twelve counters in the read address counter 143 corresponding to the twelve lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 from which the pixel data has been read in step ST34 described above are stored. The count value (read address) is incremented.

  Next, in step ST36, pixel data read from a predetermined lower memory bank is stored in the previous lower memory bank for each upper memory bank. In this case, in the lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22, the lower memory banks BK01 to BK03, BK11 to BK13 are respectively located at the address positions indicated by the write address W generated by the write address generator 146. , Pixel data read from BK21 to BK23 are written.

  Next, in step ST37, the nine counters in the write address counter 144 corresponding to the nine lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22 to which the pixel data was written in step ST36 described above are stored. The count value (write address) is incremented.

  Next, in step ST38, it is determined whether or not all accesses have been made, that is, whether or not the access pattern ACP has moved from the initial setting position to the end position during the K-th phase processing. In this case, when the count value of the counter 141 is a value indicating the end position, it is determined that all have been accessed. If it is determined that all have been accessed, the operation is terminated in step ST39. If it is determined that all are not accessed, the process returns to step ST33, and the process proceeds to the process for the next set position of the access pattern ACP.

  Here, the initial setting position of the access pattern ACP at the time of the first phase processing is the start position (see FIG. 5). The initial setting position of the access pattern ACP at the time of the second phase processing is a position shifted by one pixel in the direction orthogonal to the pixel column direction from the start position (see FIG. 13). Furthermore, the initial setting position of the access pattern ACP at the time of the third phase processing is a position shifted by two pixels in the direction orthogonal to the pixel column direction from the start position (see FIG. 15).

  The operation at the time of data access will be further described. As described above, the pixel data of each pixel of the screen SRN is distributed and stored in the three upper memory banks BK0 to BK2 by the operation at the time of initial storage. FIG. 19 shows a state in which the access pattern ACP is at the start position (initial setting position at the time of the first phase process) during the first phase process. FIG. 20 shows only the part related to the upper memory bank BK0, for example, extracted from FIG.

  At the start of the operation during the first phase processing, the read address R and the write start address W of the lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 are set. In this case, the read addresses R of the twelve lower-level memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 are generated by the address generation unit 128 of the data storage control unit 120, and start of reading during the first phase processing. Set to the same address as the address RS. In this case, the write addresses W of the nine lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22 are generated by the address generation unit 128 of the data storage control unit 120 and written during the first phase processing. Set to the same address as the start address WS.

  FIG. 21 shows the data storage state of the memory banks BK00 to BK03 and the address positions of the read address R and the write address W in the initial state. Since the data storage states of memory banks BK10 to BK13 and BK20 to 23 and the address positions of read address R and write address W are the same as those of memory banks BK00 to BK03, their illustration is omitted. The same applies to the following states.

  When the count of the counter 141 is started and the setting position of the access pattern ACP is set to the start position as shown in FIG. 19, the 12 lower memory banks BK00 to BK03, BK10 to BK13, BK20 to BK23 From the address position indicated by the read address R, the pixel data Do01 to Do12 of the 12 access pixels IM1 to IM4, IM1U to IM4U, and IM1D to IM4D specified by the access pattern ACP at the start position are simultaneously read. Then, the read addresses R of the 12 lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 are respectively incremented.

  As shown in FIG. 22, the pixel data read from the lower memory banks BK01 to BK03, BK11 to BK13, BK21 to BK23 are stored in the previous lower memory banks BK00 to BK02, BK10 to BK12, BK20 to BK22. Writing is performed at an address position indicated by a write-in address W (movement of pixel data). Then, the write addresses W of the lower memory banks BK00 to BK02, BK10 to BK12, and BK20 to BK22 are respectively incremented.

  Thereafter, every time the setting position of the access pattern ACP moves one pixel in the pixel column direction (horizontal direction) in accordance with the input of the movement clock MCK, the 12 access pixels specified by the access pattern ACP are the same as described above. Pixel data Do01 to Do12 of IM1 to IM4, IM1U to IM4U, and IM1D to IM4D are read simultaneously, and processing for incrementing the read address R, moving the pixel data, and incrementing the write address W is performed.

  FIG. 23 shows a state in which the access pattern ACP has moved by one pixel during the first phase processing. FIG. 24 shows only the part related to the upper memory bank BK0, for example, extracted from FIG. Further, FIG. 25 shows the data storage state of the memory banks BK00 to BK03 and the address positions of the read address R and the write address W when the access pattern ACP is moved by one pixel.

  FIG. 26 shows a state in which the access pattern ACP has moved by 22 pixels during the first phase processing. FIG. 27 shows only the part related to the upper memory bank BK0, for example, extracted from FIG. Further, FIG. 28 shows the data storage state of the memory banks BK00 to BK03 and the address positions of the read address R and the write address W when the access pattern ACP is moved by 22 pixels.

  In this case, as shown in FIG. 26, the setting position of the access pattern ACP moves to the beginning of a column shifted by 3 pixels in the direction orthogonal to the pixel column direction from the start position. The data access operation for the column shifted by one pixel is performed during the second phase processing, and the data access operation for the column shifted by two pixels is performed during the third phase processing.

  Hereinafter, every time the access pattern ACP moves by 22 pixels, the setting position of the access pattern ACP moves to the top of the column shifted by 3 pixels in the direction orthogonal to the pixel column direction.

  The above description using FIGS. 19 to 28 describes the data access operation during the first phase processing. Although detailed description is omitted, the data access operation during the second phase processing and the third phase processing is performed in the same manner. By performing the data access operation during the first to third phase processes, the access pattern ACP is specified by the access pattern ACP at each setting position where the setting position of the access pattern ACP is moved in the pixel column direction from the start position. Pixel data Do01 to Do12 of 12 access pixels IM1 to IM4, IM1U to IM4U, and IM1D to IM4D can be simultaneously acquired from the three upper memory banks BK0 to BK2.

  Regarding the relationship between the processing times of the first to third phase processes of initial storage controlled by the data storage control unit 120 and the first to third phase processes of data access controlled by the data access control unit 140 The processing of each phase of initial storage and data access is performed alternately, or the processing of all phases of data access is performed after the processing of all phases of initial storage. However, if all phases of initial storage are performed together, three sets of upper memory banks BK0 to BK2 are required.

  According to the data access device 100 shown in FIG. 1, twelve access pixels IM1 to IM4 specified by the access pattern ACP at each setting position where the setting position of the access pattern ACP is sequentially moved from the start position in the pixel column direction. , IM1U to IM4U, and IM1D to IM4D are stored in different lower memory banks BK00 to BK03, BK10 to BK13, and BK20 to BK23 so that the 12 pixel data can be accessed simultaneously. Yes, simultaneous acquisition of the twelve pixel data can be easily performed.

  Further, according to the data access apparatus 100 shown in FIG. 1, each of the pixel data of the first to third pixel columns is distributed and stored in the upper memory banks BK0 to BK2 at the time of initial storage. Data movement processing is performed every time, and pixel data movement processing during data access can be reduced.

  For example, when the access pattern ACP is a pattern of 12 pixels as in the above-described embodiment, the pixel data of each pixel column is set in the 12 memory banks at the start position during initial storage. The pixel data of 12 pixels specified by the access pattern ACP is stored at the head, and the pixel data of 12 pixels specified by the access pattern is stored in 12 memory banks at the time of data access. In the case of performing the data movement processing as described above, 11 data movement processes are required as the data movement process. However, in the data access device 110 shown in FIG. (See FIG. 22), the three upper memory banks BK0 to BK2 require a total of nine transfer processes.

  Further, according to the data access device 100 shown in FIG. 1, the access pattern ACP is a pattern of four central pixels IM1 to IM4 and peripheral pixels IM1U to IM4U and IM1D to IM4D positioned above and below each central pixel. Although the number of pixels constituting the access pattern ACP is as large as twelve, as described above, each of the pixel data of the first to third pixel columns is distributed and stored in the three upper memory banks BK0 to BK2. In addition, data movement processing is performed for each upper memory bank during data access, and pixel data movement processing during data access can be reduced.

  Further, according to the data access device 100 shown in FIG. 1, the pixel group composed of the central pixel and the peripheral pixels positioned above and below it extends over three pixel columns, and as described above, the first to third pixels. By distributing and storing each of the pixel data of the columns in the three upper memory banks BK0 to BK2, the required number of lower memory banks in each upper memory bank is four, and the variation is suppressed.

  Further, according to the data access device 100 shown in FIG. 1, the data storage control unit 120 gives the data access control unit 140 the read start address RS and the write start address WS of each of the memory banks BK0 to BK5. The control device that controls the data storage control unit 120 and the data access control unit 140 generates the read start address RS and the write start address WS of each lower memory bank based on the information of the access pattern ACP, and the data access control unit 140 No need to give to.

  In the above-described embodiment, as shown in FIG. 2, the access pattern ACP includes four central pixels IM1 to IM4 and eight peripheral pixels IM1U, IM1D, IM2U positioned above and below each central pixel. Although it is a pattern of 12 pixels composed of IM2D, IM3U, IM3D, IM4U, and IM4D, it is not limited to this. For example, the number of center pixels is not limited to four, and the peripheral pixels may be positioned in the left, right, up, down, left, right, or diagonal directions instead of being positioned above and below the center pixel. May not be adjacent to the central pixel.

  In the above-described embodiment, the access pattern ACP is considered as a pattern in which the central pixel and the peripheral pixels are combined as shown in FIG. 2, but is not necessarily limited to a pixel pattern in which the central pixel and the peripheral pixels are combined. There is no need to consider it as That is, the present invention is effective when the number of pixels constituting the access pattern ACP is large, regardless of whether or not the access pattern ACP is a pixel pattern obtained by combining the central pixel and the peripheral pixels.

  In the above-described embodiment, each pixel column in the screen SRN is a repetition of the first to third pixel columns, and the pixel data of the first to third pixel columns are respectively stored in the upper memory banks BK0 to BK2. However, the number of upper memory banks is not limited to three. In general, when N (N is an integer of 2 or more) upper memory banks are used, it is assumed that each pixel column in the screen SRN is a repetition of the first to Nth pixel columns, and the first to Nth pixel columns. Pixel data is stored in the first to Nth upper memory banks, respectively. When the first to Nth upper memory banks are used in this way, the data storage control unit 120 and the data access control unit 140 perform the first to Nth phase processing, respectively.

  In the above-described embodiment, it is assumed that the screen SRN has a configuration in which pixel columns extending in the horizontal direction are sequentially arranged in the vertical direction, and during initial storage, the pixels in each pixel column are sequentially set as the target pixels. The pixel data is distributed and stored in each of the upper memory banks BK0 to BK2, and at the time of data access, the 12 positions of the 12 pixels specified by the access pattern ACP are set at each setting position where the setting position of the access pattern ACP is moved in the pixel column direction. Although the pixel data Do01 to Do12 are obtained at the same time, the screen SRN has a configuration in which pixel columns extending in the vertical direction are sequentially arranged in the horizontal direction and configured to perform operations during initial storage and data access. You can also

  In the above embodiment, the data storage control unit 120 gives the data access control unit 140 with the start addresses RS and WS. However, the data storage control unit 120 and the data access are provided with the start addresses RS and WS. A configuration may also be adopted in which the data access control unit 140 is given from a control device that controls the operation of the control unit 140.

  The present invention can easily simultaneously acquire pixel data of a plurality of pixels specified by the access pattern at each setting position where the access pattern setting position is sequentially moved in the pixel column direction from the start position. For example, the present invention can be applied to an apparatus that recognizes a specific data array and performs processing such as pattern recognition and motion detection.

It is a block diagram which shows the structure of the data access apparatus as embodiment. It is a figure which shows the access pattern set on a screen in embodiment. It is a block diagram which shows the structure of the data storage control part which comprises a data access apparatus. It is a flowchart which shows the operation | movement at the time of the initial storage by control of a data storage control part. It is a figure which shows the setting position of the access pattern at the time of a 1st phase process. It is a figure which shows the initial storage state of the pixel data at the time of a 1st phase process. It is a figure which shows the access pattern on the screen which concerns on upper memory bank BK0 at the time of 1st phase processing, and pixel allocation to lower memory bank BK00-BK03. It is a figure which shows the data storage state of low-order memory bank BK00-BK03 at the time of 1st phase processing. It is a figure which shows the access pattern on the screen which concerns on the high-order memory bank BK1, and the pixel allocation to the low-order memory banks BK10-BK13 at the time of 1st phase processing. It is a figure which shows the data storage state of low-order memory bank BK10-BK13 at the time of a 1st phase process. It is a figure which shows the access pattern on the screen which concerns on high-order memory bank BK2, and the pixel allocation to low-order memory banks BK20-BK23 at the time of 1st phase processing. It is a figure which shows the data storage state of low-order memory bank BK20-BK23 at the time of a 1st phase process. It is a figure which shows the setting position of the access pattern at the time of a 2nd phase process. It is a figure which shows the initial storage state of the pixel data at the time of 2nd phase processing. It is a figure which shows the setting position of the access pattern at the time of a 3rd phase process. It is a figure which shows the initial storage state of the pixel data at the time of a 3rd phase process. It is a block diagram which shows the structure of the data access control part which comprises a data access apparatus. It is a flowchart which shows the operation | movement at the time of the data access by control of a data access control part. It is a figure which shows the state which has an access pattern in a starting position at the time of a 1st phase process. It is a figure which shows the state (part which concerns on the high-order memory bank BK0) which has an access pattern in the start position at the time of a 1st phase process. It is a figure which shows the initial state of the low-order memory bank BK00-BK03 which comprises the high-order memory bank BK0 at the time of a 1st phase process. It is a figure for demonstrating the movement process after the reading of pixel data. It is a figure which shows the state which moved 1 pixel from the starting position in the access pattern set on the screen at the time of a 1st phase process. It is a figure which shows the state (part which concerns on the high-order memory bank BK0) which the access pattern moved 1 pixel from the starting position at the time of a 1st phase process. FIG. 11 is a diagram showing a state after moving one pixel in the lower memory banks BK00 to BK03 constituting the upper memory bank BK0 during the first phase processing. It is a figure which shows the state which 22 pixels moved from the starting position in the access pattern set on the screen at the time of a 1st phase process. It is a figure which shows the state (part which concerns on the high-order memory bank BK0) which 22 pixels moved from the starting position at the time of a 1st phase process. It is a figure which shows the state after 22 pixel movement of low-order memory bank BK00-BK03 which comprises high-order memory bank BK0 at the time of 1st phase processing. 1 is a diagram schematically showing a structure of a general semiconductor memory. It is a figure which shows the state which cannot access simultaneously. It is a figure which shows the memory structure of a several memory bank. It is a figure which shows an example of the access pattern set on the screen. It is a figure which shows the example of storage of the pixel data to four memory banks. It is a figure which shows the data access position in each memory bank when an access pattern exists in a start position. It is a figure which shows the state which the access pattern moved 10 pixels. It is a figure which shows the data access position in each memory bank when the access pattern exists in the position which moved 10 pixels.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Data access apparatus, 110 ... Memory part, 111 ... Input terminal, 112 ... Output terminal, BK0-BK2 ... Upper memory bank, BK00-BK03, BK10-BK13, BK20-BK23 ... Lower memory bank, 120 ... Data storage control unit, 121 ... Counter (counter A), 122 ... Counter (counter B), 123 ... Match determination unit, 124 ... Higher bank Address counter 125 ... Lower bank address counter 126 ... Bit line address counter 127 ... Word address line counter 128 ... Address generation unit 140 ... Data access control unit 141 ...・ Counter 142... Address counter control unit 143... Read address counter 144. Scan counter, 145 ... read address generator, 146 ... write address generator, 150 ... input terminal

Claims (10)

A memory unit comprising a lower memory bank specified by a lower bank address, and having a plurality of upper memory banks specified by an upper bank address;
A pixel in each pixel column in a predetermined screen in which pixel columns extending horizontally or vertically are sequentially arranged in a vertical or horizontal direction is set as a target pixel in order, and pixel data of the target pixel is set to a plurality of pixels set on the predetermined screen. A data storage control unit that performs control for allocating and storing in the plurality of upper memory banks based on an access pattern that is a pixel pattern;
Control for simultaneously acquiring pixel data of a plurality of pixels specified by the access pattern from each of the plurality of upper memory banks at each setting position where the setting position of the access pattern is moved in the pixel column direction from the start position. A data access control unit to perform,
The data storage control unit
It is assumed that first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and each pixel column on the predetermined screen is represented as a Kth pixel during the Kth (K = 1 to N) phase processing. It is assumed that the first to Nth pixel columns are repeated with the column as the first pixel column, and the pixel data of the first to Nth pixel columns are stored in the first to Nth upper memory banks, respectively. ,
When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank at the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position. (K-1) Based on a plurality of pixels specified by an access pattern set at a position shifted by a pixel, when a target pixel in the Mth pixel column first corresponds to any of the plurality of pixels, When the pixel data of the pixel of interest starts to be stored in the first lower memory bank of the Mth upper memory bank, and then the pixel of interest in the Mth pixel column corresponds to any of the plurality of pixels , Sequentially switching lower memory banks of the Mth upper memory bank for storing pixel data of the target pixel,
The data access control unit
The first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and in the Kth (K = 1 to N) phase processing, in the direction orthogonal to the pixel column direction from the start position. (K-1) The position shifted by the pixel is set as the first set position, and each time the movement for one column is finished, the column moves to the beginning of the column shifted by N pixels, and each of the access patterns sequentially moved in the pixel column direction At the set position, pixel data of a plurality of pixels specified by the access pattern are simultaneously read from the lower memory banks constituting the first to Nth upper memory banks, and the set position is moved in the pixel column direction. In this case, each upper memory bank is read from a predetermined lower memory bank so that pixel data of a plurality of pixels specified by the access pattern at the set position is stored in different lower memory banks. Data access apparatus characterized by storing pixel data in a previous lower memory banks of the lower memory bank pixel data has been stored. The data access apparatus according to claim 1, wherein the pattern of the plurality of pixels is a pattern of a plurality of central pixels and peripheral pixels located around each central pixel. 3. The data access according to claim 2, wherein N is equal to L when a pixel group including the central pixel and peripheral pixels located around the central pixel extends over L pixel columns. apparatus. The data storage control unit
At the time of the K-th phase processing, each of the target pixels is identified by an access pattern set at a position shifted by (K−1) pixels in a direction orthogonal to the pixel column direction from the start position. A match determination unit that determines whether or not the pixel matches the pixel;
A counting unit that counts the number of pixels from the beginning of the pixel row of the pixel of interest;
An address generation unit that generates a write address for the memory unit for each pixel of interest based on the determination output of the coincidence determination unit and the count value of the count unit during the K-th phase processing; The data access device according to claim 1. The data storage control unit
A start address generator for generating a read start address and a write start address corresponding to each of the lower memory banks constituting the first to Nth upper memory banks;
The start address generation unit sets, for each memory bank, an address at which the first pixel data is stored as the read start address, and an address next to the address at which the last pixel data is stored as the write start address. The data access device according to claim 4, wherein: The data access control unit
A read address generator for generating read addresses of lower memory banks constituting the first to Nth upper memory banks at each of the K-th phase processes;
A write address generator for generating a write address of a lower memory bank constituting the first to Nth upper memory banks at each of the K-th phase processes;
The read address generation unit
When the first read address is set to the read start address given from the outside for each of the lower memory banks constituting the first to Nth upper memory banks, and pixel data is read at each setting position , Increment the read address to generate the next read address,
The write address generation unit
For each of the lower memory banks constituting the first to Nth upper memory banks, the first write address is set to the write start address given from the outside,
The data access device according to claim 1, wherein when pixel data is written at each set position, the write address is incremented to generate a next write address. The data access apparatus according to claim 6, wherein the write start address and the read start address given from the outside are given from the data storage control unit. A pixel in each pixel column in a predetermined screen in which pixel columns extending in the horizontal or vertical direction are sequentially arranged in the vertical or horizontal direction is set as a target pixel in order, and pixel data of the target pixel is set on the predetermined screen. Based on an access pattern that is a pattern of a plurality of pixels, a data storage step that consists of a lower memory bank specified by a lower bank address, and is distributed and stored in a plurality of upper memory banks specified by an upper bank address;
A data access step of simultaneously acquiring pixel data of a plurality of pixels specified by the access pattern at each setting position obtained by moving the access pattern setting position from the start position in the pixel column direction from the plurality of upper memory banks; With
In the above data storage process,
It is assumed that first to Nth (N is an integer equal to or greater than 2) phase processing is sequentially performed, and each pixel column on the predetermined screen is represented as a Kth pixel column during the Kth (K = 1 to N) phase processing. Is the repetition of the first to Nth pixel columns, and the pixel data of the first to Nth pixel columns are respectively stored in the first to Nth upper memory banks,
When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank at the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position. (K-1) Based on a plurality of pixels specified by an access pattern set at a position shifted by a pixel, when a target pixel in the Mth pixel column first corresponds to any of the plurality of pixels, When the pixel data of the pixel of interest starts to be stored in the first lower memory bank of the Mth upper memory bank, and then the pixel of interest in the Mth pixel column corresponds to any of the plurality of pixels , Sequentially switching lower memory banks of the Mth upper memory bank for storing pixel data of the target pixel,
In the above data access process,
The first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and in the Kth (K = 1 to N) phase processing, in the direction orthogonal to the pixel column direction from the start position. (K-1) The position shifted by the pixel is set as the first set position, and each time the movement for one column is finished, the column moves to the beginning of the column shifted by N pixels, and each of the access patterns sequentially moved in the pixel column direction At the set position, pixel data of a plurality of pixels specified by the access pattern are simultaneously read from the lower memory banks constituting the first to Nth upper memory banks, and the set position is moved in the pixel column direction. In this case, each upper memory bank is read from a predetermined lower memory bank so that pixel data of a plurality of pixels specified by the access pattern at the set position is stored in different lower memory banks. Data access method characterized by storing pixel data in a previous lower memory banks of the lower memory bank pixel data has been stored. A pixel in each pixel column in a predetermined screen in which pixel columns extending in the horizontal or vertical direction are sequentially arranged in the vertical or horizontal direction is set as a target pixel in order, and pixel data of the target pixel is set on the predetermined screen. Based on an access pattern that is a pattern of a plurality of pixels, a data storage step that consists of a lower memory bank specified by a lower bank address, and is distributed and stored in a plurality of upper memory banks specified by an upper bank address;
A data access step of simultaneously acquiring pixel data of a plurality of pixels specified by the access pattern at each setting position obtained by moving the access pattern setting position from the start position in the pixel column direction from the plurality of upper memory banks; With
In the above data storage process,
It is assumed that first to Nth (N is an integer equal to or greater than 2) phase processing is sequentially performed, and each pixel column on the predetermined screen is represented as a Kth pixel column during the Kth (K = 1 to N) phase processing. Is the repetition of the first to Nth pixel columns, and the pixel data of the first to Nth pixel columns are respectively stored in the first to Nth upper memory banks,
When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank at the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position. (K-1) Based on a plurality of pixels specified by an access pattern set at a position shifted by a pixel, when a target pixel in the Mth pixel column first corresponds to any of the plurality of pixels, When the pixel data of the pixel of interest starts to be stored in the first lower memory bank of the Mth upper memory bank, and then the pixel of interest in the Mth pixel column corresponds to any of the plurality of pixels , Sequentially switching lower memory banks of the Mth upper memory bank for storing pixel data of the target pixel,
In the above data access process,
The first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and in the Kth (K = 1 to N) phase processing, in the direction orthogonal to the pixel column direction from the start position. (K-1) The position shifted by the pixel is set as the first set position, and each time the movement for one column is finished, the column moves to the beginning of the column shifted by N pixels, and each of the access patterns sequentially moved in the pixel column direction At the set position, pixel data of a plurality of pixels specified by the access pattern are simultaneously read from the lower memory banks constituting the first to Nth upper memory banks, and the set position is moved in the pixel column direction. In this case, each upper memory bank is read from a predetermined lower memory bank so that pixel data of a plurality of pixels specified by the access pattern at the set position is stored in different lower memory banks. Program for executing a data access method of storing pixel data in a previous lower memory banks of the lower memory bank pixel data is stored in the computer. A pixel in each pixel column in a predetermined screen in which pixel columns extending in the horizontal or vertical direction are sequentially arranged in the vertical or horizontal direction is set as a target pixel in order, and pixel data of the target pixel is set on the predetermined screen. Based on an access pattern that is a pattern of a plurality of pixels, a data storage step that consists of a lower memory bank specified by a lower bank address, and is distributed and stored in a plurality of upper memory banks specified by an upper bank address;
A data access step of simultaneously acquiring pixel data of a plurality of pixels specified by the access pattern at each setting position obtained by moving the access pattern setting position from the start position in the pixel column direction from the plurality of upper memory banks; With
In the above data storage process,
It is assumed that first to Nth (N is an integer equal to or greater than 2) phase processing is sequentially performed, and each pixel column on the predetermined screen is represented as a Kth pixel column during the Kth (K = 1 to N) phase processing. Is the repetition of the first to Nth pixel columns, and the pixel data of the first to Nth pixel columns are respectively stored in the first to Nth upper memory banks,
When the pixel data of the Mth (M = 1 to N) pixel columns are stored in the Mth upper memory bank at the K-th phase processing, respectively, in the direction orthogonal to the pixel column direction from the start position. (K-1) Based on a plurality of pixels specified by an access pattern set at a position shifted by a pixel, when a target pixel in the Mth pixel column first corresponds to any of the plurality of pixels, When the pixel data of the pixel of interest starts to be stored in the first lower memory bank of the Mth upper memory bank, and then the pixel of interest in the Mth pixel column corresponds to any of the plurality of pixels , Sequentially switching lower memory banks of the Mth upper memory bank for storing pixel data of the target pixel,
In the above data access process,
The first to Nth (N is an integer of 2 or more) phase processing is sequentially performed, and in the Kth (K = 1 to N) phase processing, in the direction orthogonal to the pixel column direction from the start position. (K-1) The position shifted by the pixel is set as the first set position, and each time the movement for one column is finished, the column moves to the beginning of the column shifted by N pixels, and each of the access patterns sequentially moved in the pixel column direction At the set position, pixel data of a plurality of pixels specified by the access pattern are simultaneously read from the lower memory banks constituting the first to Nth upper memory banks, and the set position is moved in the pixel column direction. In this case, each upper memory bank is read from a predetermined lower memory bank so that pixel data of a plurality of pixels specified by the access pattern at the set position is stored in different lower memory banks. A computer-readable recording medium storing a program for executing a pixel data a data access method for storing the previous lower memory banks of the lower memory bank pixel data is stored in the computer with.

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