JP2000172552A - Memory access device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the memory throughput by improving the availability of a memory element. SOLUTION: When the memory requests are stored in a request storing buffer 1-1 owing to a bank busy state, the addresses of memory requests are compared with each other in the buffer 1-1 and whether the coincidence of access destination addresses is checked or not. Thus, the assurance is not needed for the sequence of requests and a memory request to which the bank busy state is canceled is issued. Then an SDRAM is used as a memory element, the inter-bank cycle management is carried out in the same SDRAM and the banks are effectively used in the SDRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory access device and a method for accessing a DRAM or SDRAM having a plurality of banks.

[0002]

2. Description of the Related Art As a conventional memory access device, for example, the one shown in FIG. 3 is known.

The memory access device shown in FIG. 3 comprises a request storage buffer 3-1, a bank busy counter 3-2, a refresh check circuit 3-3, and a bank check circuit 3.
-4, selector 3-5.

[0004] The request storage buffer 3-1 stores a memory request received from a request issuing source at the time of bank busy or refresh busy. The bank busy counter 3-2 counts the bank busy time from the bank address of the memory request sent to the memory control unit and generates a bank busy.

The refresh check circuit 3-3 generates a refresh request at regular intervals. The bank check circuit 3-4 generates a request select from a bank busy, a refresh request, and a bank address of an access destination of the request stored in the request storage buffer 3-1. The selector 3-5 selects a memory request by request selection and outputs the selected memory request to the memory control unit.

[0006]

In the above-mentioned conventional memory access device, when a read memory request and a write memory request are stored in the request storage buffer 3-1 due to, for example, bank busy, the read memory request is read. In addition, it is necessary to guarantee the order for write memory requests. Therefore, the output order of the request storage buffer 3-1 is FIFO (FARST IN FAR
ST OUT) operation. That is, even when the access destination bank of the subsequent request is not busy, the preceding request cannot be overtaken, and thus there is a problem that the memory throughput is reduced.

In addition, when an SDRAM is used, there is another problem that the banks in the SDRAM are not effectively used because cycle management between banks in the same SDRAM is not performed.

[0008] The present invention has been made in view of such circumstances, and by increasing the use efficiency of the memory element,
An object of the present invention is to provide a memory access device and an access method capable of improving a memory throughput.

[0009]

A memory access device according to claim 1 is a memory access device for a memory element having a plurality of banks, wherein the memory access device stores received memory requests in ascending order of word numbers. An address comparison circuit for comparing address information of the storage buffer with memory requests staying in the request storage buffer and checking whether a memory request for accessing the same address exists in the request storage buffer; and a bank busy circuit A bank busy counter for generating information, a refresh check circuit for generating a refresh request at regular intervals and outputting a refresh request, and a request select for selecting a memory request to output to a memory control unit for controlling a memory element A request selection circuit for generating a No., by selecting the memory request by the generated request select signal; and a selector for outputting to the memory control unit. The request storage buffer outputs the memory request to the memory control unit when the received memory request is not bank busy or refresh busy, and stores the memory request up to n (n words) when the received memory request is bank busy. Can be Further, when outputting the word number “m”, the request storage buffer holds the memory request with the word number of “m−1” or less as it is and keeps the memory request with the word number as it is. The memory request of “m + 1” can be shifted to the word number of “−1” to store the memory request. Further, the address comparison circuit may output an address comparison result of the preceding memory request for each of n-word requests after checking whether the memory request exists in the request storage buffer. Further, the address comparison circuit can perform a comparison of bank addresses, which is a partial comparison. The bank busy counter sets a bank busy time from a bank address and a command of a memory request sent to the memory control unit, decrements by −1 every clock cycle, and is set to a bank busy when the counter value is other than “0”. It is possible to have a bank busy counter for notifying that there is, for each bank. Further, the request selection circuit generates a memory request based on bank busy information from a bank busy counter, a refresh request from a refresh check circuit, an access destination bank address of a memory request of a request storage buffer, and an address comparison result from an address comparison circuit. Can be selected. The request selection circuit may set the priority of request selection in the order of a refresh request, the ascending order of word numbers stored in the request storage buffer, and the memory request transmitted from the request issuing source. it can. Further, the request selection circuit can generate the request select signal when the access destination bank is not bank busy or when the access destination addresses of the memory requests with high priority do not match. Further, the memory element can be a DRAM or an SDRAM containing a plurality of banks. Further, the bank busy counter may be provided with a counter for counting the cycle time between banks when an access is made to a different bank in the same SDRAM with respect to the SDRAM. 13. The memory access method according to claim 12, wherein the first step of storing the received memory requests in ascending order of the word numbers, and the address of the memory requests. A second step of comparing information and checking for the presence of a memory request for accessing the same address, a third step of generating bank busy information, and a second step of generating a refresh request at regular intervals and outputting the refresh request. A fourth step, a fifth step of generating a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element, and selecting a memory request based on the generated request select signal. And a sixth step of outputting to the memory control unit. . Also, in the first step, when the received memory request is not bank busy or refresh busy, the memory request is output to the memory control unit, and when the received memory request is bank busy, up to n (n words) memory requests are stored. A step of performing the operation. In the first step, when the word number “m” is output, the memory request having the word number equal to or less than “m−1” is held in the same word number, and “n−1” To "m + 1" may be shifted to "-1" word numbers to store the memory requests. The second step may include a step of outputting an address comparison result of a preceding memory request for each of n-word requests after checking whether or not a memory request is stored. it can. In addition, the second step may include a step of comparing bank addresses, which is a partial comparison. In the third step, the bank busy time is set from the bank address and the command of the memory request sent to the memory control unit, the count is reduced by −1 every clock cycle, and if the counter value is other than “0”, the bank busy time is set. A step of notifying that it is busy may be included. Further, the fifth step may include a step of selecting a memory request based on bank busy information, a refresh request, an access destination bank address of a stored memory request, and an address comparison result. Also,
In the fifth step, the priority as request selection is
The process may include a refresh request, a stored word number in ascending order, and a memory request transmitted from the request issuing source. Further, the fifth step includes a step of generating a request select signal when the access destination bank is not bank busy and when the access destination addresses of the high-priority memory requests do not match. be able to. Further, the third step may include a step of counting, for each bank, a cycle time between banks when an access is made to a different bank in the same SDRAM with respect to the SDRAM. In the memory access device and the access method according to the present invention, when a memory request is stored in the request storage buffer due to bank busy, the address of the memory request in the request storage buffer is compared,
Check whether the access destination address matches,
It is not necessary to guarantee the order of the memory requests, and a memory request in which the bank busy has been released is issued. When an SDRAM is used as a memory element, cycle management between banks in the same SDRAM is performed,
The banks in the SDRAM are effectively used.

[0010]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing an embodiment of the memory access device of the present invention, and FIG. 2 is a flowchart for explaining an access method of the memory access device of FIG.

The memory access device shown in FIG. 1 includes a request storage buffer 1-1, an address comparison circuit 1-2, a bank busy counter 1-3, a refresh check circuit 1-4, a request selection circuit 1-5, and a selector 1-. 6
It has.

The request storage buffer 1-1 is a buffer for saving requests when a bank is busy. The request storage buffer 1-1 stores memory requests up to n
(N words, from word “0” to word “n−1”) can be stored, and memory requests are stored in ascending order of word numbers.

For example, a word number “m” (0 ≦ m ≧
In the case of outputting (n-1), a memory request having a word number equal to or less than "m-1" holds the memory request in the same word number. "N-1" to "m +
The memory requests of "1" are each shifted to a word which is "-1" to store the memory request.
When a memory request is stored, the stored request is stored from the youngest, so that the stored request is not stored in a toothless state.

The address comparison circuit 1-2 compares the address information of the memory requests staying in the request storage buffer 1-1. That is, it is checked whether or not a memory request for accessing the same address in the preceding memory request exists in the request storage buffer 1-1. Is output.

As an example, a method of checking the address comparison result of the word “X” will be described. That is, the word "X"
When the access address of the address is “Y”, the word “X”
The address is compared with all access addresses from "-1" to the word "0." At this time, if the addresses do not match, the address comparison result is passed. It can be seen that the address matches.

At this time, the memory request of the word “X” does not satisfy the output condition. For the request received from the request issuing source, it is necessary to compare with the access addresses of all the memory requests staying in the request storage buffer 1-1.

Note that the address comparison by the address comparison circuit 1-2 is not limited to comparison of all addresses, but is effective, for example, only for partial comparison with bank addresses.

The bank busy counter 1-3 sets a predetermined bank busy time for a bank cycle from a bank address and a command of a memory request to be sent to a memory control unit for controlling a memory element (not shown). In addition, each bank cycle has a bank busy counter for notifying that the bank is busy when the counter value is other than "0", and generates bank busy information.

In the case of an SDRAM in which a plurality of banks are built in the same memory element, an inter-bank busy counter is provided. In this case, a predetermined bank busy time for the inter-bank cycle of the SDRAM is set, and -1 countdown is performed every clock cycle.

The refresh check circuit 1-4 generates a refresh request at regular intervals, and generates a refresh request having the highest priority.

The request selection circuit 1-5 generates a request select signal for selecting a memory request to be output to the memory control unit. In this case, the request selection circuit 1-5 receives the bank busy information from the bank busy counter 1-3, the refresh request from the refresh check circuit 1-4, and the memory request stored in the request storage buffer 1-1. An access destination bank address and an address comparison result from the address comparison circuit 1-2 are input.

The priority order for request selection at this time is a refresh request, the word number stored in the request storage buffer 1-1 in ascending order, and the memory request transmitted from the request source.

A condition necessary for generating the request select signal is that the access destination bank is not bank busy. In addition, the access destination addresses of memory requests having a high priority, that is, a memory request having a small word number do not match. Select the request with the highest priority that meets the above conditions.

The selector 1-6 selects a memory request according to the request select signal, and transmits the memory request to the memory control unit.

Next, an access method by the memory access device having such a configuration will be described with reference to FIG.

First, when the access destination bank of the memory request received from the request issuing source is not bank busy and the preceding request is not stored in the request storage buffer 1-1, the received memory request is output to the memory control unit. .

When the preceding request is stored in the request storage buffer 1-1, whether the stored request and the access destination bank of the received request are busy is determined by the bank of the bank busy counter 1-3. Check from the busy information (step 2-1).

Next, the memory request staying in the request storage buffer 1-1 is compared with the address information of each of the received memory requests. In this case, the address comparison circuit 1-2 checks whether a memory request for accessing the same address exists in the request storage buffer 1-1 (step 2-2), and compares the address comparison result with all the memory requests. Output to

The request having the highest priority is selected from the requests that have passed the above check result (step 2-3), and a request select is generated (step 2-4).

According to the generated request select, the request storage buffer 1-1 exchanges memory requests in the buffer (step 2-5). Also,
According to the generated request select, the selector 1-6 is selected.
The value corresponding to the bank cycle is set in the corresponding bank busy counter from the access destination bank address and command of the memory request output via
-6).

As described above, in this embodiment, when a memory request is stored in the request storage buffer 1-1 due to bank busy, the address of the memory request in the request storage buffer 1-1 is compared.
Since it is checked whether or not the access destination addresses match, it is not necessary to guarantee the order of the requests, and it is possible to issue a memory request from which the bank busy is released, thereby improving the throughput. .

Further, when an SDRAM is used as a memory element, cycle management between banks in the same SDRAM is performed to effectively use the banks in the SDRAM, so that the throughput can be further improved.

[0034]

As described above, according to the memory access device and the access method of the present invention, when a memory request is stored in the request storage buffer due to bank busy, the address of the memory request in the request storage buffer is changed. In comparison, it is checked whether or not the access destination addresses match, it is not necessary to guarantee the order of the memory requests, a memory request in which the bank busy is released is issued, and the SDRAM is used as a memory element. At this time, since the cycle management between banks in the same SDRAM is performed and the banks in the SDRAM are effectively used, the use efficiency of the memory element can be improved, and the memory throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a memory access device of the present invention.

FIG. 2 is a flowchart for explaining an access method by the memory access device of FIG. 1;

FIG. 3 is a diagram showing a conventional memory access device.

[Explanation of symbols]

 1-1 Request storage buffer 1-2 Address comparison circuit 1-3 Bank busy counter 1-4 Refresh check circuit 1-5 Request selection circuit 1-6 Selector

Claims (21)

[Claims] 1. A memory access device for a memory element having a plurality of banks, comprising: a request storage buffer for storing received memory requests in ascending order of word numbers; and a memory resident in the request storage buffer. An address comparison circuit for comparing address information of a request and checking whether a memory request for accessing the same address exists in the request storage buffer; a bank busy counter for generating bank busy information; and refreshing at regular intervals. A refresh check circuit that generates a request and outputs a refresh request; a request selection circuit that generates a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element; And a selector for selecting a memory request based on the generated request select signal and outputting the selected memory request to the memory control unit. 2. The request storage buffer outputs the memory request to the memory control unit when the received memory request is not the bank busy or the refresh busy, and when the received memory request is the bank busy, the request storage buffer stores at most n memory requests ( 2. The memory access device according to claim 1, wherein up to n words are stored. 3. When the request storage buffer outputs a word number “m”, a memory request having a word number equal to or less than “m−1” holds the memory request with the same word number, and outputs “n”. -1 ”to“ m +
2. The memory access device according to claim 1, wherein each of the memory requests of "1" is shifted to a word number of "-1" to store the memory request. 4. The address comparison circuit outputs an address comparison result of a preceding memory request for each of n-word requests after checking whether the memory request exists in the request storage buffer. The memory access device according to claim 1, wherein: 5. The memory access device according to claim 1, wherein the address comparison circuit performs a comparison of a bank address that is a partial comparison. 6. The bank busy counter sets a bank busy time from a bank address and a command of a memory request sent to the memory control unit, decrements by −1 every clock cycle, and a counter value other than “0”. 2. The memory access device according to claim 1, wherein each of the banks has a bank busy counter for notifying that the bank is busy. 7. The request selection circuit includes a bank busy information from the bank busy counter, a refresh request from the refresh check circuit, an access destination bank address of a memory request of the request storage buffer, and an address from the address comparison circuit. The memory access device according to claim 1, wherein the memory request is selected based on a comparison result. 8. The request selection circuit sets the priority as a request selection in the order of a refresh request, the word number stored in the request storage buffer in ascending order, and the memory request transmitted from the request issuing source. 2. The memory access device according to claim 1, wherein: 9. The request selection circuit according to claim 1, wherein the request selection circuit generates the request select signal when an access destination bank is not bank busy and when an access destination address of a high priority memory request does not match. 2. The memory access device according to claim 1, wherein: 10. The memory access device according to claim 1, wherein the memory element is a DRAM or an SDRAM containing a plurality of banks. 11. The bank busy counter includes:
11. The memory access device according to claim 10, wherein a counter for counting a cycle time between banks when an access is made to a different bank in the same SDRAM with respect to the DRAM is provided for each bank. 12. A memory access method for a memory element having a plurality of banks, comprising: a first step of storing received memory requests in ascending order of word numbers; and comparing address information of the memory requests; A second step of checking for the presence of a memory request accessing the same address, a third step of generating bank busy information, a fourth step of generating a refresh request at regular intervals and outputting the refresh request, A fifth step of generating a request select signal for selecting a memory request to be output to a memory control unit that controls the memory element; and selecting the memory request by the generated request select signal to perform the memory control. Characterized by comprising a sixth step of outputting to a unit. Reaccess method. 13. The first step includes: outputting the memory request to the memory control unit when the received memory request is not bank busy or refresh busy; 13. The memory access method according to claim 12, further comprising the step of storing up to n (for n words). 14. In the first step, when outputting a word number “m”, a memory request having a word number equal to or less than “m−1” holds the memory request with the same word number, “N−1” to “m + 1”
13. The memory access method according to claim 12, further comprising the step of storing the memory request by shifting each of the memory requests to a word number set to "-1". 15. The second step includes outputting an address comparison result of a preceding memory request for each of n-word requests after checking whether the memory request is stored. 13. The memory access method according to claim 12, wherein: 16. The memory access method according to claim 12, wherein the second step includes a step of comparing bank addresses, which is a partial comparison. 17. In the third step, a bank busy time is set from a bank address and a command of a memory request to be sent to the memory control unit, -1 countdown is performed every clock cycle, and a counter value is "0". 13. The memory access method according to claim 12, further comprising a step of notifying that the bank is busy in other cases. 18. The method according to claim 15, wherein the fifth step includes selecting the memory request based on the bank busy information, the refresh request, an access destination bank address of the stored memory request, and the address comparison result. 13. The memory access method according to claim 12, wherein the memory access method is included. 19. The fifth step includes a step of setting the priority of request selection in the order of a refresh request, the stored word number in ascending order, and the memory request transmitted from the request issuing source. 13. The memory access method according to claim 12, wherein the memory access method is included. 20. The fifth step includes the step of generating the request select signal when an access destination bank is not bank busy and when an access destination address of a high priority memory request does not match. 13. The memory access method according to claim 12, wherein the memory access method is included. 21. The method according to claim 21, wherein the third step includes a step of counting, for each bank, an interbank cycle time when an access is made to a different bank in the same SDRAM with respect to the SDRAM. The memory access method according to claim 12.