JP2912609B2 - Multiple address holding storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-address holding storage device shared by a plurality of processes or a plurality of processors, and more particularly, to efficiently access data in a main storage unit at random input / output. The present invention relates to a multiple-address holding storage device that holds addresses of access destinations in advance and rearranges the order so that access can be performed efficiently.

[0002]

2. Description of the Related Art When one dynamic random access memory (hereinafter, referred to as DRAM) is accessed by sharing a plurality of processes or a plurality of processors, in order to shorten the DRAM access time, for example, There has been a method in which the inside of a main storage unit is configured as a multi-bank structure and accessed while switching banks to reduce the apparent access time, as currently employed in synchronous DRAMs.

In such a multi-bank memory system, especially in a memory system in which an address bus and a data bus can be accessed independently, when the access to the address bus is attempted, the previous operation is performed. In order to eliminate the need to wait for the end of access, an address is stored in a first-in first-out memory (hereinafter referred to as a FIFO memory),
There has also been a memory system that employs a method of giving addresses in order of input from a FIFO memory to storage means. This memory system is disclosed in Japanese Patent Application Laid-Open No. 4-175943.

[0004]

However, in the above-mentioned conventional memory system, since the address is stored in the FIFO memory, the information stored in the FIFO memory is retrieved in the order of access from the process or the processor. Therefore, the address information stored in the FIFO memory and the control information for accessing the storage means can be accessed only in the order of access. Therefore, in consideration of the address structure and the bank structure of the storage unit in the memory system accessed from the process or the processor and the priority when the memory system is accessed from the process or the processor, the order of the access is changed, and the optimal access, that is, It was not possible to access in the order that minimizes the access time.

Here, the optimum access order will be described. For example, when accessing data in different banks successively, there is no need to perform precharge between accesses to continuous data. Even when data in the same bank is accessed continuously, if data having the same row address but different column addresses is continuously accessed, precharge is performed between successive data accesses in the bank. No need to do.

In consideration of the above points, the access order of the addresses is set such that the addresses of the addresses to be accessed are such that addresses of different banks continue or addresses of the same row address continue in the same bank. It is considered that if the number of precharge cycles inserted between successive data accesses is reduced as much as possible, the access time can be shortened.

However, the access order of the addresses is simply rearranged such that addresses different in banks continue or addresses having the same row address continue in the same bank. With this configuration, if a situation occurs in which access from multiple processes or multiple processors is performed without interruption, only data access from a specific process or processor is performed, and data from other processes or processors is only used. Access may be postponed and other processes or processors may stagnate. The reason is that, in a process or processor that performs image processing or the like, access to data in which the same row address is the same and the only column address is different in the same bank often continues, and in this case, the bank from another process or processor is used. This is because even if an access to an address having a different row address or a different row address is performed in the middle, it is postponed by changing the access order under the above conditions.

Further, if addresses are exchanged simply for the purpose of shortening the access time in the access order, there is a possibility that an access that is always postponed may appear. This is the case where the access added later is always suitable for shortening the access time.
In this case, a method of setting priorities for accesses, raising the priority of accesses that have been delayed many times, and starting access unconditionally for accesses having a certain priority or higher. If it is used, it can be avoided.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiple address holding storage device capable of shortening the entire access time when a main storage is shared by a plurality of processes or a plurality of processors. Another object of the present invention is to retain a plurality of addresses that can prevent the access of any process or processor among a plurality of processes or a plurality of processors from being postponed and the processing of the process or the processor from being stagnated. It is to provide a storage device.

[0010]

According to the present invention, addresses sequentially or simultaneously inputted are stored in an address temporary storage unit, and the order of the addresses stored in the address temporary storage unit by a reordering unit is reduced so that the entire access time is reduced. By reading the stored addresses at a speed corresponding to the operation of the main memory, the access cycle required between the main memory and the process or the processor is reduced, and the total access time to the main memory is reduced. Is shortened. Reordering the addresses so that the overall access time is reduced, that is, to increase the access speed, is, for example, reordering so that addresses having the same row address are accessed successively, and in particular, multiple banks. In the case of the main storage unit having the structure, it means that if there is no address having the same row address, the addresses are rearranged so that addresses having different banks are successively accessed. By such rearrangement, the precharge between the access of one address and the access of the next address can be avoided or the waiting time for the precharge can be reduced, and as a result, the overall access time can be shortened. It becomes. By setting priorities for accesses from a plurality of processes or a plurality of processors, and prioritizing the priorities for the above-described reordering of addresses to increase the access speed, the priority of a plurality of processes or a plurality of processors can be improved. By appropriately setting the order, it is possible to prevent the access order from continuously falling due to the change of the address order, thereby preventing stagnation of access to the main storage unit from a specific process or processor.

More specifically, the multiple address holding storage device of the present invention exchanges data with a plurality of processes or a plurality of processors, and is shared by a plurality of processes or a plurality of processors. The multi-address holding storage device includes a main storage unit, an address bus, a data bus, an address temporary storage unit, and a rearrangement unit.

The address bus receives an address for accessing the main storage unit from a plurality of processes or a plurality of processors and a control signal for controlling the main storage unit.
Data bus inputs and outputs data between processes or more processors and a main memory unit of the multiple. The address temporary storage unit is provided at an address input end of the main storage unit, and can hold a plurality of addresses input through an address bus and hold a plurality of control signals corresponding to the plurality of addresses. The given addresses are sequentially provided to the main storage unit, and a control signal is provided to the main storage unit. Moreover, reordering unit provides a main storage unit Warazu access all the accessed sequentially is replaced address and control signals on the order in which the high speed from the temporary storage unit address to the main storage unit.

As described above, the arrangement is such that the addresses are exchanged by the rearranging section and the addresses are provided from the temporary address storage section to the main storage section, so that the access can be speeded up. In other words, by having an address temporary storage unit that can store addresses sequentially, the cycle of address input can be pipelined, which serves as a buffer for bus access, and can be used when discontinuous accesses or simultaneous accesses occur. Can respond to the sequential access, and it is possible to rearrange the access so that the access of the main storage unit becomes efficient, and it is possible to eliminate unnecessary access cycles and shorten the access time.

Here, the address bus and the data bus are
In order to pipeline address input cycles, it is necessary to operate independently, in other words, to operate independently. Operationally independent means not only when the address bus and data bus are separately wired, but also when the same wiring is used, the address bus and data bus operate independently by time sharing. This is because we want to include cases where we can consider that The above-mentioned time sharing means that only one address information is transmitted during a period when one common bus is used as an address bus, and only data information is transmitted during a period when one common bus is used as a data bus. It is a form.

Next, the relationship between the reordering of memory accesses and the independence of the address bus and the data bus will be described. The contents of the signal for accessing the main storage unit from the processor or the like through the address bus include address information for accessing the main storage unit, control information for reading or writing to the main storage unit, priority order information for access, and the processor that accessed the main storage unit. Contains a control number indicating what is.

When the condition that the processor can access the address temporary storage unit is satisfied, that is, even if the address temporary storage unit has a free space and two or more processors access simultaneously, the priority order is higher than that of the access of the other party. When it is higher, the address can be sequentially written to the address temporary storage unit, so that the next access cannot be input until the cycle of the address bus in the processor access is completed.

At this time, if the address bus and the data bus are not independent, or if the same bus is not properly time-shared, address information and control information are not exchanged during data exchange. Will be waited for. For this reason, the address bus and the data bus are operatively independent from each other so that address information and control information can be accessed even when data is exchanged.

Next, a useless access cycle will be described. There are three types of this useless access cycle. When reading or writing is performed by accessing the main storage unit, access is performed by inserting control information such as read or write and address information. After the above information is input to the main storage unit and before data writing or reading is performed, an internal circuit of the main storage unit, such as activation of an address to the storage area of the main storage unit or selection of data, is performed. Causes a time lag. This is the first useless access cycle.

In a normal DRAM, two types of addresses called a row address and a column address are sequentially input, and reading and writing can be performed on one portion of a storage area. However, after one access and before the next access is performed, a so-called reset period, which is called precharge, is required. However, the reset period is not required for the same row address. In this method, the row address is entered first, followed by the column address.When the row address is entered, all the storage areas connected to the row address are activated, and when the column address is entered, the activation is started. Data is read and written by specifying one location in the specified storage area, so once the storage area is started,
Even if the column address is different, access can be made without a time lag of startup. However, if the same row address accesses the main storage unit with a different row address, the first row address differs from the next row address, so a reset period called precharge is required. And the row address is different in the next access, so a reset period is required. It is the second useless access cycle that there is an access of another row address between these accesses of the same row address and a precharge occurs and a time lag occurs.

In a DRAM having a plurality of banks, the access in one bank is the same as that in the above-mentioned two.
It is similar in two respects, but has other advantages. That is,
The reset period referred to as precharge in the description of the second useless access cycle is a period in which resetting is performed when one row address is accessed and a storage area is started with another row address. However, if a plurality of banks are employed, even if the bank is in the reset period, if the bank is different from the bank in the reset period, the bank has already been precharged, so even if the bank has a different row address. It is possible to start a storage area. By doing so, there is no time lag in the reset period only by the time lag of starting the storage area by inputting the row address. In other words, when the main memory is accessed three times with different row addresses, the first and second banks are the same, and when only the last bank is different, access is performed in order. A reset period is required between the first and second accesses. This is the third useless access cycle.

When the control signal stored in the temporary storage unit includes the access priority information, the rearrangement unit performs rearrangement according to the access priority so that the access can be performed at high speed. It is also possible to give priority to rearrangement according to the priority of access over rearrangement according to a certain order. The order in which the above access is performed at a high speed is, for example, an order in which accesses to addresses having the same row address are consecutive. In particular, when the main storage unit has a multi-bank structure, addresses in different banks are used. Access is in consecutive order.

The processing of the rearranging unit that prioritizes rearrangement according to the access priority order over rearrangement according to the order in which access speeds up is, for example, the following processing.
That is, the access is started by rearranging the access order with the highest priority first. If there is a row address that is currently being executed and the row address is the same, and another row address with a different priority has a priority equal to or less than that of the same row address, the row with the same row address is sorted first. To start access. If there is a different bank from the one currently being executed and the priority of the other bank is the same or less than that of the different bank, the access is started by rearranging the different bank first. This is the process. In the address and the control signal stored in the temporary storage means, the control signal includes priority information and control information for writing or reading to or from the main storage unit. Is defined.

As described above, if the order is determined in consideration of the access priority and rearranged, even if the access is delayed, important accesses can be preferentially performed. In addition, it is possible to prevent the access of any process or processor among the plurality of processes or the plurality of processors from being postponed, and the processing of the process or the processor from being stagnated.

Here, the relationship between the priority of access, the important access, and a plurality of processes or a plurality of processors will be described. Priority is used in two ways. First, when two or more accesses are made simultaneously from a process or a processor, it is used to determine which access is received first, and is previously included as information in a control signal. With this priority information, it becomes clear in which order the information is stored in the temporary storage means even if accesses occur simultaneously.

Second, the rearrangement section uses the information as one of the rearrangement information when determining the rearrangement.
More specifically, the temporary storage unit also has a priority as part of the control signal information, and the reordering unit rearranges the order of the highest priority in the priority first and starts access. I do. If the row address currently being executed is the same as the row address, and the priority of the different row address is lower than or equal to that of the same row address, the rows with the same row address are sorted first. If there is a bank with a different bank from the one currently being executed and the priority of the other bank is the same or less than that of a different bank, the bank with a different bank is sorted first. By starting access, sorting is determined. It is used as one of the information of the rearrangement at this time.

However, if rearrangement by priority is not adopted, or if the priority is fixed, if rearrangement is performed so that access to an address having the same row address is continued or access to a different bank is continued. When the address / control signal pair newly written from the plurality of processes or the plurality of processors to the temporary storage means one after another has the same row address as that currently being executed or has a different bank. The following phenomenon will occur. In other words, old address / control signal pairs written from a process or processor that has different row addresses and the same bank accesses the same address may have the same row address or a different bank from the currently executed one. When new data is written to the temporary storage means, it is always skipped. A process or processor that has a different row address than the one in which the bank accesses the same address will be permanently deferred.

Therefore, every time the old address / control signal pair is pulled out, the rearranging unit performs an operation of increasing the priority, which is the information of the control signal, for the old address / control signal pair. With such an operation, when rearrangement is performed by the rearranging unit in consideration of the priority in addition to the row address and the bank, the old address / control signal pair having the higher priority becomes
New addresses from multiple processes or processors
Even if a control signal pair having the same row address as that currently being executed is newly written in the temporary storage means, if the priority of the old address / control signal pair is higher, the access is not permitted. Even if it becomes more efficient and slower, access is started first.

In this way, each time the old address / control signal pair is extracted by the rearranging unit, the priority is operated by the rearranging unit, so that the access of the new process or processor, which is currently being executed, is different from that of the currently executed one. The address / control signal pair for the same row address or the different bank is written to the temporary storage means, so that the row address is different from the currently executing row address and the bank is the same, so that it is always postponed. It is possible to prevent a process or a processor in which a certain address / control signal pair is written from being permanently stagnated. In other words, since the rearrangement in consideration of the priority can be performed, it is possible to increase the priority of the address / control signal pair that has been omitted, for example, by rearrangement based on the row address or the bank information.
It is possible to design so that there is no control that is not executed forever. The process that is permanently stagnant is an access of a new process or a processor, and the address / control signal pair for the one having the same row address or the one having a different bank is written in the temporary storage means, so that the process is constantly performed. This is a process or a process of a processor in which an address / control signal pair in which the row address is different and the bank is the same is written later.

Also, by utilizing the priority information contained in the control signal positively, a certain process or processor needs real-time access, which is an important access compared to other accesses that do not need real-time performance. In the case of accessing the audio data or the image data, by increasing the priority from the beginning, the rearranging unit can perform the rearrangement in consideration of the priority, and start the access without waiting for another access. It becomes possible.

The temporary storage means temporarily stores an address and a control signal for accessing the main storage unit as described above. Among these, the control signal includes priority information and the main information. And control information for controlling whether to write data to the storage unit or read data from the main storage unit. By accessing the main storage unit as a pair of the above-described address and the control signal including the control information, data read or write access is performed at a specific address in the main storage unit. Therefore, the address and the control signal need to be paired. The temporary storage means stores a pair of an address and a control signal (hereinafter, referred to as a pair).
And a plurality of address / control signal pairs).

The reordering unit includes, for example, an order determining unit that determines the order of the addresses of the temporary storage unit based on information included in the address / control signal pair stored at each address of the temporary storage unit; The order storage switching unit stores the order determined by the unit, and an output address generation unit that supplies an output address for reading data to the temporary storage unit according to the storage content of the order storage switching unit.

Further, as the address information of the address and the control signal stored in the temporary storage means,
There are address information indicating an address to access the main storage unit and bank information indicating a bank to access the main storage unit (only when the main storage unit has a multiple bank structure). Further, as information of the control signal, for example, a vacancy flag indicating that the address of the temporary storage means is vacant, priority information indicating the priority of access in the process or the processor, and whether to read out to the main storage unit There are read / write information indicating whether to perform writing and a control number indicating a number specifying a processor (or a control signal).

Then, the order of the address and the control signal is determined in the sequential determination unit using the priority order information, the address information, and the bank information, and the order is stored in the order storage exchange unit. Read and write to a specific process or processor. Further, the free address checking unit checks the free address of the temporary storage unit based on the free flag.

The empty flag, the priority information, the read / write information, and the control number are part of the information of the control signal in the address / control signal pair. The address information and the bank information are part of address information in the address / control signal pair. Hereinafter, each information will be described in detail. The empty flag contains information as a part of the control signal in the address / control signal pair.
It is used to check a free address in the temporary storage means. The temporary storage means has a plurality of areas for storing address / control signal pairs. To indicate whether the area for storing the address / control signal pair is free, there is one empty flag in each area for storing each address / control signal pair, and the address / control signal pair is written. When empty, the empty flag indicates that it is not empty. Here, it is assumed that the empty flag is not empty when the empty flag is at the high level, and that the empty flag is empty when the empty flag is at the low level. When the address / control signal pair is written, the empty flag is at the high level. When the address / control signal pair is used for accessing the main storage unit and read, the empty flag changes from a high level to a low level. It is the free address checking unit that checks the area where the free flag is at the low level.

The control number contains information as a part of the control signal in the address / control signal pair, and has two meanings. First, in the case where a plurality of address / control signal pairs are written in the temporary storage means, the control of the rearrangement is performed by the order determination unit and the address / control signal pairs corresponding to the address / control signal pairs are input to the order storage replacement unit. Used as a number. In this case, since it corresponds to a specific address / control signal pair, it is used for recognizing which address / control signal pair. Second, when reading / writing data from / to the main storage unit in response to address / control signal pairs written from a plurality of processes or a plurality of processors,
Identify which process or processor,
This is to access a specific process or processor on the data bus.

The priority information is part of the information of the control signal in the address / control signal pair, and describes the priority level. -Used to have the control signal pair accepted. The other is used as information for changing the order in the order determination unit using priority information as described later.

The read / write information is a part of the information of the control signal in the address / control signal pair, and describes whether to read data from the main memory or write data to the main memory. Determining when the main memory is accessed in the control signal timing generator;
It is used to determine the direction of data in the read direction or the write direction on the data bus.

The address information contains information as a part of the address in the address / control signal pair, and is stored in the temporary storage means. In this address information, a row address and a column address for the process or the processor to access the main storage unit are written, and this information is used by the control signal timing generation unit. Is accessed for the data at the specified address.

The bank information contains information as a part of the address in the address / control signal pair, and is stored in the temporary storage means. This bank information describes data indicating which bank of the main storage unit the process or the processor accesses, and the control signal timing generation unit uses this information to access the main storage unit. The bank is specified.

The operation of the order determining unit, the order storage changing unit, the output address generating unit, and the control signal timing generating unit in the rearranging unit will be described below. The order determination unit that determines the order of the address / control signal pairs stored in the temporary storage unit first changes the order based on the priority information.
Next, replacement is performed based on the difference between the row addresses in the address information and finally based on the difference between banks in the bank information, and the result is stored in the order storage replacement unit. Then, in accordance with the order stored in the order storage changing section, the output address generating section gives the temporary storage means an output address of the temporary storage means for reading out the contents of the temporary storage means. Further, in the control signal timing generator,
Using the address information, read / write information, and bank information in the address / control signal pair read from the temporary storage means, the main storage is accessed with good timing.

The temporary storage means may be provided with a write data section in addition to the address / control signal section. This write data section is used during a write operation, and the reason for providing the write data section will be described below.
In a DRAM, the timing of data access is different in the access timing of a control signal between a write operation and a read operation, and data at the time of writing is more accessible than data at the time of reading. In this case, the address / control signal pair is temporarily stored at the same time when the address / control signal pair is written in the temporary storage means.

With this configuration, it is determined that the information necessary for rearrangement in the temporary storage means is an empty flag, priority information, an address, bank information, read / write information, and a control number. And can be rearranged corresponding to each information. In addition, since the information set as the control signal is determined in advance, it is determined in which part the information necessary for each rearrangement is located.

Here, the rearrangement according to each information will be described. The information in the address / control signal pair written in the temporary storage means includes an empty flag, priority information, address information, bank information, read / write information, and a control number. The vacancy flag is used to indicate that there is vacancy for writing the address / control signal pair in the above-mentioned temporary storage means. The order determining unit and the order storage rearranging unit in the rearranging unit rearrange the access of the process or the processor.
Then, when rearranging the access, the information in the address / control signal pair is used.

First, the address / control signal pair storing portion where the empty flag is not set in the temporary storage means is stored in the address / control signal pair in the access from the process or the processor.
A control signal pair has been written. In the order determination unit, of the information in the written address / control signal pair,
Using the priority information, the address with the highest priority
The order of the access stored in the order storage rearranging unit is rearranged so that the order of the control signal pair is first. If there is none, the address information including the next row address is used, so that the order of the address / control signal pair having the same row address as that currently being executed is first.
The access order stored in the order storage rearranging unit is rearranged. If none of the above exist, the bank information is then used to rearrange the access order stored in the order storage rearrangement unit so that the access order of the bank currently being executed is different from that of the bank currently running. I do. The rearrangement based on the bank information is performed only in the main storage unit having the multiple bank structure. In the case of the main storage unit having the single bank structure, the rearrangement based on the bank information is not performed.

In accordance with the order stored in the order storage rearranging unit, an output address to the temporary storage unit for specifying the address / control signal pair is output from the output address generation unit to the temporary storage unit. Thus, a control number necessary for accessing the main storage section of the address / control signal pair from the temporary storage means and capable of specifying a process or a processor at the time of data input / output on the data bus, a row address and a column address , The bank information that can specify the bank in the main storage unit, and the read / write information that is information on whether to read or write to the main storage unit, are output to the control signal timing generation unit.

The control signal timing generator controls the main memory. Specifically, the control signal timing generation unit first specifies whether the access to the main storage unit is a read operation or a write operation by using the read / write information, and determines the data input / output operation according to the access operation. The timing is given to the data bus, the bank of the main memory is specified based on the bank information, and the specified bank is accessed for reading or writing according to the read / write information. Then, the row address is first extracted from the address information, and the main memory is informed that the row address is to be input. Next, a column address is extracted from the address information, and the main storage unit is notified of the input of the column address and is input. By doing so, it becomes possible to read or write to the main storage unit for a specific bank and a specific address. In the case of a DRAM, when the row address is the same, it is possible to access data at another column address without a time lag between the reset period of precharge and the period of starting up the region connected to the row address as described above. Yes, if the bank is different, access is possible without the time lag of only the reset period of precharge as described above, so if such address information or bank information enters the control signal timing generation unit, The main memory is accessed so as to eliminate the time lag.

[0047]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a multiple address holding storage device according to an embodiment of the present invention.
FIG. 2 is a block diagram of an address temporary storage unit of the multiple address holding storage device, and FIG. 3 shows a rearrangement unit of the multiple address holding storage device.

In FIG. 1 to FIG. 3, reference numeral 101 denotes a main storage unit for storing data to be accessed for the multiple address storage device. Reference numerals 105 to 107 are first to third processors. Reference numeral 207 denotes an address bus, and reference numeral 218 denotes a data bus for inputting and outputting data to and from the main storage unit 101. Reference numeral 103 temporarily stores an address / control signal pair to the main storage unit 101, which is received from the processors 105 to 107 as access to the main storage unit 101, and provides the main storage unit 101 with address and bank information. This is a temporary address storage unit that generates and controls data read / write control signals. Reference numeral 102 denotes a rearrangement unit that rearranges the order of the address / control signal pairs stored in the address temporary storage unit 103 according to the information of the address / control signal pairs.

Reference numeral 104 denotes a data output unit which adds a control number and outputs data read from the main storage unit 101 to the data bus 218. Here, the control numbers will be described. Since the address bus 207 and the data bus 218 are independent, a control number used as information for specifying access to the main storage unit 101 from the processors 105 to 107 is provided. In this case, a control number is assigned for each access from the processors 105 to 107, and the assigned control number is stored in the address temporary storage unit 103 as information added to the address / control signal pair accessed from the processors 105 to 107. Stored as an address / control signal pair. Then, when the address temporary storage unit 103 performs read and write operations on the main storage unit 101, any of the processors 105 to 107 on the data bus 218 can access the data bus 218. In order to identify whether or not the information is the control number, the control number is added. As a result, the specified processors 105 to 10
7 can read and write data.

Next, the control numbers and the respective processors 105 to 105
The relationship with the processor 107 and the operation of each of the processors 105 to 107 based on the control number will be described. The control number is, for example, “105” for the processor 105,
"106" for processor 106, processor 1
07 is assigned a number “107”. Then, the address / control signal pair to which the control number is added as a part of the information of the address / control signal pair is stored in the address temporary storage unit 103 via the address bus.

Then, with respect to the stored information of the address / control signal pair, the order of access to the main storage unit 101 is changed, and when control such as reading / writing to / from the main storage unit 101 is started, the data bus 218 is started. It is necessary to read and write data in. At this time, since the data bus 218 is independent of the address bus 207,
It is not possible to specify which of the processors 105 to 107 is the access. Therefore, by using the data bus 218 by adding a control number, when the data bus 218 is operating with the control number “105”, the processor 105 attempts to access the data bus 218 via the address bus 207. The data read / write operation is performed with the processor 105 in accordance with the information of the address / control signal pair. The same applies when the control numbers are “106” and “107”.

Reference numeral 108 denotes a main storage unit 1 from each processor from the first processor 105 to the third processor 107.
This is a priority determining unit that determines the priority of the access to be made to the 01. Specifically, for example, in the access performed by each of the first processor 105 to the third processor 107 to the main storage unit 101, the priority order determination unit 108
When the priority of the processor 107 is set to the highest priority of the first processor 105 and the priority of the third processor 107 is set to the lowest, the function of accepting the priority in the descending order of the priority according to the setting of the priorities. Having.

Reference numeral 111 denotes temporary storage means for temporarily storing the address / control signal pair accessed in the address temporary storage unit 103. The address / control signal for storing the extracted address of the temporary storage means and the control signal. Part 112
And a write data unit 113 for storing data to be written in the main storage unit 101. The write data section 113 is provided for the following purpose. That is, when data is written to and read from the main storage unit 101, the timing at which data is needed during control is different, and data is required at a timing earlier at the time of writing than at the time of reading. Also,
At the time of writing, since the data from the main storage unit 101 is not necessary for the processors 105 to 107, the data can be read from the processors 105 to 107 in advance. So, at the time of writing,
The write data is temporarily stored in advance together with the address and the control signal. The portion storing this write data is the write data section 113.

Reference numeral 109 denotes a free address checking unit for checking a free address in the temporary storage unit 111. Here, the empty address checking unit 109 will be specifically described. In the address / control signal unit 112 in the temporary storage unit 111, an area for storing a plurality of address / control signal pairs includes:
Each address that stores an address / control signal pair
For the address of the control signal unit 112, the address bus 2
The empty flag which becomes a high level when it is written from 07 to an address generated by an input address generation unit 110 described later, and becomes a low level when it is read out by the control signal timing generation unit 114, one by one. Have one. Address / control signal unit 1 whose empty flag is at low level
Twelve addresses are free. The address / control signal unit 1
Each of the empty flag signals at the 12 addresses is
The address of the address / control signal section 112 is connected so that the address can be specified, and the empty address check section 109 checks the low level of the empty flag to determine which address of the address / control signal section 112 has an empty area. It becomes possible to recognize.

Reference numeral 110 denotes an input address generation unit for generating an address of a control signal input to the temporary storage unit based on the result of the search by the free address check unit 109. A control signal timing generation unit 114 generates a main storage control signal for causing the main storage unit 101 to perform operations such as reading and writing at a good timing. In the control signal timing generation unit 114, the temporary storage unit 111
A main storage control signal is generated for the main storage unit 101 using the information of the address / control signal pair from the main storage unit.

Reference numeral 115 denotes an order determining unit that determines the order in which control signals are rearranged. This order determination unit 115
An address / control signal unit 112 having a CPU for comparison;
Is read out, and the information is compared with the information of the address / control signal pair in which the main storage section 101 is currently operating, as shown in the flowchart of FIG. In this order determination unit 115, an access is generated from the processors 105 to 107 and the
Each time an address / control signal pair is written to the control signal section 112, comparison and order determination are performed. The flowchart of FIG. 4 will be described later.

Reference numeral 116 denotes an order storage interchange unit for storing the rearranged order. In the order storage exchange unit 116, the order number and the address / control signal unit 11
2, the order number can be rewritten from the order determining unit 115, and the order number having the smallest value is output to the output address generating unit 117 as an address in the address / control signal unit 112. You. The sequence number is incremented each time one is read. The output address generation unit 117 has a function of outputting an address / control signal pair from the temporary storage unit 111 in the order of the order storage exchange unit 116.

Reference numeral 201 denotes rearrangement information, which indicates an address / control signal pair stored in the address / control signal section 112 of the temporary storage means 111. Reference numeral 202 denotes an output address output from the output address generation unit 117. Reference numeral 203 denotes a control signal for the main storage unit 101 that controls reading and writing of the main storage unit 101, including an address for the main storage unit 101. Symbol 204
Is a write data signal. Reference numeral 205 denotes an output control number output from the address temporary storage unit 103 to the data output unit 104. Reference numeral 206 denotes a read data signal read from the main storage unit 101. The code 208 is sent from the data output unit 104 onto the data bus 218 or sent from the data bus 218 to the address temporary storage unit 1.
03 is a data signal to be sent.

Reference numeral 209 denotes a first request signal for requesting access from the first processor 105. Sign 2
Reference numeral 10 denotes a second request signal for requesting access from the second processor 106. Reference numeral 211 denotes a third request signal for requesting access from the third processor 107. Reference numeral 212 denotes a first address / control signal pair output from the first processor 105. Reference numeral 213 denotes first processor data sent out on the data bus 218 to read and write the first processor 105. Reference numeral 214 denotes a second address / control signal pair output from the second processor 106. Reference numeral 215 indicates the second
This is the second processor data sent out on the data bus 218 to read and write the processor 106. 216 is the third output from the third processor 107
An address / control signal pair. Reference numeral 217 denotes a data bus 2 for reading / writing the third processor 107.
18 is the third processor data sent out.

Reference numeral 219 denotes a determination request signal output to the empty address checking unit 109 when a request from the processors 105 to 107 accepted by the priority determining unit 108 is determined. Reference numeral 220 denotes a vacant address of the address / control signal unit 112, which is a vacant address signal output from the vacant address checking unit 109 to the input address generating unit 110. Reference numeral 221 denotes an input address indicating an address in the address / control signal unit 112 to which an address / control signal pair output from the processors 105 to 107 to the address bus 207 is to be written. Reference numeral 222 denotes control information composed of an address / control signal pair read from the address / control signal unit 112, which is necessary for the control signal timing generation unit 114 to generate a main storage control signal for the main storage unit 101 with good timing. is there. Code 22
3 is written together with each address / control signal pair of the address / control signal unit 112, and
It is a control number indicating a number for specifying 07. Reference numeral 224 denotes an original write data signal output from the write data unit 113 that previously stores write data from the processors 105 to 107 when writing data to the main storage unit 101. Reference numeral 225 denotes an address
If the address is free for each address of a plurality of address / control signal pairs in the control signal section 112, the information is free flag information indicating that the address is free. Reference numeral 226 denotes the address / control signal unit 1 determined by the order determination unit 115.
12 is an order determination signal indicating which address / control signal pair and which address / control signal pair are to be exchanged among the access orders stored in the T.12. Reference numeral 227 denotes an output address determination signal indicating the address in the address / control signal unit 112 which is determined in order by the order storage switching unit 116 and output in the determined order.

Here, the plurality of processors 105 to 107
Request signals 209 to 211 and the address temporary storage unit 103
The relationship with the priority order determination unit 108 in FIG. It is assumed that the first processor 105, the second processor 106, and the third processor 107 request access to the main storage unit 101 at the same time. The request is request signal 2
09, 210 and 211. Request signal 20
When 9, 210 and 211 are output, they are input to the priority order determination unit 108 in the address temporary storage unit 103, and the first
When the priority of the processor 105 is the highest and the priority of the third processor 107 is the lowest, the priority determining unit 108 first accepts the access from the first processor 105 and sends a request to the first processor 105. Signal 2
09 to notify that the request is accepted.

When notified that the request has been accepted, the first processor 105 outputs an address / control signal pair to the address bus 207. At the same time, it outputs a decision request signal 219 to the free address checking unit 109 so as to receive an address / control signal pair from the first processor 105. Upon receiving the decision request signal 219, the free address checking unit 109 recognizes a free address in the address / control signal unit 112 using free flag information indicating that the address is free with respect to the free address. An empty address signal indicating an empty address is output to input address generating section 110. At this time, the empty flag information may include an empty flag for each address in the address / control signal unit 112.
The input address generation unit 110 converts the empty address signal into a write address to the address / control signal unit 112.
Output to the address / control signal section 112 as an input address.

Note that the priority order when a request is simultaneously sent to the main storage unit is determined by the priority order determination unit 108. In this embodiment, the first processor 105 and the second processor 10
6, the order of the third processor 107 is assumed. However, it is assumed that, after being taken into the address temporary storage unit 103, the priority operates according to the internal priority information. As the internal priority, one of the information written in the address / control signal pair of the address / control signal unit 112 includes priority information, and the priority information is used. It may be different from the priority in the processor.

The above-mentioned priority does not mean the priority of the processor, but means the priority in the access of the processor. Therefore, an important access in the present invention is not limited to a specific processor, but an access that requires a higher priority. With this kind of priority setting,
For example, when an access that requires real-time properties such as voice or image information arrives, a higher priority is set in the priority information of the address / control signal pair so that the priority of the access can be increased. The order determining unit 115 of the reordering unit 102 can order the corresponding address / control signal pair first so that the access can be performed first.

In the following description, it is assumed that the priorities are the same internally. In the case of a 16-bit address, the upper 8 bits are a row address and the lower 8 bits are a column address. When the row address is the same, the column address can be followed even if it changes every clock (page access).
It is assumed that the bank has a two-bank configuration of M and N, and when the banks are different, there is no need to precharge and continuous access is possible. Further, two clocks are required from the input of the row address until the column address can be input, and two clocks are required from the input of the column address to the output of the data. However, if the row address is the same and only the column address is different, only continuous access is possible. Then, four clocks are required as precharge. As a method of displaying an address, it is assumed that the leading 0x indicates a hexadecimal number, the next M or N indicates a bank, and the rest indicates the address itself. In addition, the address rearrangement process is performed every time an access is received from the processors 105 to 107. In this example, since the access is ABCD for each clock, the rearrangement process is performed for each clock. .

The address / control signal section 112 includes:
As data necessary for rearranging, for each address / control signal pair, an empty flag indicating whether or not an address / control signal pair is included in the storage portion, priority information indicating priority, address information indicating address, It is assumed that bank information indicating a bank, read / write information indicating read / write, and control number information indicating a control number are included. These pieces of information are stored in the address / control signal section 112 as follows. That is, for example, the processor 10 sets the priority information to be high when there is an access that requires real-time properties, and to be low when the data is rarely used even if it is late.
The processors 105 to 107 are generated by the processors 105 to 107, and address information, bank information, and read / write for accessing data of a specific bank and a specific address in the main storage unit 101 for reading or writing. The information is generated and stored in the address / control signal section 112 together with the priority information described above. At that time, the address / control signal unit 112 adds a control number that can specify the processors 105 to 107 and stores the control number as an address / control signal pair.

The read / write information is not used for controlling the rearrangement itself. However, the main storage unit 10
When the main memory control signal is generated for the data 1, the timing at which the data is required differs depending on whether the data in the main memory 101 is read or written, and the direction of the data is also reversed. It is included in the address / control signal pair. Also, the control number information is not used for the rearrangement itself, but is used for specifying the data access of the processors 105 to 107 on the data bus 208, and thus is similarly included in the address / control signal pair.

The operation in the case of the above specifications will be described below. The first processor 105 sends a message to the main storage unit 101
The data at the address of address 0xM0000 is read, and the second processor 106 writes 0xM
The data at the address of address 1200 is read, and the third processor 107 stores 0xM008 in the main storage unit 101.
The data at the address of address 0 is read, and the first processor 105 again writes 0xNA000 to the main storage unit 101.
The data at the address of the address is read.
, The first request of the third processor comes at the same time, and the request of the first processor comes after two clocks have elapsed. The timing chart is shown in FIG. In FIG. 5, A is the first request of the first processor, B is the request of the second processor, C is the request of the third processor, and D is the second request of the first processor.

The address / control signal pair is determined by the priority determining unit 108 in the order of the first processor to the third processor. Temporary storage unit 111
The free address checking unit 109 checks the free address of the input address using the free flag in the address / control signal unit 112, and inputs the free address to the input address generating unit 1 in the order of the request according to the priority.
Tell the free address to 10. The address / control signal pair is stored in the address / control signal section 112 based on the address generated by the input address generating section 110. The stored address / control signal pair is sent to the reordering unit 102 as reordering information 201, and reordering is performed. The reordering unit 102 has a configuration as shown in FIG. 3, and the order is determined by the order determination unit 115. The order determination by the order determination unit 115 is shown in the flowchart of FIG. The address 1 in this flowchart is the address where the address / control signal pair is stored in the address temporary storage unit 103. In the order determination unit 115, the address 1
In response to this, it is confirmed whether or not an address is included by using an empty flag in the address / control signal section 112. If the address is not included in the address 1, there is nothing and the address 1 is ignored. However, if the address is included, then check if the priority is the highest. In this case, since the priorities are the same, the order is not advanced, and it is checked whether the row addresses are the same. In this case, the access bank and row address of A and C are the same (0xM0000 and 0xM0000).
M0080), and since the access of A has already started at the time of the first priority determination, the next access is B
Instead, the order is moved up to C.

Next, whether or not the bank is different is examined. Here, there is an access of D with a different bank (D is 0xNA).
(Address 000), so that D is accessed after C. Thus, access is performed in the order of ACDB. The difference between the multiple address holding storage device in the single bank configuration is that the comparison of banks is not performed in the flowchart required when using multiple banks. The configuration of the connection of each part is the same.

In this way, the B data which is finally read out in 11 clocks after the row address is input to the main storage unit 101 comes out. On the other hand, if the access is normally performed in the order of ABCD, A and B
Are different row addresses in the same bank.
As shown in (4), four clocks in the precharge period are required, and when accessing C, four clocks in the precharge period are necessary. Therefore, the row address of the first A is read before the data of D is read out. 13 clocks are required after the clock is input. Therefore, in the present invention, the access time for two clocks is reduced as compared with the conventional example.

Here, a supplementary explanation will be given on the time chart of FIG. The address / control signal pair input to the temporary storage unit 111 is sent to the control signal timing generation unit 114 in the next cycle. Control signal timing generator 1
14 is sent to the order determination unit 115.
Since the exchange of the control signal pair is determined, the signal of A is output as it is in the next cycle, and the signal B after exchange is output in the next cycle. However, when the control signal timing generation unit 114 accesses the main storage unit 101, B is not accepted for two cycles because the row address is different, and an access of C having the same row address comes during that time. , The order storage interchange unit 116
Then, because B's access has not been accepted yet, C
Access first.

Next, the case where the read operation and the write operation are mixed will be briefly described. At the time of a write operation, when data is accessed from the processors 105 to 107 to the address bus 207, write data is written to the write data unit 113 of the temporary storage unit 111 using the data bus 218 so as to correspond to the address / control signal pair. It is. In addition, the address and
At the same time when the control signal pair is read by the control signal timing generator 114, the write data is also read by the control signal timing generator 114. Then, the control signal timing generator 114 outputs a main memory control signal and a write data signal to the main memory 101 using the address / control signal pair and the write data.

[0074]

According to the present invention, an address temporary storage unit capable of holding a plurality of addresses and holding a plurality of control signals corresponding to a plurality of addresses is provided in the main storage unit. An address input end, a stored address and control signal are sequentially supplied from the address temporary storage section to the main storage section, and a rearrangement section for rearranging the address and control signal is provided, and the order in which the main storage section is accessed is provided. Warazu access since to give an address and control signals from the temporary storage unit address interchanged in order to be fast to the main storage unit, to share the main storage unit of a plurality of processes or more processors written In such a case, the entire access time can be shortened.

Further , the rearrangement unit performs rearrangement in accordance with the access priority, and prioritizes rearrangement in accordance with the access priority over rearrangement in accordance with the order in which the access speed becomes high. It is possible to prevent the access of any process or the processor among the process or the plurality of processors from being postponed and the process of the process or the processor from stagnating.

[0076] According to multiple address holding memory device according to claim 2, wherein, since rearranged order to the address and control signals to access the address having the same row address are consecutive, access a plurality of turned fast process Alternatively, when the main storage unit is shared by a plurality of processors, the entire access time can be reduced. According to the multiple address holding storage device according to claim 3 , the addresses and control signals are rearranged in a sequence in which accesses to addresses in different banks are consecutive, so that the access speed is increased and a plurality of processes or a plurality of processors are provided. In the case where the main storage unit is shared by the above, the entire access time can be shortened.

According to the multiple address holding storage device of the fourth aspect , the same effect as that of the multiple address holding storage device of the first aspect is obtained. According to the multi-address holding storage device of the fifth aspect, the order of the addresses of the temporary storage means can be determined based on the address information, and the address and control signal are controlled so that accesses to the addresses having the same row address are consecutive. By rearranging, when the access speed becomes high and the main storage is shared by a plurality of processes or a plurality of processors, the entire access time can be shortened.

[0078] According to multiple address holding memory device according to claim 6, it is possible to determine the order of the address of the temporary storage means by the address information and bank information, so that the access to the address having the same row address are consecutive By rearranging the address and control signals,
When the main storage is shared by a plurality of processes or a plurality of processors due to high speed access, the entire access time can be reduced.

According to the multiple address holding storage device of the seventh aspect , the same effect as the multiple address holding storage device of the second aspect is obtained. According to the multiple address holding storage device of the eighth aspect, the order of the addresses of the temporary storage means can be determined based on the priority order information and the address information,
By rearranging the address and the control signal according to the priority information, it is possible to prevent the access of the process or the processor among the plurality of processes or the plurality of processors from being delayed so that the processing of the process or the processor is not stagnated. be able to. When the priority information is equal to or less than the same, the address and the control signal are rearranged so that the access to the address having the same row address is continued. Alternatively, when the main storage unit is shared by a plurality of processors, the entire access time can be reduced.

According to the ninth aspect of the present invention, the order of the addresses in the temporary storage means can be determined based on the priority information, the address information, and the bank information. By rearranging, it is possible to prevent the access of any process or processor among the plurality of processes or the plurality of processors from being postponed and the processing of the process or the processor to be stagnated. When the priority information is equal to or less than the same, access to addresses having the same row address is consecutively performed.
By rearranging the address and the control signal, when the access speed is increased and a plurality of processes or a plurality of processors share a main storage unit, the entire access time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an example of a multiple address holding storage device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an example of an address temporary storage unit of the multiple address holding storage device according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of an example of a reordering unit of the multiple address holding storage device according to the embodiment of the present invention.

FIG. 4 is a flowchart of an order determining unit in the rearranging unit.

FIG. 5 is a timing chart showing an access operation when rearranging.

FIG. 6 is a timing chart showing an access operation when rearrangement is not performed.

[Explanation of symbols]

 Reference Signs List 101 main storage unit 102 rearrangement unit 103 address temporary storage unit 104 data output unit 105 first processor 106 second processor 107 third processor 108 priority order determination unit 109 free address check unit 110 input address generation unit 111 temporary storage unit 112 address / Control signal section 113 Write data section 114 Control signal timing generation section 115 Order determination section 116 Order storage exchange section 117 Output address generation section 201 Rearrangement information 202 Output address 203 Control signal 204 Write data signal 205 Output control number 206 Read data signal 207 Address Bus 208 data signal 209 first request signal 210 second request signal 211 third request signal 212 first address / control signal pair 213 first processor data 214 Second address / control signal pair 215 Second processor data 216 Third address / control signal pair 217 Third processor data 218 Data bus 219 Decision request signal 220 Empty address signal 221 Input address 222 Control information 223 Control number 224 Original write data signal 225 Empty flag information 226 Order determination signal 227 Output address determination signal

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kazuichi Kusumoto 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Inside the company (72) Inventor Hiroshi Terada 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Takashi Hirata 1006 Okadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference Document JP-A-9-55081 (JP, A) JP-A-58-225432 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 12/00-12/06

Claims (9)

(57) [Claims] 1. A shared multi-address storage device for exchanging data with a plurality of processes or a plurality of processors, comprising: a main storage unit; a plurality of processes or the plurality of processors; an address bus for inputting a control signal for controlling an address for accessing part of the main memory unit, input and output data between the previous SL and a plurality of processes or the plurality of processors and said main memory unit A data bus, and an address provided at an address input end of the main storage unit and capable of holding a plurality of addresses input through the address bus and holding a plurality of control signals corresponding to the plurality of addresses. An address temporary storage unit for sequentially providing the control signal to the main storage unit while applying the control signal to the main storage unit; Permutation written Warazu access and a reordering unit for providing address and control signals from said address temporary storage unit interchanged in order to be fast to the main storage unit, according to the priority of access by the reordering unit
And sort according to the order of faster access
Priority is given to sorting according to access priority.
A multi-address holding storage device , characterized in that the storage device has a plurality of addresses. 2. The method according to claim 1, wherein the order of high speed access is the same row.
Order in which accesses to addresses having addresses are consecutive
2. The multiple address holding storage device according to claim 1, wherein: 3. A main storage unit having a multi-bank structure.
The order of faster access is to addresses in different banks
Access in a sequential order
Item 2. The multiple address holding storage device according to Item 1 . 4. A plurality of processes or a plurality of processors.
Of multiple shared addresses that exchange data with the
Storage device, the main storage unit, and the plurality of processes or
Accesses the main storage unit from the plurality of processors.
For controlling the main storage unit and the address for the
An address bus for inputting signals and the plurality of processes;
Alternatively, data is transferred between the plurality of processors and the main storage unit.
A data bus for inputting / outputting data, and an address of the main storage unit.
Input terminal through the address bus.
Multiple addresses held and multiple addresses supported
Multiple control signals can be held, and the held addresses are
At the same time, the control signal is given to the main storage unit.
The address temporary storage for the storage unit and the main storage
The order in which access speeds up regardless of the access order
In the first place, from the address temporary storage unit to the main memory
Rearrangement section for giving address and control signals to section
The address temporary storage unit accesses the main storage unit.
To temporarily hold address and control signals for
Time storage means, the plurality of processes or the plurality of processes.
To the main memory in the order of priority
Address and control signal reception for access
And an address for accessing the main storage unit and
Priority decision to output decision request signal when receiving control signal
To the main memory in response to the determination request signal.
Address and control signals for temporary access
Check the free address of the temporary storage means for storing
Free address checker and check by the free address checker
The free address of the temporary storage means based on the result of
As an input address for writing data to temporary storage
An input address generating unit to be provided;
An appropriate timer for accessing the output signal to the main memory
Control signal timing generation given to the main
And a rearranging section , wherein the rearranging section records each address of the temporary storage means.
Based on the stored address and control signal information,
An order determining unit that determines the order of addresses in the temporary storage unit
And an order description for storing the order determined by the order determining unit.
Storage unit and the storage contents of the order storage switching unit
Therefore, an output address for reading data is stored in the temporary storage means.
And an output address generating section for giving an address.
Multiple address holding memory device according to. 5. The method according to claim 5 , wherein said information is stored at each address of said temporary storage means.
The address and control signal information includes the temporary storage means.
An empty flag indicating that the address is empty, and
Address information indicating the address for accessing the storage unit.
In rare cases, the vacant address investigation unit
The free address of the temporary storage means is checked, and the order determination unit
The order of the addresses in the temporary storage means based on the address information
5. The method according to claim 4, wherein
Number address holding storage device. 6. A main storage unit having a plural bank structure,
Address and control stored in each address of the storage means
In the signal information, the address of the temporary storage means is empty.
Access to the main storage unit and an empty flag indicating that
Address information indicating an address and access to the main storage unit.
Bank information indicating the bank to be
The investigation unit determines whether the temporary storage means is empty based on the empty flag.
The address determination unit checks the address, and the
Address of the temporary storage means based on the bank information
The multi-address holding storage device according to claim 4, wherein the number is determined . 7. The temporary address storage unit accesses the main storage unit.
Address and control signals to access
Temporary storage means, and the plurality of processes or the plurality of
Determine the priority of the processor, and
Address and control signals to access the memory
Address and an address for accessing the main storage unit.
Priority for output of decision request signal when receiving control signal
A position determination unit, and the main storage unit in response to the determination request signal.
Address and control signal for accessing
Check the free address of the temporary storage means for remembering.
Vacant address checking unit, and the vacant address checking unit
Based on the result of the survey, the free address of the temporary storage
An input address for writing data to the temporary storage means;
An input address generating unit to be provided as a
These output signals are suitable for accessing the main storage unit.
Control signal to be given to the main storage unit at an appropriate timing
A reordering unit, wherein the reordering unit stores the information stored in each address of the temporary storage unit.
Based on the address and control signal information
An order determining unit for determining the order of the addresses of the storage means;
An order storage for storing the order determined by the order determining unit.
A reordering unit and the storage contents of the order storage reordering unit.
Output address for reading data from the temporary storage means.
And an output address generator for providing
2. The multiple address holding storage device according to claim 1, wherein: 8. The method according to claim 8 , wherein said information is stored at each address of said temporary storage means.
Address and control signal information includes access priority
Priority information indicating the order and the address of the temporary storage means
An empty flag indicating that the
It contains the address information indicating the address to Seth, free
The address investigating unit stores the temporary storage device based on the empty flag.
The empty address of the stage is checked, and the order determining unit checks the priority information.
Information of the temporary storage means based on the information and the address information.
Claims characterized in that the order of the Les
8. The multiple address holding storage device according to 7 . 9. The main storage section has a multiple bank structure,
Address and control stored in each address of the storage means
The signal information includes priority information indicating the priority of access.
And that the address of the temporary storage means is free.
And an address for accessing the main storage unit.
Access to the main storage unit
Includes bank information indicating the bank, and checks for free addresses
The unit stores an empty address in the temporary storage unit based on the empty flag.
Address, and the order determining unit checks the priority information and the address.
Based on the address information and the bank information.
An address order is determined.
8. The multiple address holding storage device according to claim 7 .