JPH08235855A - Clock synchronization type semiconductor storage device and its access method - Google Patents

Abstract

PURPOSE: To eliminate the generation of the cycle, in which clock cycle synchronized data output does not take place, by controlling the selection order of a scramble means in accordance with data access starting addresses. CONSTITUTION: Block cell groups A and B of a memory cell section are accessed in accordance with a least significant bit value of a row address. Then, four bit data including a column address are read from accesses cell groups A or B, transferred to a RWD line 8, held, read for every two bits and stored in a register 3. At that time, which two bits are to be transferred is selected by scramblers 2a and 2b. Each scrambler is controlled by the control signal generated by a control circuit 1 based on the condition of least significant two bits of the column address which is updated for every two cycles and the data output condition of reading registers R0 to R3. Then, by scanning the registers R0 to R3 with a certain order, data are outputted at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a clock synchronous semiconductor device capable of inputting / outputting data at high speed and an access method thereof.

[0002]

2. Description of the Related Art Previously, the author took in an address in a specific cycle of the basic clock in synchronism with the basic clock supplied to the system, and after a certain number of cycles counted from that cycle, input / output of data was started. A semiconductor memory device to be started was proposed (Japanese Patent Application No. 3-25535).
4). In the operation of the semiconductor memory device, there is a cycle in which data is not output from the time a row address is applied to the time data is output. Therefore, for example, if the row address is changed while data is being output in synchronization with the clock, a cycle in which no data is output will occur. Further, even in the case of the column address, it is not suitable to change the column address frequently to provide random accessibility. This point will be described in detail below.

The structure of the memory cell array of the semiconductor memory has a matrix structure composed of rows and columns in which a plurality of memory cells are regularly arranged. Generally, a series of cells belonging to a word line is selected by a row address,
The data of one cell in the word line selected by the column address is selected. For this reason, the time required from the confirmation of the row address to the output of data requires a longer time than the time required from the determination of the column address to the data output. Therefore, if a new row address is set during a series of clock-synchronized data output, the clock-synchronized data output may be interrupted because time is required to access the row with the new row address. become. This is called a cycle in which no data is output. Especially DRA
In M, the precharge time is always required before the access of a new row address, so that the interruption time of the output of each data becomes long. FIG. 2 is a diagram specifically showing a cycle in which the above data is not output. In the figure, first of all, the memory is accessed by the control signal row enable /
A row address is given when RE is in the "L" cycle (C
LK1), for example, when the control signal column enable / CE is in the "L" cycle after two cycles, the row address is applied to start access to a predetermined column of the memory cell group. This data can be exchanged with an external circuit after several cycles until output, for example, in the fourth cycle (CLK7) after giving a column address. Next, data is output for each cycle according to the determined order. The series of designated cell data after the row address is given all belong to the first given row address. In a DRAM, access from a row address takes time to sense cell data and hold it in a sense amplifier, but access to a column address only reads data held in this sense amplifier, which is relatively This is because the data can be read in a short time. Now, when the control signal / RE is set to "L" and a new row address is set, the data held in the sense amplifier until now is reset, and the sense system pre-setting is performed in order to sense the data of the new row. Needs to be charged. After this precharge is performed, a sensing operation is performed, and new column data is held in the sense amplifier. During the precharge period for this newly specified row, the data belonging to the previous row address is
It is possible to continue to output the data collectively read to the output register, but after the output for that amount is completed, the output operation is stopped because the data to be output has not been prepared yet. In the figure, data output can be continued from the cycle (CLK12) in which a new row address is set to three cycles (CLK15) later. In this example, it takes at least 6 cycles to output the data of the new row address.
There is a gap between two cycles of data output.

[0004]

As described above, in the conventional clock synchronous semiconductor device, when the designation of the row address is changed, the data output synchronized with the clock is interrupted, and the function as the clock synchronous memory is realized. There was a problem that it could not be fully demonstrated.

Further, regarding the data output in response to the change of the column address, as shown in FIG. 4, in the semiconductor memory device proposed by the author (see FIG. 3), the memory cell group 32 is collectively transferred to the serial register 37. Then, since the data for one column is transferred, the column address cannot be arbitrarily changed within the cycle required to output the data for the length of the serial register 37. That is, in this case, the serial register 37 is always accessed in a fixed order for high-speed access to the memory cell, and the head of the access to the register 37 can be determined only when the data is collectively transferred to the register 37. Because you can. Therefore, in this example, as the number of bits of the serial register 37 increases, the characteristic of the random accessibility disappears.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to change a row address in a clock cycle in a conventional clock synchronous access system. Eliminates the occurrence of cycles in which synchronized data output is not performed,
Regarding the column address as well, a system that allows clock-synchronous access by changing to a new column address in a cycle that is determined only by the time required for data transfer inside the memory cell regardless of the length of the output serial register To provide.

[0007]

In order to solve the above-mentioned conventional problems, the clock synchronous semiconductor memory device according to claim 1 of the present invention comprises a plurality of memory cells arranged in rows and columns. The memory cell has a memory having a structure divided into a plurality of blocks, and a plurality of registers for temporarily accumulating a set of access data for performing data access between the memory and the outside. A scrambler for selecting whether to store the access data, and a scrambler control for controlling the scrambler to cyclically store the access data in each of the registers in a predetermined order for each cycle of a clock signal. The scrambler comprises a circuit and output means for exchanging data with the register and the outside. Control means is characterized by having a function of setting the selection order of the scrambling means and the head address is given for the data access starting in a predetermined order.

Further, in the access method of the clock synchronous semiconductor memory device according to the present invention, it is composed of a plurality of memory cells arranged in rows and columns, and the memory cells are divided into a plurality of blocks. The data access between the memory and the outside is performed in synchronization with the clock signal, and the data access between the memory and the outside is performed in a plurality of registers. Therefore, a set of access data is temporarily stored and scrambled by the scramble means. , Which of the registers stores the access data, and the scrambler control circuit cyclically accesses the scramble means to each of the registers in a predetermined order for each cycle of the clock signal. Data is controlled to be stored, and the output means outputs the data to and from the register. Exchanges, by the scramble control unit, and sets the selection order of the scrambling means every time the start address is given for the data access starting in a predetermined order.

In the clock synchronous semiconductor memory device and the access method described above, the active memory cell block is changed every time a part of the bits of the row address as the address data designating the block is changed to change the pre-active state. While the data from the appropriate memory cell block is being output from the serial register, the newly active memory cell block is accessed to eliminate the cycle in which new data is not output from the row address to the data output. Also, when storing data from the memory cell block to the output serial register, data is stored for each part of the constituent elements of the register,
At that time, by storing data in the register according to the data order determined according to the given column address, the serial register access order is always constant and high-speed operation is performed, and it is sufficient for frequent column address changes. I am able to deal with it.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a clock synchronous semiconductor memory device according to the present invention. In the figure, the memory cell portion is divided into two block portions A and B, and this block portion is selected, for example, by changing the value of the least significant bit of the row address as address data designating the block. When a row address is given to each of the block cell groups A and B, the block cell group corresponding to the value of the least significant bit of the address starts the access operation, and the other block cell group can enter the access operation standby state. For example, the block cell group is put into an access operation standby state to operate. For example, when a DRAM cell is used, the cell array must be precharged before the access operation. However, when access to the cell group that has been in the precharged state is started, the other cell group is started. Now start precharging and prepare for the next access. When a cell group that is not in the standby state for access is selected, the access operation of the cell group first starts precharge, and then the access operation is started after the access operation standby state.

FIG. 5 shows the operating condition of this cell group. In the figure, the checkered cycle represents the preparation standby period for the access operation. In FIG. 5, the control signal /
Every cycle when RE is “L” (CLK1, 7, 13, 2
In 3), the cell group is supposed to be accessed in the order of A, B, B, A. Cycle in which A enters access state (CLK
Two cycles (CLK3) after 1), B enters the standby state (checker pattern 51) for the next access operation. Next, when B enters the access state (CLK7) and two cycles later (CLK9), A enters the access operation standby state (checker pattern 52). Next, B accesses again (CLK13)
Then, B immediately waits for access (checker pattern 5
After entering 3) and preparing for the access operation, the access operation state is set. The same operation is repeated thereafter depending on the row address and the access state of the cell group.

As for the access method for each block, the following access method can be considered in addition to the above-mentioned embodiment. For example, when a row address is given to the block cell groups A and B, the access operation is started if the block cell group corresponding to the block selection bit value in the row address is in the access operation standby state, and the access operation is already performed. If it is in the operating state, the access is ignored so that the access waiting state must be passed. That is, in order to enter the access standby state, a block cell group is designated by an address bit for block selection, and an instruction signal for setting the standby state is given. For example, when a DRAM cell is used, the access operation starts as soon as the block cell group that has been in the precharged state until now is selected, while the existing word line is selected and the cell data sensing is completed. If the block cell group in the selected state (read start complete state) is selected and the selection command selects another word line, the access operation is ignored and the cell belonging to the already selected word line is ignored. If it is selected, data reading is started from the cell (according to a method described later).

The timing chart shown in FIG. 10 shows the operating condition of the cell group in this case. As for the command signal included in the precharge, the control signal / RE and the write enable signal / WE are set to "L" at the same time. In the same figure, the checkered cycle represents the preparation standby period for the access operation, as in the case of the embodiment shown in FIG. In the embodiment of FIG. 10, as in the embodiment of FIG. 1, every cycle of the control signal / RE being "L" (CLK1, 7, 1).
7, 23), the cell group is accessed in the order of A, B, B, A. The embodiment of FIG. 10 shows the timing of the input signal for providing the preparation standby period for the access operation as in the embodiment of FIG. Two cycles after the cycle (CLK1) in which A enters the access state (CLK3)
Then, the control signals / RE and / WE are set to "L" to select the B cell group, and the standby state for the access operation (checker pattern 10
Enter 1). Next, B enters the access state (CLK
7) The control signals / RE and / WE are set to "L" (CLK9) in order to put the subsequent block cell group A in the access standby state (checker pattern 102). Next again, block cell group B
To access the block cell group B to the access waiting state (checker pattern 103), the control signals / RE and / W.
It is set by setting E to "L" (CLK13). In the cycle (CLK17) in which the access preparation of the block cell group B is completed, the control signal / RE is set to "L" to start the access operation of the block cell group B. Thereafter, the same operation is repeated to perform the access operation.

Returning to FIG. 1, for example, 4-bit data including a column address given from the cell group which has entered the access state is read out, and the four RWD lines are read through the data transfer lines DLNa and DLNb. Read out. These data are read out every 2 bits and transferred to the register. However, which 2 bits to transfer is determined based on the control signal output from the scrambler control circuit 1 depending on the state of the lower 2 bits of the column address that can be updated every 2 cycles and the data output state of the read registers R0 to R3. Scramblers 2a-2d. The data output from the registers R0 to R3 realizes high-speed data output by always scanning the registers R0 to R3 in a fixed order. The access order of these registers R0 to R3 is always constant, and the corresponding access to the new column address is
Data is scrambled by data transfer from 0 to R3 so that data access can be started from an arbitrary address. For this reason, it has become possible to realize high speed and randomness in which the start address can be changed in a cycle (two cycles in this case) determined only by the data transfer time from the cell groups A and B. In this example, since the data output from the cell groups A and B is transferred in units of 4 bits, the address change of serial access is such that the lower 2 bits of the column address go through all four states from the top address. Make a change. For example, 0, 1, 2, 3; 1, 2, 3,
0; 2, 3, 0, 1; 3, 0, 1, 2, etc.

The write operation may be considered in the reverse order of the data output, and the data is always written in the write register in a fixed order and the data is transferred to the cell group through the scrambler by 2 bits. At this time, the cells capable of accessing the cell groups A and B are in blocks of 4 bits, as in the case of the read operation.

Next, the data transfer method in the read operation will be described in more detail with reference to FIG. The data read from the four columns (for example, A1) simultaneously designated by the column address excluding the least significant 2 bits are transferred in parallel and held until the next data is transferred to the four RWD lines 8. To be done. During this data holding period, 2-bit data is transferred through the scrambler circuit controlled by the signal generated from the scrambler control circuit 1 according to the scramble determined by the information of the currently accessed registers R0 to R3 and the start address. It is transferred to the registers (RG1, RG2). Data output from the registers R0 to R3 is continuously performed by accessing the registers R0 to R3 in a fixed order. In the figure, always R0 → R1 → R2 → R3 → R0 → ...
The data is cyclically output from the register to the outside in the order of. This cyclically accessed register R0-R
Data is stored in the scramblers 2a and 2b in 3, but since the data is stored in every two registers, the head address of the cyclic access can be changed every time this storage is performed. The settings such as the length of the register and how many bits to store the data collectively can be determined by how many registers are accessed before new data is transferred to the RWD line 8. In this embodiment, it is assumed that data of arbitrary 4 columns is transferred from the cell block to the RWD line 8 in 2 cycles of accessing the registers R0 to R3. By the way, in FIG. 6, a group of four columns A1
Although only five A5 to A5 are drawn, it goes without saying that any number may be used depending on the size of the memory. The specific configuration of the scramblers 2a to 2d and the connection relationship between the RWD line 8 and the registers R0 to R3 will be described later, but the data flow will be described first with reference to the timing chart.

FIG. 7 shows a flow in which data is transferred to each part of the registers R0 to R3 shown in FIG. 6 every cycle of the basic clock CLK. Each time the basic clock rises, the registers R0 to R3 are always accessed in a fixed order. The access start address can be changed in the access start cycle of the registers R1 and R3 (eg, CLK1, DLK3). As shown in FIG. 7, in this cycle, the control signal / CE is set to "L" to take in the column address and set it as a new head address. RWD states shown are 0 to 3 RWD
The line shows the period during which data is latched. It takes about 2 cycles (CLK3) from the cycle (CLK1) where the new address is set, and the new data is RWD.
Line to change the state of the RWD line. RWD if no new address is set (eg CLK7)
The line may maintain the data holding state as it is. Also,
A counter in the chip may automatically generate an address every four cycles from the last address setting and the address may be automatically incremented.

The register transfer period indicates the data transfer period to the register groups RG1 and RG2 each consisting of two registers, and is R when "H".
It is a data load period to G1 and to RG2 when "L". The scrambler state is shown under the register transfer period. The scrambler setting is maintained unless a new address is set. When the address is incremented by the internal counter, the scrambler state does not change. That is, the data transferred to the RWD line changes in the next 4 columns and the next 4 columns, and there is no change in the order within 4 bits of the data output from the register. The states of the registers RG1 / RG2 are shown by the thick line RG1 and the thin line RG2, and when the data is "H", the data is loaded into the register.
Data is held when it is "L". The held data is output to the outside as output data by cyclically accessing the register in each cycle.

FIG. 8 is a concrete configuration diagram of the scramblers 2a to 2d. The specific operation of the scrambler using this is shown below. Figure 8 shows four RWD lines 8
And a data transfer path to one register. Actually, there are the same number of circuits as the number of registers (omitted in FIGS. 1 and 6). In each circuit, the signal input to the clocked inverter is different.

Table 1 shown below is a table of control signals input to the clocked inverter. When this signal is "H", the clocked inverter functions as an inverter.

[0022]

[Table 1]

In the above table, for example, in the case of the register of R2, the signal is input with α = c, β = d, γ = a, and δ = b. Signal a to select this clocked inverter,
b, c and d are determined by which register group, RG1 and RG2, is being accessed in the cycle in which the head address is newly set, and what is the least significant 2 bits of the column address. This is the output of the scrambler control circuit. Table 2 below shows a table of the output logic of the scrambler control circuit.

[0024]

[Table 2]

In the above table, for example, the control signal / CE is set to "L".
In the cycle in which the register group RG2 is being accessed when the column address is fetched in the above manner, if the least significant 2 bits (A1, A0) of the column address are (0, 1), only b is "H". And this scrambled signal is
It is set in the scrambler when the data of the address that determines the scramble is taken into the register. In the present example, R0 is connected to RWD1, R1 is connected to RWD2, R2 is connected to RWD3, and R3 is connected to RWD0.

The effect of the clock synchronous memory device having the system configuration of this embodiment will be described below with reference to the overall configuration diagram of FIG. 1 and the operation timing diagram of FIG. That is, it will be described how data can be output for each cycle without any gap in data output with respect to changes in row and column addresses. In the timing diagram shown in FIG. 9, for convenience, the data output (A
out, Bout) are shown separately, but since data is actually output from the same output buffer, data output is continuously output in each cycle. Now, control signal /
Cycles in which RE is "L" (CLK1, 9, 15, 2
In 1), it is assumed that the row address is set in the order of A, B, A, B. Then, the leading column address is also updated every two cycles. That is, it is assumed that the randomness of the column address is incorporated as much as possible. First, in the second cycle (CLK3) from the cycle (CLK1) in which the row address of A is set, the cell group B which has been in the access state until now starts the precharge operation. Therefore, the data state of the data transfer line DLNb from the cell group B becomes uncertain. This state is shown by hatching 91 in the figure. Now,
The RWD line 8 holds the data of which DLNa or DLNb is fixed. The data held on the RWD line 8 is transferred to the register. The transferred data is DLNa or D as shown in FIG.
It is the same as the data determined by LNb. In the state of the register RG1 / 2 in FIG. 9, the thick line indicates the state of the register group RG1, and the thin line indicates the state of the register group RG2. In each case, the state of "H" is the data transfer period to the register. Therefore, before the cell group B enters the precharge, the data of CLNb is stored in the register group RG1.
And transferred to RG2. While these data are being output, the data from the cell group A is read out to the DLNa and fixed. This data is output to register RG1
Transferred to. After 2 cycles, the data from the column determined by the next column address is confirmed in DLNa,
This data is transferred to the register group RG2 for which data output has been completed. Similarly, data is continuously output to the register and data is output without interruption. When data is transferred to the register, as described above, the scrambler control circuit 1 operates according to the column address to store the data in the register so that the data is output to the register group in a predetermined order. It As described above, according to the system of the present invention, continuous data transfer and random access as frequently as possible can be realized in a memory that operates at high speed cycles.

[0027]

As described above, according to the present invention,
Changing the active memory cell block each time some bits of the row address are different, and accessing the new memory cell block while the data from the previously active memory cell block is being output from the serial register. Thus, it is possible to eliminate the cycle from the row address to the data output in which new data is not output. Furthermore, when storing data from the memory cell block to the output serial register, the data is stored for each part of the register, and at that time, the data is stored in a predetermined data order according to the given column address, so that the serial It is possible to provide a semiconductor memory device of a clock synchronous access system and a method of accessing the same, which is capable of coping with high-speed and frequent column address changes while keeping the register access order constant.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock synchronous semiconductor memory device of the present invention.

FIG. 2 is a timing diagram showing the relationship between row address settings and output data in a conventional clock synchronous semiconductor memory device.

FIG. 3 is a block diagram of a conventional clock synchronous semiconductor memory device.

FIG. 4 is a timing diagram showing the relationship between row address settings and output data in a conventional clock synchronous semiconductor memory device.

5 is a timing diagram illustrating an operation for a row address in the clock synchronous semiconductor memory device shown in FIG.

FIG. 6 is a block diagram illustrating in detail a data output method of the clock synchronous semiconductor memory device of the present invention.

FIG. 7 is a timing diagram illustrating an operation for the column address shown in FIG.

8 is a specific circuit configuration diagram of the scrambler circuit shown in FIG.

FIG. 9 is a timing chart showing the data output operation and characteristics of the clock synchronous semiconductor memory device of the present invention.

10 is a timing chart illustrating another operation of the clock synchronous semiconductor memory device shown in FIG.

[Explanation of symbols]

1 ... Scrambler control circuit, 2a-2d ... Scramble circuit, 3 ... Read register, 4 ... Write register, 5 ... Output buffer, 5 ... Input buffer, 8 ... RWD
line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shozo Saito No.580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Semiconductor System Technology Center

Claims (6)

[Claims] 1. A memory comprising a plurality of memory cells arranged in rows and columns, the memory cells having a configuration divided into a plurality of blocks, and a group of blocks for performing data access between the memory and the outside. A plurality of registers for temporarily accumulating access data, a scramble means for selecting whether to store the access data in any one of the registers, and a register for the scramble means for each cycle of a clock signal. A scrambler control circuit that cyclically stores the access data in a predetermined order, and an output unit that obtains data from the register and the outside, and the scramble control unit is a data access unit. Each time the start address for starting is given, the order of selection of the scramble means is changed. Clock synchronous semiconductor memory device characterized by having a function of setting a constant of the order. 2. The clock synchronous semiconductor memory device according to claim 1, wherein the register is composed of a plurality of registers for input and a plurality of registers for output, and each of the registers for output is It is divided into m groups of register blocks each consisting of a registers.
n = a × m (m, n is a positive integer) is set equal to the number of data transferred from the block for data access, and the number of data is set in the register every a cycle of the clock signal. A clock synchronous semiconductor memory device, wherein the scramble control means changes the selection order of the scramble means each time the data is stored. 3. The clock synchronous semiconductor memory device according to claim 2, wherein a time T required for a cycle of a minimum unit of the clock signal is T.
A clock synchronous semiconductor memory device, wherein xa is set to a value equal to the time required to store the access data from the block into the register. 4. A memory comprising a plurality of memory cells arranged in rows and columns, the memory cell executing data access to the outside and a memory having a configuration divided into a plurality of blocks in synchronization with a clock signal, In order to perform data access between the memory and the outside in a plurality of registers, a set of access data is temporarily stored, and scrambling means selects whether to store the access data in any of the registers. The scrambler control circuit controls the scramble means to cyclically store the access data in each of the registers in a predetermined order for each cycle of a clock signal, and outputs the data to and from the register and the outside. And the scramble control means is used to transfer data Access method of clock synchronous semiconductor memory device and sets the selection order of the scrambling means each time the address is given in a predetermined order. 5. The access method for a clock synchronous semiconductor memory device according to claim 4, wherein the register comprises a plurality of registers for input and a plurality of registers for output, and the register for output is , M groups of register blocks each consisting of a registers, n = a ×
Set m (m and n are positive integers) equal to the number of data transferred from the block for data access,
A clock synchronous semiconductor memory device, characterized in that the number of data is stored in the register every a cycle of the clock signal, and the scramble control means changes the selection order of the scramble means every time the data is stored. how to access. 6. The method of accessing a clock synchronous semiconductor memory device according to claim 5, wherein a time T required for a cycle of the minimum unit of the clock signal is T.
A method of accessing a clock synchronous semiconductor memory device, wherein xa is set to a value equal to a time required to store the access data from the block into the register.