JPS63188882A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To attain write/read asynchronously by providing a timing circuit selecting a 1st register and writing a bit data and a timing circuit moving the bit data to a 2nd register and selecting and reading it. CONSTITUTION:A clock address circuit 2 receiving the supply of a clock 1(b) supplies an address signal to a clock selection circuit 3. The circuit 2 selects sequentially L1-L8 of the register 1 in a ring and an input data 1(a) is written sequentially in the register 1. A delay setting circuit 4 receiving the supply of the clock 1(b) reaches a prescribed count, then the circuit 4 gives a delay signal (f) to a crystal oscillation circuit 6. The circuit 6 receiving the signal (f) outputs a gate clock (g) to a clock address generating circuit 7 and a selection address circuit 9. The circuit 7 supplies an address signal (h) to the clock selection circuit 8. Thus, the storage data (e) stored in the register 1 is written in the register 5. Moreover, the circuit 9 gives an address signal (j) to the data selection circuit 10 and the stored data in the register 5 is read sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used in devices and systems that perform data transmission, and writes and reads data with asynchronous timing using one timing clock and another timing clock. The present invention relates to a signal processing circuit that executes the processing.

2. Description of the Related Art In the prior art, when writing and reading bisoto data from a memory, a method was used in which the writing timing and the reading timing were synchronized.

Problems to be Solved by the Invention However, in the conventional technology in which the timing of writing and reading from memory is synchronized, it is not possible to perform writing and reading simultaneously, let alone asynchronously. .

An object of the present invention is to enable writing and reading to be performed asynchronously and simultaneously.

Means for Solving the Problem In order to solve this problem, the present invention sequentially selects registers for a plurality of bits of first registers that store input bit data in a serial or parallel state, and stores the bit data. the first one that supplies the clock input with
means for controlling accumulation of bit data by a clock selection circuit and a first clock address generation circuit for supplying an address for selecting the first register to the first clock selection circuit; The bit data accumulated in the register of the second register of the other multiple bits
a second clock selection circuit that sequentially selects and supplies a clock to registers to be moved to the register; and a second clock selection circuit that supplies an address for selecting the second register to the second clock selection circuit; The first register is connected to a clock address generation circuit and a crystal oscillation circuit that generates a clock at a timing that is asynchronous with the clock supplied to the first register and is delayed by a predetermined clock amount set by a delay setting circuit. The accumulated bit data of
means for moving the bit data to a register; a data selection circuit for sequentially selecting the second register to extract serial data; and a selection address for selecting the second register for the data selection circuit. It has a selection address circuit for generating and a means for extracting data at a bit data timing which is asynchronous with the data timing.

Function The present invention is capable of writing and reading by using a timing circuit that selects a first register storing bit data and writes the bit data, and a timing circuit that moves the bit data to a second register and selects and reads the register. The timing will be operated asynchronously.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2.

In Figure 1, 1 is a register, and the figure shows an 8-bit register, in which bit data 1 is sent to the clock selection circuit 3.
The data is taken into the register 1 (L1 to Ls) selected by the clock 1 at the timing of the clock 1. 2 is clock address generation circuit 1
Then, a selection address is generated to the clock selection circuit 3 which selects the clock to be supplied to the register 1. A clock selection circuit 3 supplies a clock 1 for sequentially selecting the register 1 with the address from the clock address generation circuit 2 and writing bit data 1 therein. 4 is a delay setting circuit, register 6
A gate is applied to the crystal oscillator circuit that generates the clock 2 for reading data, thereby delaying the clock 2. 5 is a register, and the figure shows an 8-bit register, and the bit data accumulated in register 1 is sent to clock selection circuit 8.
It is read out at the timing of clock 2 selected in . 6 is a crystal oscillation circuit that generates a clock 2 for reading the sibit data from the register 76; This oscillation is controlled by a gate from the delay setting circuit. A clock address generation circuit 7 generates a selection address to a clock selection circuit 8 which selects a clock to be supplied to the register 6. 8 is a clock selection circuit, which connects register 5 to clock address generation circuit 7.
A clock 2 is supplied to write bit data 1 stored in register 1 by sequentially selecting addresses from . 9
is a selection address circuit which generates a selection address for the data selection circuit 1o at the timing of clock 2.

Reference numeral 10 denotes a data selection circuit which sequentially selects the bit data read out at the clock 2 using the address selected by the selection address circuit 9 and rearranges it into serial bit data.

a is input bit data 1, data to be written to register 1, b is clock 1, input bit data 1 to register 1
C is the clock for writing to register 1, C is register 1
d is a write clock that selects and supplies clock 1b to register 1 according to address signal C, and the timing for L1 to L8 is the clock address generation. Determined by circuit 2, e is storage (latch) data of input bit data a, f is a delay signal that delays the read clock 2 of register 5, g is a gate clock gated by delay signal f, and h is Address signal i for selecting a clock for writing accumulated data e into register 6
is a read clock that is selected and supplied to the register 5 according to the address signal, and the timing of signals L11 to L88 is determined by the clock address generation circuit 7. j is a data selection address signal for selecting the read position of the register 5, k is the read data read out by the read clock i selected by the clock selection circuit 8, and 1 is the data selected by the data selection circuit 1Q. The input bit data a and the asynchronous output bit data are respectively shown.

Next, the specific operation will be explained.

At the same time as the input bit data 11L is input, the clock 1b is also input at the same time as the input bit data a. The clock address generation circuit 2 that receives the clock 1b starts counting up at the timing of the clock 1b, and supplies a binary output as the address signal C to the clock selection circuit 3. When the clock selection circuit 3 that receives the address signal C is a binary signal and all signals are 0, the register 1
It operates to select Ll of 0o0 with binary signal.
If it is 1'', L2 of register 1 is selected, and if the binary signal is '0111', L8 of register 1 is selected. The clock address generation circuit 2 sequentially selects L1 to L8 of the register 1 in a ring shape by repeating binary signals from 'oooo' to '0111''. A write clock d is sequentially supplied to the selected register 1. Therefore, input bit data 11L is sequentially written into register 1 as L1 to L8.

The clock 1b is also supplied to a clock address generation circuit 2, a clock selection circuit 3, and a delay setting circuit 4. The delay setting circuit 4 receiving the clock 1b counts the clock 1b, and when a predetermined count is reached, supplies the delay signal f to the crystal oscillation circuit 6.

This count number is arbitrarily set and determined by the phase difference between the write timing and the read timing to output data.

The crystal oscillation circuit 6 that receives the delayed signal f is prohibited from outputting by an internal gate circuit even if it normally oscillates, and when it receives the delayed signal f, the date circuit opens and outputs the gate clock g. .

For example, if the delay signal f is set to '4'', the gate clock g
is output. The clock address generation circuit 7, which receives the gate clock g, starts counting up at the timing of the gate clock r, and supplies a binary output to the clock selection circuit 8 as an address signal. The clock selection circuit 8 receiving the address signal operates to select Lll of register 6 if all binary signals are °○'', and if the binary signal is °'oo○1'', it selects L22 of register 5. Select, and then input “01” with a binary signal.
11", it operates to select Lsa of the register 5.Then, the clock address generation circuit 7 operates to select "0".
By repeating the binary signal of ~7'' at the timing of the gate clock g, L11 to L88 of the registers 5 are sequentially selected in a ring shape.The read clock i is sequentially supplied to the selected registers 5. clock i
Accordingly, the accumulated data e of the input bit register 1a, which has been accumulated in the register 1, is written into the register 5.

The selection address circuit 9, which receives the gate clock g from the crystal oscillation circuit 6, generates a binary output data selection address signal j, similar to the clock address generation circuit 7.
is supplied to the data selection circuit 1o. The data selection circuit 1o, which has received the data selection address signal j, sequentially selects the accumulated data sequentially read out from the register 5 by supplying the readout clock main at the timing of the readout clock g, and outputs bit data. Output as 1.

Next, the timing will be specifically explained with reference to FIG. It is assumed that the data flow direction is from left to right on the drawing. First, input bit data 1a and clock 1b are input simultaneously. Input bit data 1a is written to register 1 at the timing of clock 1b.

In the figure, the rising edge of the clock 1b is written as "C".

Next, the method for selecting register 1 is as shown by address signal C in the figure. L1~L8
supply a selection clock to the In the figure, "000" selects and writes Ll, "001" selects L2, and j11179 selects and writes L8. Register L1. L2. L4 indicates the write state. The delay signal f is the set value ++
Assuming that it is set to 411, it is turned on when clock 1b is counted for four clocks. The delayed signal f
The gate clock g controlled by the clock address generating circuit 7 and the clock selecting circuit 8 is sequentially supplied to each of the registers 6 in the same manner as in the write state of the input bit data 12L. Register L11. Register L22 indicates the movement and accumulation state of the accumulation data e. With the read clock 1 supplied to this register 5, the read data k is sent to the data selection circuit 10.
When sequentially selected by , output bit data 1 is formed.

As is clear from the above explanation, input bit data and output bit data are written and read completely asynchronously. In other words, writing and reading can be considered separately, and there is no need for both to be synchronized as in the past, and writing and reading can be achieved with rough timing.

Effects of the Invention According to the present invention, it is possible to supply write and read timing to a register (memory) independently of both timing clocks with a simple configuration, and write/read can be realized asynchronously.

Furthermore, bit data can be output with an arbitrary delay by changing the setting value of the delay setting circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a signal processing circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing timing in the block diagram. 1...Register, 2...Clock address generation circuit, 3...Clock selection circuit, 4...
...Delay setting circuit, 5...Register, 6...
...Crystal oscillation circuit, 7...Clock address generation circuit, 8...Clock selection circuit, 9...
...Selection address circuit, 1o...Data selection circuit.

Claims (1)

[Claims] A first clock selection circuit that sequentially selects registers for a plurality of bits of first registers that store input bit data in a serial or parallel state and supplies a clock input together with the bit data; means for controlling accumulation of bit data by means of a first clock address generation circuit supplying an address for selecting the first register; a second clock selection circuit that sequentially selects and supplies clocks to registers in order to move the bits to the second register; and supplies an address for selecting the second register to the second clock selection circuit; and a crystal oscillation circuit that generates a clock asynchronously with the clock supplied to the first register and delayed by a predetermined clock amount set by a delay setting circuit. a data selection circuit for sequentially selecting the second register to extract serial data; and a data selection circuit for sequentially selecting the second register to extract serial data; 1. A signal processing circuit comprising: a selection address circuit for generating a selection address for selecting a register; and means for extracting data at a bit data timing asynchronous with input bit data timing.