JPH03131899A - Pattern conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the number of times of an instruction fetch cycle, to reduce a load on a CPU, and to accelerate conversion speed by selectively taking out data at a designated bit position, and outputting data of (n) bits taken out as a result of readout for (n) times from a memory. CONSTITUTION:A control means 6 issues a readout signal to the memory 1 for (n) times corresponding to the column readout instruction of the CPU 5, and an address designation means 7 performs the address designation of data of (m) bits which belongs to the same column of pattern data corresponding to the issuance of the readout signal from the control means 6. Also, a bit position designation means 8 designates a bit position. A selection means 10 selectively takes out the data at the bit position designated with the bit position designation means 8 at every readout of the data of (m) bits whose address is designated with the address designation means 7 from the memory 1 based on the readout signal, and outputs the data of (n) bits taken out as the result of readout for (n) times from the memory 1. In such a way, it is possible to reduce the number of times of the instruction fetch cycle, and to reduce the load on the CPU, and to accelerate the conversion speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern conversion circuit that reads and outputs pattern data of M columns and XN rows written in a memory in the column direction.

[Prior Art] (1) Background In recent years, information processing devices such as word processors that handle pattern data such as image data have come into use.

Such information processing equipment uses a pattern conversion circuit that converts the direction of pattern data stored in a memory by 90 degrees and outputs the result.

(2) Memory and pattern data structure Figure 6 shows 8
A bit-wise accessible memory 1 is shown, and each row of the pattern memory 1 has 0.1.2 . ... has been assigned an address.

FIG. 7 shows the structure of pattern data stored in the memory 1. If the pattern data stored in memory 1 is data consisting of unit pattern data arranged in 3 rows x 5 columns, and furthermore, this unit pattern data is data of 8 bits vertically x 8 bits horizontally, the memory Addresses 0 to 4 of 1 are 8-bit data belonging to the 0th bit of the 0th row of the pattern data D D, . . .
If we sequentially associate data with pattern memory 1 by sequentially assigning 0' 1 to D4 and then assigning addresses 5 to 9 of memory 1 to the data belonging to the 1st bit of the 0th row of pattern data. , pattern data having the structure shown in FIG. 7 can be stored in the memory 1 shown in FIG.

(3) First conventional method Next, a pattern conversion method in a conventional pattern conversion circuit will be explained.

Conventional pattern conversion is, for example, disclosed in Japanese Patent Publication No. 61-32990.
This is realized by the device disclosed in the publication.

FIG. 8 schematically shows a pattern conversion method using this conventional device.

In this conventional method, pattern data is written/read from memory every m bits (eg, 8 bits). For example, when attempting to read data X written in the area shown by diagonal lines in FIG. 7 (so-called column read), data Do is first read into the register shown by 2 in FIG. 8. Next, the bit where address 0 intersects with the shaded area, that is, the first bit of data
Extracted by bit shift operation. This bit data Xl is stored in another register 3 by shifting one bit to the right.

After this, data D5 is read into the register 2. Data D. Similarly to the operation when reading data D5
Data X2 of the first bit of is stored in the register 3. When this reading is repeated up to address 35, all of the leading bit data Xl in the shaded area is read out and stored in register 3.

Note that if the diagonally shaded area to be read is not in the 0th column of the memory 1, the leftward shift in the register 2 is performed by the bit position to which the read target area belongs.

In this way, in this conventional method, column reading of data is performed by reading each row of memory 1 and shifting operations of registers 2 and 3, and it is possible to convert pattern data in 90@ direction and output it. It is.

(4) Second conventional method Furthermore, as a conventional pattern conversion method, there is a method as shown in FIG. 9, for example. It has been adopted.

In this conventional method, the 8-bit data read into the register 2 is once stored in the 8-bit×8-bit register 4. This reading and storing is repeated 8 times, and when the storage of data in the register 4 is completed, the 0 column of this register 4 is read out to the register 3, so that the shaded area shown in FIG. The stored 8-bit data is read.

[Problems to be Solved by the Invention] (1) Conventional Problems However, in the past, there were the following problems.

For example, in the first conventional method shown in FIG.
When processing by software using a CPU, fetch cycles are required for one instruction for reading data from memory and two instructions for shifting registers. In this case, reading the shaded area in FIG. 7 requires 3.times.8-24 fetch cycles for data conversion only, excluding address calculation.

Similarly, in the circuit according to the second conventional method shown in FIG. ) are required, and 2×8+1-17 fetch cycles are required to retrieve the data in the shaded area in FIG.

As described above, in the conventional pattern conversion method, the first problem is that pattern conversion requires a large amount of instruction fetch cycles.

, which places a heavy burden on the CPU and causes problems such as slow conversion speed.

(2) Purpose of the Invention The present invention was made to solve these problems, and the instruction fetch cycles are reduced, so the load on the CPU is reduced, and high-speed conversion can be realized. The purpose is to create a pattern conversion circuit.

[Means for Solving the Problem] In order to achieve the above object, the present invention provides a control means for issuing a read signal η n times to the memory in response to a column read command of a CPL, and a control means for generating a read signal by the control means. m bits of data to be addressed in the same column of pattern data according to the data, bit position specifying means for specifying the bit position, and address specifying means based on the readout signal. Selection of selecting and extracting data at a bit position specified by the bit position specifying means every time m-bit data is read from the memory, and outputting n-bit data extracted as a result of n times of reading from the memory. It is characterized by having a means.

[Function] In the pattern conversion circuit of the present invention, when a column read command is issued from the CPU, a read signal is sequentially supplied to the memory and the selection means n times from the control means. Furthermore, the pattern data stored in the memory is read out every m bits according to address designation. This addressing is performed so that data belonging to the same column of pattern data are sequentially read from the memory. In the selection means, among the m-bit data thus read out, the data at the bit position designated by the bit position designation means is selected and taken out, and after taking out n rows, n
Output as bit data.

Therefore, n-bit data is taken out with one column read request, and this data becomes data in the column direction of the pattern data.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

Components similar to those of the conventional example shown in FIGS. 6 to 9 are denoted by the same reference numerals, and description thereof will be omitted.

(1) Configuration of Embodiment FIG. 1 shows the configuration of a pattern conversion circuit according to this embodiment. The configuration of this embodiment will be explained below based on FIG.

(A) Overall configuration of the embodiment In this embodiment, the CPU 5 receives the memory read signal MRD a predetermined number of times (8 times) when reading a column of the memory 1.
A control unit 6 for emitting is connected. The control unit 6 sequentially updates the physical address S10ADH related to data readout during column readout, and updates the bit position BI
An address unit 7 for specifying TADR is connected. Further, the selector 8, which is controlled by the signal sIo issued by the control unit 6 and connected to the address unit 7 and the CPU 5, is connected to the address bus A-B.
It is connected to memory 1 via US9. On the other hand, the memory 1 is connected via a data bus D-BUS11 to a selection unit 1o that selects bit data based on the bit position BITADH during column reading. Further, this selection unit 10 is connected to the selector 12.

Further, the selection unit) 10 is configured such that the memory read signal MRD from the control unit 6 can be inputted to the selection unit 111m.
Connected to unit 6.

(B) Structure of Address Unit 7 FIG. 2 shows a detailed structure of the address unit 7 according to the feature of the present invention.

This address unit 7 includes a bit position register 13, a memory width register 14, and a selector 15 connected to the D-BUS 11, a physical address register 16 connected to the selector 15, and a physical address register 16 and a memory width register. The adder 17 is connected to the adder 14. Further, the adder 17 is connected to the input terminal of the selector 15.

(C) Structure of selection unit 10 FIG. 3 shows a detailed structure of the selection unit 10 according to the feature of the present invention.

The selection unit 10 is composed of a selector 18 that selects one bit of the data read from the memory 1 according to the bit position BITADR, and a shift register 19 that converts the output of the selector 18 from serial to parallel. .

(2) Operation of the Embodiment FIG. 4 schematically shows the operation of this embodiment, and FIG. 5 shows the operation of this embodiment in detail. Hereinafter, the operation of this embodiment will be explained based on FIGS. 4 and 5.

(A) Normal Mode First, the operation of writing/reading data without performing pattern conversion (normal mode operation) will be described.

In this case, control unit 6 sets signal 510 to rLJ level and generates memory write signal MWR or memory read signal MRD to memory 1 once in response to a memory write command or memory read command from CPU 5, as in the conventional case. When the signal SIO is at the rLJ level, the selector 8 selects the address from the CPU 5, and the selector 12 selects the output of the memory 1, so that normal write and read operations for the memory 1 are realized.

(B) Pattern Conversion Mode Next, the operation (pattern conversion mode operation) when performing pattern conversion, which is the original purpose function of the pattern conversion circuit, will be described.

FIG. 5 shows the operation timing in this embodiment in detail. In this figure, the dashed-dotted line represents the synchronous interlocking relationship between each signal, and the dashed-two dotted line represents the data shift. .

First, prior to the pattern conversion operation, values indicating the bit position to be read and the width of pattern data are set in the bit position register 13 and memory width register 14 by the normal mode operation described above. This setting is made by the control unit 6 according to the 5TATUS and address given from the CPU 5.
This is performed by I10 write signals 10W1 to 10W3 issued from.

Next, in order to execute a column read command, the CPU 5 sends a 5TATUS signal indicating an I10 read to the control unit 6.
(rLJ level) and a specific I10 address, the rise of the clock PCLK that comes immediately after the fall of 5TATUS to the rLJ level causes SIO to rise to a value representing column read. When SIO reaches the rHJ level, selector 8 selects physical address 5IOADH from address unit 7 and outputs it to memory 1. Furthermore, READY falls and a wait is applied to the CPU 5.

Next, the memory read signal MRD is issued from the control unit 6 eight times at every predetermined cycle (four cycles in the figure) of the clock PCLK.

When the memory read signal MRD is issued, the physical address S10AD output from the physical address register 14 is
Data D1 specified by R is read from memory 1. This data D is transmitted via D-BUSl 1,
A selection unit 10 is supplied.

The R selection unit 10 selects the memory 1 based on the bit position B ITADH specified by the address unit 7.
One bit of data (indicated by diagonal lines in FIG. 4) is selected from the data DI inputted from the input data DI.

This selection is made by the selector 18 shown in FIG. That is, the data D1 input to the selection unit 10 is first input to the selector 18 forming the selection unit 10.

The selector 18 also includes the address unit 7.
The bit position B ITADH set by the I10 write signal l0WI is input. In the selector 18, this bit position B ITADH
Only the data of the bit specified by is output from the Q terminal and input to the shift register 19.

In the shift register 19, the data input from the selector 18 is shifted by one bit each time the memory read signal MRD is supplied. for example,
As shown by the two-dot chain line in FIG. 5, every time the memory read signal MRD rises, the data on the D-BUS 11 is read into the 7th bit of the shift register 19, and is already stored in this shift register 19. The resulting bit data is sequentially shifted one bit to the left.

Furthermore, in the address unit 7, the physical address 5I
OADH is updated by adding the memory width.

At this time, the selector 15 selects the adder 1 by SIO.
7 is output to the physical address register 16,
The I10 write signal 10W4a is similarly output eight times from the control unit 6 in response to the generation of the memory read signal MRD.
, 10W5a, and 10W6a, the contents of the physical address register 16 are rewritten all at once.

In this embodiment, the memory width is 5, so the data read from the memory I by this updated physical address S I 0ADR is the address of the first read data DI, as shown in FIG. This is data obtained by adding 5 to D1, that is, data D1+5.

Similarly, regarding this data Di+5, the bit position BI
Based on TADR (bit data is selected and stored in the shift register 19).

Then, the data read from the memory 1 is sequentially updated at the physical address 5IO in the address unit 7.
When this is performed eight times based on ADH, the contents of the shift register 19 become the 8-bit data X extracted from the data related to the output from the memory 1 according to the specification of the BITADR.

In FIG. 5, prior to inputting the data DI+35 read out from the memory 1 for the eighth time to the selection unit 19, a READ signal is issued from the control unit 6.
Y is being launched. The rise of this READY,
It is latched by PCLK and releases the wait state of the CPU 5. When the weight is released, the CPU 5
5 Launch TATUS. The rise of this 5TATUS indicates that this 5TATUS indicates an I10 lead.
This means that it will no longer be in the US.

Then, at the timing after the data X is stored in the shift register 19, the R/W output from the control unit 6 indicates read, so this data Loaded.

Before long, SIO will be shut down. That is, the CP
U5 is addressably connected to memory 1 via said selector 8, and the circuit returns to normal mode operation.

In the figure, READY rises before 5TATUS, but this order may be reversed. If column reading is continued without changing the bit position BITADH, it is not necessary to reset the contents of registers 13 and 16. Further, the contents of the memory width register 14 do not need to be reset unless the data structure changes.

In the embodiment described above, the selection unit 10 uses the shift register 19 to serially/transmit data.
I was performing parallel conversion, but this shift register 19
An 8-bit memory can also be used instead. In this case, a write signal is required to specify the storage address in this 8-bit memory.

Alternatively, a read signal may be supplied to the shift register 19 to output the stored contents of the shift register 19 at a desired time.

In this embodiment, even if the address calculations excluded in the calculations for the conventional example are added, the instruction fetch cycle related to pattern conversion is still limited to the bit address register setting (
There are only 7 fetch cycles: memory width register setting (2 instructions), physical address register setting (3 instructions), and pattern conversion performed by I10 read (1 instruction). This value is significantly reduced compared to the conventional method shown in FIGS. 8 and 9 described above.

Therefore, in this embodiment, the number of instruction fetch cycles can be reduced, and the load on the CPU 5 can be reduced.

[Effects of the Invention] As explained above, according to the pattern conversion circuit of the present invention, it is possible to read a column of n-bit data with one column read instruction, reducing the instruction fetch cycle and reducing the load on the CPU. It is possible to obtain the effect of improving conversion speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a pattern conversion circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of an address unit in this embodiment, and FIG. 3 is a block diagram showing the structure of an address unit in this embodiment. FIG. 4 is an operating principle diagram showing the operating principle of this embodiment; FIG. 5 is a timing chart showing the operation timing of this embodiment; FIG. 6 is a memory The configuration diagrams illustrating the configuration of FIG. 7, FIG. 8, and FIG. 9 are as follows. 1 ... 5 ... 6 ... 7 ... 10 ... Dl ... X ... Memory CPU Control unit Address Unit Selection unit Data Output data Map showing the structure of pattern data, first Principle diagram showing the principle of the conventional method; Principle diagram showing the principle of the second conventional method.

Claims (1)

[Scope of Claims] In a pattern conversion circuit including a memory that stores pattern data of M columns and N rows and is accessed by a CPU every m bits, a read signal is sent to the memory in response to a column read command from the CPU. control means for generating a read signal repeatedly; addressing means for addressing m-bit data belonging to the same column of the pattern data in response to generation of a read signal by the control means; and bit position specifying means for specifying a bit position; Based on the readout signal,
Each time m-bit data addressed by the addressing means is read from the memory, data at a bit position designated by the bit position designating means is selected and retrieved, and data is read n times from the memory. A pattern conversion circuit comprising: selection means for outputting n-bit data extracted as a result of .