JPS63149751A - 直接メモリアクセス制御回路の半二重通信方式 - Google Patents

直接メモリアクセス制御回路の半二重通信方式

Info

Publication number
JPS63149751A
JPS63149751A JP61297149A JP29714986A JPS63149751A JP S63149751 A JPS63149751 A JP S63149751A JP 61297149 A JP61297149 A JP 61297149A JP 29714986 A JP29714986 A JP 29714986A JP S63149751 A JPS63149751 A JP S63149751A
Authority
JP
Japan
Prior art keywords
control circuit
serial communication
channel
processor
communication control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61297149A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0447345B2 (enrdf_load_stackoverflow
Inventor
Fumio Usui
文雄 臼井
Yuichi Goto
裕一 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61297149A priority Critical patent/JPS63149751A/ja
Publication of JPS63149751A publication Critical patent/JPS63149751A/ja
Publication of JPH0447345B2 publication Critical patent/JPH0447345B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
JP61297149A 1986-12-12 1986-12-12 直接メモリアクセス制御回路の半二重通信方式 Granted JPS63149751A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61297149A JPS63149751A (ja) 1986-12-12 1986-12-12 直接メモリアクセス制御回路の半二重通信方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61297149A JPS63149751A (ja) 1986-12-12 1986-12-12 直接メモリアクセス制御回路の半二重通信方式

Publications (2)

Publication Number Publication Date
JPS63149751A true JPS63149751A (ja) 1988-06-22
JPH0447345B2 JPH0447345B2 (enrdf_load_stackoverflow) 1992-08-03

Family

ID=17842834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61297149A Granted JPS63149751A (ja) 1986-12-12 1986-12-12 直接メモリアクセス制御回路の半二重通信方式

Country Status (1)

Country Link
JP (1) JPS63149751A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0447345B2 (enrdf_load_stackoverflow) 1992-08-03

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