JPS63136815A - 周期信号発生回路 - Google Patents

周期信号発生回路

Info

Publication number
JPS63136815A
JPS63136815A JP61284647A JP28464786A JPS63136815A JP S63136815 A JPS63136815 A JP S63136815A JP 61284647 A JP61284647 A JP 61284647A JP 28464786 A JP28464786 A JP 28464786A JP S63136815 A JPS63136815 A JP S63136815A
Authority
JP
Japan
Prior art keywords
circuit
gate circuit
level
signal
inversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61284647A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0473891B2 (en:Method
Inventor
Hirohisa Machida
町田　浩久
Takeo Nakabayashi
中林　竹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61284647A priority Critical patent/JPS63136815A/ja
Priority to DE19873740362 priority patent/DE3740362A1/de
Priority to US07/125,470 priority patent/US4827157A/en
Publication of JPS63136815A publication Critical patent/JPS63136815A/ja
Publication of JPH0473891B2 publication Critical patent/JPH0473891B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
JP61284647A 1986-11-28 1986-11-28 周期信号発生回路 Granted JPS63136815A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61284647A JPS63136815A (ja) 1986-11-28 1986-11-28 周期信号発生回路
DE19873740362 DE3740362A1 (de) 1986-11-28 1987-11-27 Schaltung zur periodischen signalerzeugung
US07/125,470 US4827157A (en) 1986-11-28 1987-11-27 Periodic signal generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61284647A JPS63136815A (ja) 1986-11-28 1986-11-28 周期信号発生回路

Publications (2)

Publication Number Publication Date
JPS63136815A true JPS63136815A (ja) 1988-06-09
JPH0473891B2 JPH0473891B2 (en:Method) 1992-11-24

Family

ID=17681173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61284647A Granted JPS63136815A (ja) 1986-11-28 1986-11-28 周期信号発生回路

Country Status (3)

Country Link
US (1) US4827157A (en:Method)
JP (1) JPS63136815A (en:Method)
DE (1) DE3740362A1 (en:Method)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01177711A (ja) * 1988-01-08 1989-07-14 Nec Corp ラッチ回路
US5041738A (en) * 1989-12-04 1991-08-20 Advanced Micro Devices, Inc. CMOS clock generator having an adjustable overlap voltage
US5120990A (en) * 1990-06-29 1992-06-09 Analog Devices, Inc. Apparatus for generating multiple phase clock signals and phase detector therefor
US5001369A (en) * 1990-07-02 1991-03-19 Micron Technology, Inc. Low noise output buffer circuit
US5124572A (en) * 1990-11-27 1992-06-23 Hewlett-Packard Co. VLSI clocking system using both overlapping and non-overlapping clocks
US5306962A (en) * 1990-11-27 1994-04-26 Hewlett-Packard Company Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing
US5325515A (en) * 1991-05-14 1994-06-28 Nec Electronics, Inc. Single-component memory controller utilizing asynchronous state machines
FR2696598B1 (fr) * 1992-10-01 1994-11-04 Sgs Thomson Microelectronics Circuit élévateur de tension de type pompe de charge avec oscillateur bootstrapé.
US5453707A (en) * 1993-01-13 1995-09-26 Nec Corporation Polyphase clock generation circuit
JP2959372B2 (ja) * 1993-12-03 1999-10-06 日本電気株式会社 クロック生成回路
JP3441780B2 (ja) * 1994-02-21 2003-09-02 日本テキサス・インスツルメンツ株式会社 クロック信号生成回路
US5818276A (en) * 1996-03-04 1998-10-06 Motorola, Inc. Non-overlapping clock generator circuit and method therefor
JP2994272B2 (ja) * 1996-08-23 1999-12-27 九州日本電気株式会社 多相クロック発生回路
US6362676B1 (en) * 1999-04-30 2002-03-26 Bae Systems Information And Electronic Systems Integration, Inc. Method and apparatus for a single event upset (SEU) tolerant clock splitter
US6629276B1 (en) * 1999-04-30 2003-09-30 Bae Systems Information And Electronic Systems Integration, Inc. Method and apparatus for a scannable hybrid flip flop
JP3428527B2 (ja) * 1999-09-29 2003-07-22 日本電気株式会社 波形整形回路
JP2002026265A (ja) * 2000-07-06 2002-01-25 Toshiba Lsi System Support Kk 半導体集積回路およびその配置設計方法
US6433603B1 (en) * 2000-08-14 2002-08-13 Sun Microsystems, Inc. Pulse-based high speed flop circuit
US6774683B2 (en) * 2002-08-13 2004-08-10 Analog Devices, Inc. Control loop for minimal tailnode excursion of differential switches
KR100526350B1 (ko) * 2003-08-23 2005-11-08 삼성전자주식회사 다상 클록신호 발생회로 및 방법
WO2022272029A1 (en) * 2021-06-25 2022-12-29 Ic Analytica, Llc Apparatus and method for implementing a scalable digital infrastructure for measuring ring oscillators

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787620A (en) * 1980-11-20 1982-06-01 Fujitsu Ltd Clock generating circuit
JPS59121697A (ja) * 1982-12-27 1984-07-13 Toshiba Corp シフトレジスタ
US4691122A (en) * 1985-03-29 1987-09-01 Advanced Micro Devices, Inc. CMOS D-type flip-flop circuits

Also Published As

Publication number Publication date
US4827157A (en) 1989-05-02
DE3740362C2 (en:Method) 1989-12-07
DE3740362A1 (de) 1988-06-09
JPH0473891B2 (en:Method) 1992-11-24

Similar Documents

Publication Publication Date Title
JPS63136815A (ja) 周期信号発生回路
JP2621993B2 (ja) フリップフロップ回路
US3976949A (en) Edge sensitive set-reset flip flop
JPS6236913A (ja) Ｃｍｏｓ　ｄ形フリツプフロツプ回路
JPS61191114A (ja) パルス発生回路
US3971960A (en) Flip-flop false output rejection circuit
JPS6216478B2 (en:Method)
KR0181720B1 (ko) 고속 동기형 논리 데이타 래치 장치
KR950014550B1 (ko) 반도체집적회로
US4469962A (en) High-speed MESFET circuits using depletion mode MESFET signal transmission gates
KR910006510B1 (ko) 반도체집적회로
US4420695A (en) Synchronous priority circuit
US12380941B2 (en) Power supply switching circuit and memory
US5454116A (en) Semiconductor integrated circuit with external clock signal and reduced data output delay
US5994936A (en) RS flip-flop with enable inputs
US6307416B1 (en) Integrated circuit for producing two output clock signals at levels which do not overlap in time
KR960008137B1 (ko) 반도체 소자의 노이즈 특성 강화회로
JPH04306013A (ja) ラッチ回路装置
JPS61264817A (ja) クロツク信号発生回路
JPH0355045B2 (en:Method)
JPH03102911A (ja) クロック信号発生回路
KR930001440B1 (ko) 클록 오우버래핑 방지회로
JP2878032B2 (ja) 半導体装置
JPS60123129A (ja) クロック作成回路
KR20020068623A (ko) 반도체 소자의 딜레이 회로